Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid

[pandora-kernel.git] / arch / arm / mach-u300 / include / mach / syscon.h

diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
index 7444f5c..6e84f07 100644 (file)
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -234,91 +234,6 @@
 #define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE       (0x0004)
 #define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE          (0x0002)
 #define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE          (0x0001)
-/* PAD MUX Control register 1 (LOW) 16bit (R/W) */
-#define U300_SYSCON_PMC1LR                                     (0x007C)
-#define U300_SYSCON_PMC1LR_MASK                                        (0xFFFF)
-#define U300_SYSCON_PMC1LR_CDI_MASK                            (0xC000)
-#define U300_SYSCON_PMC1LR_CDI_CDI                             (0x0000)
-#define U300_SYSCON_PMC1LR_CDI_EMIF                            (0x4000)
-#ifdef CONFIG_MACH_U300_BS335
-#define U300_SYSCON_PMC1LR_CDI_CDI2                            (0x8000)
-#define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO                  (0xC000)
-#elif CONFIG_MACH_U300_BS365
-#define U300_SYSCON_PMC1LR_CDI_GPIO                            (0x8000)
-#define U300_SYSCON_PMC1LR_CDI_WCDMA                           (0xC000)
-#endif
-#define U300_SYSCON_PMC1LR_PDI_MASK                            (0x3000)
-#define U300_SYSCON_PMC1LR_PDI_PDI                             (0x0000)
-#define U300_SYSCON_PMC1LR_PDI_EGG                             (0x1000)
-#define U300_SYSCON_PMC1LR_PDI_WCDMA                           (0x3000)
-#define U300_SYSCON_PMC1LR_MMCSD_MASK                          (0x0C00)
-#define U300_SYSCON_PMC1LR_MMCSD_MMCSD                         (0x0000)
-#define U300_SYSCON_PMC1LR_MMCSD_MSPRO                         (0x0400)
-#define U300_SYSCON_PMC1LR_MMCSD_DSP                           (0x0800)
-#define U300_SYSCON_PMC1LR_MMCSD_WCDMA                         (0x0C00)
-#define U300_SYSCON_PMC1LR_ETM_MASK                            (0x0300)
-#define U300_SYSCON_PMC1LR_ETM_ACC                             (0x0000)
-#define U300_SYSCON_PMC1LR_ETM_APP                             (0x0100)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK                     (0x00C0)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC                   (0x0000)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF                     (0x0040)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM                    (0x0080)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB               (0x00C0)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK                     (0x0030)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC                   (0x0000)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF                     (0x0010)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM                    (0x0020)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI                     (0x0030)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK                     (0x000C)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC                   (0x0000)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF                     (0x0004)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM                    (0x0008)
-#define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI                     (0x000C)
-#define U300_SYSCON_PMC1LR_EMIF_1_MASK                         (0x0003)
-#define U300_SYSCON_PMC1LR_EMIF_1_STATIC                       (0x0000)
-#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0                       (0x0001)
-#define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1                       (0x0002)
-#define U300_SYSCON_PMC1LR_EMIF_1                              (0x0003)
-/* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
-#define U300_SYSCON_PMC1HR                                     (0x007E)
-#define U300_SYSCON_PMC1HR_MASK                                        (0xFFFF)
-#define U300_SYSCON_PMC1HR_MISC_2_MASK                         (0xC000)
-#define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO                     (0x0000)
-#define U300_SYSCON_PMC1HR_MISC_2_MSPRO                                (0x4000)
-#define U300_SYSCON_PMC1HR_MISC_2_DSP                          (0x8000)
-#define U300_SYSCON_PMC1HR_MISC_2_AAIF                         (0xC000)
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK                     (0x3000)
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO                 (0x0000)
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF                     (0x1000)
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP                      (0x2000)
-#define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF                     (0x3000)
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK                     (0x0C00)
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO                 (0x0000)
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC                      (0x0400)
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP                      (0x0800)
-#define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF                     (0x0C00)
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK                   (0x0300)
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO               (0x0000)
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI                    (0x0100)
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF                   (0x0300)
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK                   (0x00C0)
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO               (0x0000)
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI                    (0x0040)
-#define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF                   (0x00C0)
-#define U300_SYSCON_PMC1HR_APP_SPI_2_MASK                      (0x0030)
-#define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO                  (0x0000)
-#define U300_SYSCON_PMC1HR_APP_SPI_2_SPI                       (0x0010)
-#define U300_SYSCON_PMC1HR_APP_SPI_2_DSP                       (0x0020)
-#define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF                      (0x0030)
-#define U300_SYSCON_PMC1HR_APP_UART0_2_MASK                    (0x000C)
-#define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO                        (0x0000)
-#define U300_SYSCON_PMC1HR_APP_UART0_2_UART0                   (0x0004)
-#define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS                 (0x0008)
-#define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF                    (0x000C)
-#define U300_SYSCON_PMC1HR_APP_UART0_1_MASK                    (0x0003)
-#define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO                        (0x0000)
-#define U300_SYSCON_PMC1HR_APP_UART0_1_UART0                   (0x0001)
-#define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF                    (0x0003)
 /* Step one for killing the applications system 16bit (-/W) */
 #define U300_SYSCON_KA1R                                       (0x0080)
 #define U300_SYSCON_KA1R_MASK                                  (0xFFFF)
@@ -357,57 +272,6 @@
 #define U300_SYSCON_PUCR_EMIF_1_16BIT_PU_ENABLE                        (0x0080)
 #define U300_SYSCON_PUCR_EMIF_1_8BIT_PU_ENABLE                 (0x0040)
 #define U300_SYSCON_PUCR_KEY_IN_PU_EN_MASK                     (0x003F)
-/* Padmux 2 control */
-#define U300_SYSCON_PMC2R                                      (0x100)
-#define U300_SYSCON_PMC2R_APP_MISC_0_MASK                      (0x00C0)
-#define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO                  (0x0000)
-#define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM                        (0x0040)
-#define U300_SYSCON_PMC2R_APP_MISC_0_MMC                       (0x0080)
-#define U300_SYSCON_PMC2R_APP_MISC_0_CDI2                      (0x00C0)
-#define U300_SYSCON_PMC2R_APP_MISC_1_MASK                      (0x0300)
-#define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO                  (0x0000)
-#define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM                        (0x0100)
-#define U300_SYSCON_PMC2R_APP_MISC_1_MMC                       (0x0200)
-#define U300_SYSCON_PMC2R_APP_MISC_1_CDI2                      (0x0300)
-#define U300_SYSCON_PMC2R_APP_MISC_2_MASK                      (0x0C00)
-#define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO                  (0x0000)
-#define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM                        (0x0400)
-#define U300_SYSCON_PMC2R_APP_MISC_2_MMC                       (0x0800)
-#define U300_SYSCON_PMC2R_APP_MISC_2_CDI2                      (0x0C00)
-#define U300_SYSCON_PMC2R_APP_MISC_3_MASK                      (0x3000)
-#define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO                  (0x0000)
-#define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM                        (0x1000)
-#define U300_SYSCON_PMC2R_APP_MISC_3_MMC                       (0x2000)
-#define U300_SYSCON_PMC2R_APP_MISC_3_CDI2                      (0x3000)
-#define U300_SYSCON_PMC2R_APP_MISC_4_MASK                      (0xC000)
-#define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO                  (0x0000)
-#define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM                        (0x4000)
-#define U300_SYSCON_PMC2R_APP_MISC_4_MMC                       (0x8000)
-#define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO                  (0xC000)
-/* TODO: More SYSCON registers missing */
-#define U300_SYSCON_PMC3R                                      (0x10c)
-#define U300_SYSCON_PMC3R_APP_MISC_11_MASK                     (0xc000)
-#define U300_SYSCON_PMC3R_APP_MISC_11_SPI                      (0x4000)
-#define U300_SYSCON_PMC3R_APP_MISC_10_MASK                     (0x3000)
-#define U300_SYSCON_PMC3R_APP_MISC_10_SPI                      (0x1000)
-/* TODO: Missing other configs */
-#define U300_SYSCON_PMC4R                                      (0x168)
-#define U300_SYSCON_PMC4R_APP_MISC_12_MASK                     (0x0003)
-#define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO                 (0x0000)
-#define U300_SYSCON_PMC4R_APP_MISC_13_MASK                     (0x000C)
-#define U300_SYSCON_PMC4R_APP_MISC_13_CDI                      (0x0000)
-#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA                     (0x0004)
-#define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2                    (0x0008)
-#define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO                 (0x000C)
-#define U300_SYSCON_PMC4R_APP_MISC_14_MASK                     (0x0030)
-#define U300_SYSCON_PMC4R_APP_MISC_14_CDI                      (0x0000)
-#define U300_SYSCON_PMC4R_APP_MISC_14_SMIA                     (0x0010)
-#define U300_SYSCON_PMC4R_APP_MISC_14_CDI2                     (0x0020)
-#define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO                 (0x0030)
-#define U300_SYSCON_PMC4R_APP_MISC_16_MASK                     (0x0300)
-#define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13              (0x0000)
-#define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS            (0x0100)
-#define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N      (0x0200)
 /* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
 #define U300_SYSCON_S0CCR                                      (0x120)
 #define U300_SYSCON_S0CCR_FIELD_MASK                           (0x43FF)