Merge branch 'for-linus' of git://oss.sgi.com/xfs/xfs

[pandora-kernel.git] / arch / arm / mach-spear3xx / include / mach / spear320.h

diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 940f0d8..8cfa83f 100644 (file)
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -36,31 +36,31 @@
 #define SPEAR320_SOC_CONFIG_BASE       UL(0xB3000000)
 
 /* Interrupt registers offsets and masks */
-#define INT_STS_MASK_REG               0x04
-#define INT_CLR_MASK_REG               0x04
-#define INT_ENB_MASK_REG               0x08
-#define GPIO_IRQ_MASK                  (1 << 0)
-#define I2S_PLAY_IRQ_MASK              (1 << 1)
-#define I2S_REC_IRQ_MASK               (1 << 2)
-#define EMI_IRQ_MASK                   (1 << 7)
-#define CLCD_IRQ_MASK                  (1 << 8)
-#define SPP_IRQ_MASK                   (1 << 9)
-#define SDHCI_IRQ_MASK                 (1 << 10)
-#define CAN_U_IRQ_MASK                 (1 << 11)
-#define CAN_L_IRQ_MASK                 (1 << 12)
-#define UART1_IRQ_MASK                 (1 << 13)
-#define UART2_IRQ_MASK                 (1 << 14)
-#define SSP1_IRQ_MASK                  (1 << 15)
-#define SSP2_IRQ_MASK                  (1 << 16)
-#define SMII0_IRQ_MASK                 (1 << 17)
-#define MII1_SMII1_IRQ_MASK            (1 << 18)
-#define WAKEUP_SMII0_IRQ_MASK          (1 << 19)
-#define WAKEUP_MII1_SMII1_IRQ_MASK     (1 << 20)
-#define I2C1_IRQ_MASK                  (1 << 21)
+#define SPEAR320_INT_STS_MASK_REG              0x04
+#define SPEAR320_INT_CLR_MASK_REG              0x04
+#define SPEAR320_INT_ENB_MASK_REG              0x08
+#define SPEAR320_GPIO_IRQ_MASK                 (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK             (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK              (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK                  (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK                 (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK                  (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK                        (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK                        (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK                        (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK                        (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK                        (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK                 (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK                 (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK                        (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK           (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK         (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK    (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK                 (1 << 21)
 
-#define SHIRQ_RAS1_MASK                        0x000380
-#define SHIRQ_RAS3_MASK                        0x000007
-#define SHIRQ_INTRCOMM_RAS_MASK                0x3FF800
+#define SPEAR320_SHIRQ_RAS1_MASK               0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK               0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK       0x3FF800
 
 #endif /* __MACH_SPEAR320_H */