ARM: mach-shmobile: sh7372 A3SM support

[pandora-kernel.git] / arch / arm / mach-shmobile / sleep-sh7372.S

diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index dedf612..d365842 100644 (file)
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -36,7 +36,58 @@
 
        .align  12
        .text
-       .global sh7372_resume_core_standby
-sh7372_resume_core_standby:
+       .global sh7372_resume_core_standby_a3sm
+sh7372_resume_core_standby_a3sm:
        ldr     pc, 1f
 1:     .long   cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
+
+       .global sh7372_do_idle_a3sm
+sh7372_do_idle_a3sm:
+       /*
+        * Clear the SCTLR.C bit to prevent further data cache
+        * allocation. Clearing SCTLR.C would make all the data accesses
+        * strongly ordered and would not hit the cache.
+        */
+       mrc     p15, 0, r0, c1, c0, 0
+       bic     r0, r0, #(1 << 2)       @ Disable the C bit
+       mcr     p15, 0, r0, c1, c0, 0
+       isb
+
+       /* disable L2 cache in the aux control register */
+       mrc     p15, 0, r10, c1, c0, 1
+       bic     r10, r10, #2
+       mcr     p15, 0, r10, c1, c0, 1
+
+       /*
+        * Invalidate data cache again.
+        */
+       ldr     r1, kernel_flush
+       blx     r1
+       /*
+        * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+        * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+        * This sequence switches back to ARM.  Note that .align may insert a
+        * nop: bx pc needs to be word-aligned in order to work.
+        */
+ THUMB(        .thumb          )
+ THUMB(        .align          )
+ THUMB(        bx      pc      )
+ THUMB(        nop             )
+       .arm
+
+       /* Data memory barrier and Data sync barrier */
+       dsb
+       dmb
+
+#define SPDCR 0xe6180008
+#define A3SM (1 << 12)
+
+       /* A3SM power down */
+       ldr     r0, =SPDCR
+       ldr     r1, =A3SM
+       str     r1, [r0]
+1:
+       b      1b
+
+kernel_flush:
+       .word v7_flush_dcache_all