Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle...

[pandora-kernel.git] / arch / arm / mach-s5pv210 / include / mach / regs-clock.h

diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 499aef7..ebaabe0 100644 (file)
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -25,6 +25,7 @@
 #define S5P_APLL_CON           S5P_CLKREG(0x100)
 #define S5P_MPLL_CON           S5P_CLKREG(0x108)
 #define S5P_EPLL_CON           S5P_CLKREG(0x110)
+#define S5P_EPLL_CON1          S5P_CLKREG(0x114)
 #define S5P_VPLL_CON           S5P_CLKREG(0x120)
 
 #define S5P_CLK_SRC0           S5P_CLKREG(0x200)
@@ -67,11 +68,28 @@
 #define S5P_CLKGATE_BUS1       S5P_CLKREG(0x488)
 #define S5P_CLK_OUT            S5P_CLKREG(0x500)
 
+/* DIV/MUX STATUS */
+#define S5P_CLKDIV_STAT0       S5P_CLKREG(0x1000)
+#define S5P_CLKDIV_STAT1       S5P_CLKREG(0x1004)
+#define S5P_CLKMUX_STAT0       S5P_CLKREG(0x1100)
+#define S5P_CLKMUX_STAT1       S5P_CLKREG(0x1104)
+
 /* CLKSRC0 */
-#define S5P_CLKSRC0_MUX200_MASK                (0x1<<16)
+#define S5P_CLKSRC0_MUX200_SHIFT       (16)
+#define S5P_CLKSRC0_MUX200_MASK                (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
 #define S5P_CLKSRC0_MUX166_MASK                (0x1<<20)
 #define S5P_CLKSRC0_MUX133_MASK                (0x1<<24)
 
+/* CLKSRC2 */
+#define S5P_CLKSRC2_G3D_SHIFT           (0)
+#define S5P_CLKSRC2_G3D_MASK            (0x3 << S5P_CLKSRC2_G3D_SHIFT)
+#define S5P_CLKSRC2_MFC_SHIFT           (4)
+#define S5P_CLKSRC2_MFC_MASK            (0x3 << S5P_CLKSRC2_MFC_SHIFT)
+
+/* CLKSRC6*/
+#define S5P_CLKSRC6_ONEDRAM_SHIFT       (24)
+#define S5P_CLKSRC6_ONEDRAM_MASK        (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT)
+
 /* CLKDIV0 */
 #define S5P_CLKDIV0_APLL_SHIFT         (0)
 #define S5P_CLKDIV0_APLL_MASK          (0x7 << S5P_CLKDIV0_APLL_SHIFT)
@@ -90,12 +108,24 @@
 #define S5P_CLKDIV0_PCLK66_SHIFT       (28)
 #define S5P_CLKDIV0_PCLK66_MASK                (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
 
+/* CLKDIV2 */
+#define S5P_CLKDIV2_G3D_SHIFT           (0)
+#define S5P_CLKDIV2_G3D_MASK            (0xF << S5P_CLKDIV2_G3D_SHIFT)
+#define S5P_CLKDIV2_MFC_SHIFT           (4)
+#define S5P_CLKDIV2_MFC_MASK            (0xF << S5P_CLKDIV2_MFC_SHIFT)
+
+/* CLKDIV6 */
+#define S5P_CLKDIV6_ONEDRAM_SHIFT       (28)
+#define S5P_CLKDIV6_ONEDRAM_MASK        (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
+
 #define S5P_SWRESET            S5P_CLKREG(0x2000)
 
+#define S5P_ARM_MCS_CON                S5P_CLKREG(0x6100)
+
 /* Registers related to power management */
 #define S5P_PWR_CFG            S5P_CLKREG(0xC000)
 #define S5P_EINT_WAKEUP_MASK   S5P_CLKREG(0xC004)
-#define S5P_WAKEUP_MASK        S5P_CLKREG(0xC008)
+#define S5P_WAKEUP_MASK                S5P_CLKREG(0xC008)
 #define S5P_PWR_MODE           S5P_CLKREG(0xC00C)
 #define S5P_NORMAL_CFG         S5P_CLKREG(0xC010)
 #define S5P_IDLE_CFG           S5P_CLKREG(0xC020)
@@ -159,8 +189,11 @@
 #define S5P_SLEEP_CFG_USBOSC_EN                (1 << 1)
 
 /* OTHERS Resgister */
+#define S5P_OTHERS_RET_IO              (1 << 31)
+#define S5P_OTHERS_RET_CF              (1 << 30)
+#define S5P_OTHERS_RET_MMC             (1 << 29)
+#define S5P_OTHERS_RET_UART            (1 << 28)
 #define S5P_OTHERS_USB_SIG_MASK                (1 << 16)
-#define S5P_OTHERS_MIPI_DPHY_EN                (1 << 28)
 
 /* MIPI */
 #define S5P_MIPI_DPHY_EN               (3)