Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/ickle...
[pandora-kernel.git] / arch / arm / mach-s5p64x0 / clock-s5p6440.c
index f93dcd8..e4883dc 100644 (file)
@@ -79,13 +79,16 @@ static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
        __raw_writel(epll_con, S5P64X0_EPLL_CON);
        __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
 
+       printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
+                       clk->rate, rate);
+
        clk->rate = rate;
 
        return 0;
 }
 
 static struct clk_ops s5p6440_epll_ops = {
-       .get_rate = s5p64x0_epll_get_rate,
+       .get_rate = s5p_epll_get_rate,
        .set_rate = s5p6440_epll_set_rate,
 };
 
@@ -149,6 +152,12 @@ static struct clk init_clocks_disable[] = {
                .parent         = &clk_hclk.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 8),
+       }, {
+               .name           = "pdma",
+               .id             = -1,
+               .parent         = &clk_hclk_low.clk,
+               .enable         = s5p64x0_hclk0_ctrl,
+               .ctrlbit        = (1 << 12),
        }, {
                .name           = "hsmmc",
                .id             = 0,
@@ -330,12 +339,6 @@ static struct clk init_clocks[] = {
                .parent         = &clk_hclk.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 21),
-       }, {
-               .name           = "dma",
-               .id             = -1,
-               .parent         = &clk_hclk_low.clk,
-               .enable         = s5p64x0_hclk0_ctrl,
-               .ctrlbit        = (1 << 12),
        }, {
                .name           = "uart",
                .id             = 0,
@@ -548,7 +551,7 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
 
        /* Set S5P6440 functions for clk_fout_epll */
 
-       clk_fout_epll.enable = s5p64x0_epll_enable;
+       clk_fout_epll.enable = s5p_epll_enable;
        clk_fout_epll.ops = &s5p6440_epll_ops;
 
        clk_48m.enable = s5p64x0_clk48m_ctrl;