Merge branch 'next/fixes2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/linux...

[pandora-kernel.git] / arch / arm / mach-s5p64x0 / clock-s5p6440.c

diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 9f12c2e..0e9cd30 100644 (file)
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = {
 static struct clksrc_clk clk_hclk = {
        .clk    = {
                .name           = "clk_hclk",
-               .id             = -1,
                .parent         = &clk_armclk.clk,
        },
        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
@@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = {
 static struct clksrc_clk clk_pclk = {
        .clk    = {
                .name           = "clk_pclk",
-               .id             = -1,
                .parent         = &clk_hclk.clk,
        },
        .reg_div        = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = {
 static struct clksrc_clk clk_hclk_low = {
        .clk    = {
                .name           = "clk_hclk_low",
-               .id             = -1,
        },
        .sources        = &clkset_hclk_low,
        .reg_src        = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
@@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = {
 static struct clksrc_clk clk_pclk_low = {
        .clk    = {
                .name           = "clk_pclk_low",
-               .id             = -1,
                .parent         = &clk_hclk_low.clk,
        },
        .reg_div        = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = {
 static struct clk init_clocks_off[] = {
        {
                .name           = "nand",
-               .id             = -1,
                .parent         = &clk_hclk.clk,
                .enable         = s5p64x0_mem_ctrl,
                .ctrlbit        = (1 << 2),
        }, {
                .name           = "post",
-               .id             = -1,
                .parent         = &clk_hclk_low.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 5)
        }, {
                .name           = "2d",
-               .id             = -1,
                .parent         = &clk_hclk.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 8),
        }, {
                .name           = "pdma",
-               .id             = -1,
                .parent         = &clk_hclk_low.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 12),
        }, {
                .name           = "hsmmc",
-               .id             = 0,
+               .devname        = "s3c-sdhci.0",
                .parent         = &clk_hclk_low.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 17),
        }, {
                .name           = "hsmmc",
-               .id             = 1,
+               .devname        = "s3c-sdhci.1",
                .parent         = &clk_hclk_low.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 18),
        }, {
                .name           = "hsmmc",
-               .id             = 2,
+               .devname        = "s3c-sdhci.2",
                .parent         = &clk_hclk_low.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 19),
        }, {
                .name           = "otg",
-               .id             = -1,
                .parent         = &clk_hclk_low.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 20)
        }, {
                .name           = "irom",
-               .id             = -1,
                .parent         = &clk_hclk.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 25),
        }, {
                .name           = "lcd",
-               .id             = -1,
                .parent         = &clk_hclk_low.clk,
                .enable         = s5p64x0_hclk1_ctrl,
                .ctrlbit        = (1 << 1),
        }, {
                .name           = "hclk_fimgvg",
-               .id             = -1,
                .parent         = &clk_hclk.clk,
                .enable         = s5p64x0_hclk1_ctrl,
                .ctrlbit        = (1 << 2),
        }, {
                .name           = "tsi",
-               .id             = -1,
                .parent         = &clk_hclk_low.clk,
                .enable         = s5p64x0_hclk1_ctrl,
                .ctrlbit        = (1 << 0),
        }, {
                .name           = "watchdog",
-               .id             = -1,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 5),
        }, {
                .name           = "rtc",
-               .id             = -1,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 6),
        }, {
                .name           = "timers",
-               .id             = -1,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 7),
        }, {
                .name           = "pcm",
-               .id             = -1,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 8),
        }, {
                .name           = "adc",
-               .id             = -1,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 12),
        }, {
                .name           = "i2c",
-               .id             = -1,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 17),
        }, {
                .name           = "spi",
-               .id             = 0,
+               .devname        = "s3c64xx-spi.0",
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 21),
        }, {
                .name           = "spi",
-               .id             = 1,
+               .devname        = "s3c64xx-spi.1",
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 22),
        }, {
                .name           = "gps",
-               .id             = -1,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 25),
        }, {
                .name           = "iis",
-               .id             = 0,
+               .devname        = "samsung-i2s.0",
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 26),
        }, {
                .name           = "dsim",
-               .id             = -1,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 28),
        }, {
                .name           = "etm",
-               .id             = -1,
                .parent         = &clk_pclk.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 29),
        }, {
                .name           = "dmc0",
-               .id             = -1,
                .parent         = &clk_pclk.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 30),
        }, {
                .name           = "pclk_fimgvg",
-               .id             = -1,
                .parent         = &clk_pclk.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 31),
        }, {
                .name           = "sclk_spi_48",
-               .id             = 0,
+               .devname        = "s3c64xx-spi.0",
                .parent         = &clk_48m,
                .enable         = s5p64x0_sclk_ctrl,
                .ctrlbit        = (1 << 22),
        }, {
                .name           = "sclk_spi_48",
-               .id             = 1,
+               .devname        = "s3c64xx-spi.1",
                .parent         = &clk_48m,
                .enable         = s5p64x0_sclk_ctrl,
                .ctrlbit        = (1 << 23),
        }, {
                .name           = "mmc_48m",
-               .id             = 0,
+               .devname        = "s3c-sdhci.0",
                .parent         = &clk_48m,
                .enable         = s5p64x0_sclk_ctrl,
                .ctrlbit        = (1 << 27),
        }, {
                .name           = "mmc_48m",
-               .id             = 1,
+               .devname        = "s3c-sdhci.1",
                .parent         = &clk_48m,
                .enable         = s5p64x0_sclk_ctrl,
                .ctrlbit        = (1 << 28),
        }, {
                .name           = "mmc_48m",
-               .id             = 2,
+               .devname        = "s3c-sdhci.2",
                .parent         = &clk_48m,
                .enable         = s5p64x0_sclk_ctrl,
                .ctrlbit        = (1 << 29),
@@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = {
 static struct clk init_clocks[] = {
        {
                .name           = "intc",
-               .id             = -1,
                .parent         = &clk_hclk.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 1),
        }, {
                .name           = "mem",
-               .id             = -1,
                .parent         = &clk_hclk.clk,
                .enable         = s5p64x0_hclk0_ctrl,
                .ctrlbit        = (1 << 21),
        }, {
                .name           = "uart",
-               .id             = 0,
+               .devname        = "s3c6400-uart.0",
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 1),
        }, {
                .name           = "uart",
-               .id             = 1,
+               .devname        = "s3c6400-uart.1",
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 2),
        }, {
                .name           = "uart",
-               .id             = 2,
+               .devname        = "s3c6400-uart.2",
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 3),
        }, {
                .name           = "uart",
-               .id             = 3,
+               .devname        = "s3c6400-uart.3",
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 4),
        }, {
                .name           = "gpio",
-               .id             = -1,
                .parent         = &clk_pclk_low.clk,
                .enable         = s5p64x0_pclk_ctrl,
                .ctrlbit        = (1 << 18),
@@ -374,12 +347,10 @@ static struct clk init_clocks[] = {
 
 static struct clk clk_iis_cd_v40 = {
        .name           = "iis_cdclk_v40",
-       .id             = -1,
 };
 
 static struct clk clk_pcm_cd = {
        .name           = "pcm_cdclk",
-       .id             = -1,
 };
 
 static struct clk *clkset_group1_list[] = {
@@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = {
        {
                .clk    = {
                        .name           = "sclk_mmc",
-                       .id             = 0,
+                       .devname        = "s3c-sdhci.0",
                        .ctrlbit        = (1 << 24),
                        .enable         = s5p64x0_sclk_ctrl,
                },
@@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "sclk_mmc",
-                       .id             = 1,
+                       .devname        = "s3c-sdhci.1",
                        .ctrlbit        = (1 << 25),
                        .enable         = s5p64x0_sclk_ctrl,
                },
@@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "sclk_mmc",
-                       .id             = 2,
+                       .devname        = "s3c-sdhci.2",
                        .ctrlbit        = (1 << 26),
                        .enable         = s5p64x0_sclk_ctrl,
                },
@@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "uclk1",
-                       .id             = -1,
                        .ctrlbit        = (1 << 5),
                        .enable         = s5p64x0_sclk_ctrl,
                },
@@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "sclk_spi",
-                       .id             = 0,
+                       .devname        = "s3c64xx-spi.0",
                        .ctrlbit        = (1 << 20),
                        .enable         = s5p64x0_sclk_ctrl,
                },
@@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "sclk_spi",
-                       .id             = 1,
+                       .devname        = "s3c64xx-spi.1",
                        .ctrlbit        = (1 << 21),
                        .enable         = s5p64x0_sclk_ctrl,
                },
@@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "sclk_post",
-                       .id             = -1,
                        .ctrlbit        = (1 << 10),
                        .enable         = s5p64x0_sclk_ctrl,
                },
@@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "sclk_dispcon",
-                       .id             = -1,
                        .ctrlbit        = (1 << 1),
                        .enable         = s5p64x0_sclk1_ctrl,
                },
@@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "sclk_fimgvg",
-                       .id             = -1,
                        .ctrlbit        = (1 << 2),
                        .enable         = s5p64x0_sclk1_ctrl,
                },
@@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = {
        }, {
                .clk    = {
                        .name           = "sclk_audio2",
-                       .id             = -1,
                        .ctrlbit        = (1 << 11),
                        .enable         = s5p64x0_sclk_ctrl,
                },