Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...

[pandora-kernel.git] / arch / arm / mach-s3c64xx / clock.c

diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 9b587e2..2ac2e7d 100644 (file)
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -151,6 +151,14 @@ static struct clk init_clocks_disable[] = {
                .enable         = s3c64xx_pclk_ctrl,
                .ctrlbit        = S3C_CLKCON_PCLK_IIS1,
        }, {
+#ifdef CONFIG_CPU_S3C6410
+               .name           = "iis",
+               .id             = -1,  /* There's only one IISv4 port */
+               .parent         = &clk_p,
+               .enable         = s3c64xx_pclk_ctrl,
+               .ctrlbit        = S3C6410_CLKCON_PCLK_IIS2,
+       }, {
+#endif
                .name           = "spi",
                .id             = 0,
                .parent         = &clk_p,
@@ -748,19 +756,29 @@ static struct clk *clks1[] __initdata = {
        &clk_arm,
 };
 
+static struct clk *clks[] __initdata = {
+       &clk_ext,
+       &clk_epll,
+       &clk_27m,
+       &clk_48m,
+       &clk_h2,
+};
+
 /**
- * s3c6400_register_clocks - register clocks for s3c6400 and above
- * @armclk_divlimit: Divisor mask for ARMCLK
+ * s3c64xx_register_clocks - register clocks for s3c6400 and s3c6410
+ * @xtal: The rate for the clock crystal feeding the PLLs.
+ * @armclk_divlimit: Divisor mask for ARMCLK.
  *
- * Register the clocks for the S3C6400 and above SoC range, such
- * as ARMCLK and the clocks which have divider chains attached.
+ * Register the clocks for the S3C6400 and S3C6410 SoC range, such
+ * as ARMCLK as well as the necessary parent clocks.
  *
  * This call does not setup the clocks, which is left to the
  * s3c6400_setup_clocks() call which may be needed by the cpufreq
  * or resume code to re-set the clocks if the bootloader has changed
  * them.
  */
-void __init s3c6400_register_clocks(unsigned armclk_divlimit)
+void __init s3c64xx_register_clocks(unsigned long xtal, 
+                                   unsigned armclk_divlimit)
 {
        struct clk *clkp;
        int ret;
@@ -768,33 +786,9 @@ void __init s3c6400_register_clocks(unsigned armclk_divlimit)
 
        armclk_mask = armclk_divlimit;
 
-       for (ptr = 0; ptr < ARRAY_SIZE(clks1); ptr++) {
-               clkp = clks1[ptr];
-               ret = s3c24xx_register_clock(clkp);
-               if (ret < 0) {
-                       printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                              clkp->name, ret);
-               }
-       }
-
-       s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
-}
-
-static struct clk *clks[] __initdata = {
-       &clk_ext,
-       &clk_epll,
-       &clk_27m,
-       &clk_48m,
-       &clk_h2,
-};
-
-void __init s3c64xx_register_clocks(void)
-{
-       struct clk *clkp;
-       int ret;
-       int ptr;
-
+       s3c24xx_register_baseclocks(xtal);
        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+
        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 
        clkp = init_clocks_disable;
@@ -809,5 +803,7 @@ void __init s3c64xx_register_clocks(void)
                (clkp->enable)(clkp, 0);
        }
 
+       s3c24xx_register_clocks(clks1, ARRAY_SIZE(clks1));
+       s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
        s3c_pwmclk_init();
 }