Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[pandora-kernel.git] / arch / arm / mach-s3c2410 / irq.c
index 973a5fe..cd6139b 100644 (file)
@@ -86,7 +86,7 @@ unsigned long s3c_irqwake_intmask     = 0xffffffffL;
 unsigned long s3c_irqwake_eintallow    = 0x0000fff0L;
 unsigned long s3c_irqwake_eintmask     = 0xffffffffL;
 
-static int
+int
 s3c_irq_wake(unsigned int irqno, unsigned int state)
 {
        unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
@@ -184,20 +184,16 @@ struct irqchip s3c_irq_level_chip = {
        .ack       = s3c_irq_maskack,
        .mask      = s3c_irq_mask,
        .unmask    = s3c_irq_unmask,
-       .wake      = s3c_irq_wake
+       .set_wake          = s3c_irq_wake
 };
 
 static struct irqchip s3c_irq_chip = {
        .ack       = s3c_irq_ack,
        .mask      = s3c_irq_mask,
        .unmask    = s3c_irq_unmask,
-       .wake      = s3c_irq_wake
+       .set_wake  = s3c_irq_wake
 };
 
-/* S3C2410_EINTMASK
- * S3C2410_EINTPEND
- */
-
 static void
 s3c_irqext_mask(unsigned int irqno)
 {
@@ -205,9 +201,9 @@ s3c_irqext_mask(unsigned int irqno)
 
        irqno -= EXTINT_OFF;
 
-       mask = __raw_readl(S3C2410_EINTMASK);
+       mask = __raw_readl(S3C24XX_EINTMASK);
        mask |= ( 1UL << irqno);
-       __raw_writel(mask, S3C2410_EINTMASK);
+       __raw_writel(mask, S3C24XX_EINTMASK);
 
        if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
                /* check to see if all need masking */
@@ -232,11 +228,11 @@ s3c_irqext_ack(unsigned int irqno)
        bit = 1UL << (irqno - EXTINT_OFF);
 
 
-       mask = __raw_readl(S3C2410_EINTMASK);
+       mask = __raw_readl(S3C24XX_EINTMASK);
 
-       __raw_writel(bit, S3C2410_EINTPEND);
+       __raw_writel(bit, S3C24XX_EINTPEND);
 
-       req = __raw_readl(S3C2410_EINTPEND);
+       req = __raw_readl(S3C24XX_EINTPEND);
        req &= ~mask;
 
        /* not sure if we should be acking the parent irq... */
@@ -257,14 +253,14 @@ s3c_irqext_unmask(unsigned int irqno)
 
        irqno -= EXTINT_OFF;
 
-       mask = __raw_readl(S3C2410_EINTMASK);
+       mask = __raw_readl(S3C24XX_EINTMASK);
        mask &= ~( 1UL << irqno);
-       __raw_writel(mask, S3C2410_EINTMASK);
+       __raw_writel(mask, S3C24XX_EINTMASK);
 
        s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
 }
 
-static int
+int
 s3c_irqext_type(unsigned int irq, unsigned int type)
 {
        void __iomem *extint_reg;
@@ -275,28 +271,28 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
        if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
        {
                gpcon_reg = S3C2410_GPFCON;
-               extint_reg = S3C2410_EXTINT0;
+               extint_reg = S3C24XX_EXTINT0;
                gpcon_offset = (irq - IRQ_EINT0) * 2;
                extint_offset = (irq - IRQ_EINT0) * 4;
        }
        else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
        {
                gpcon_reg = S3C2410_GPFCON;
-               extint_reg = S3C2410_EXTINT0;
+               extint_reg = S3C24XX_EXTINT0;
                gpcon_offset = (irq - (EXTINT_OFF)) * 2;
                extint_offset = (irq - (EXTINT_OFF)) * 4;
        }
        else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
        {
                gpcon_reg = S3C2410_GPGCON;
-               extint_reg = S3C2410_EXTINT1;
+               extint_reg = S3C24XX_EXTINT1;
                gpcon_offset = (irq - IRQ_EINT8) * 2;
                extint_offset = (irq - IRQ_EINT8) * 4;
        }
        else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
        {
                gpcon_reg = S3C2410_GPGCON;
-               extint_reg = S3C2410_EXTINT2;
+               extint_reg = S3C24XX_EXTINT2;
                gpcon_offset = (irq - IRQ_EINT8) * 2;
                extint_offset = (irq - IRQ_EINT16) * 4;
        } else
@@ -350,16 +346,16 @@ static struct irqchip s3c_irqext_chip = {
        .mask       = s3c_irqext_mask,
        .unmask     = s3c_irqext_unmask,
        .ack        = s3c_irqext_ack,
-       .type       = s3c_irqext_type,
-       .wake       = s3c_irqext_wake
+       .set_type    = s3c_irqext_type,
+       .set_wake    = s3c_irqext_wake
 };
 
 static struct irqchip s3c_irq_eint0t4 = {
        .ack       = s3c_irq_ack,
        .mask      = s3c_irq_mask,
        .unmask    = s3c_irq_unmask,
-       .wake      = s3c_irq_wake,
-       .type      = s3c_irqext_type,
+       .set_wake  = s3c_irq_wake,
+       .set_type  = s3c_irqext_type,
 };
 
 /* mask values for the parent registers for each of the interrupt types */
@@ -496,11 +492,11 @@ static void s3c_irq_demux_adc(unsigned int irq,
        if (subsrc != 0) {
                if (subsrc & 1) {
                        mydesc = irq_desc + IRQ_TC;
-                       mydesc->handle( IRQ_TC, mydesc, regs);
+                       desc_handle_irq(IRQ_TC, mydesc, regs);
                }
                if (subsrc & 2) {
                        mydesc = irq_desc + IRQ_ADC;
-                       mydesc->handle(IRQ_ADC, mydesc, regs);
+                       desc_handle_irq(IRQ_ADC, mydesc, regs);
                }
        }
 }
@@ -529,17 +525,17 @@ static void s3c_irq_demux_uart(unsigned int start,
                desc = irq_desc + start;
 
                if (subsrc & 1)
-                       desc->handle(start, desc, regs);
+                       desc_handle_irq(start, desc, regs);
 
                desc++;
 
                if (subsrc & 2)
-                       desc->handle(start+1, desc, regs);
+                       desc_handle_irq(start+1, desc, regs);
 
                desc++;
 
                if (subsrc & 4)
-                       desc->handle(start+2, desc, regs);
+                       desc_handle_irq(start+2, desc, regs);
        }
 }
 
@@ -572,6 +568,23 @@ s3c_irq_demux_uart2(unsigned int irq,
        s3c_irq_demux_uart(IRQ_S3CUART_RX2, regs);
 }
 
+static void
+s3c_irq_demux_extint(unsigned int irq,
+                    struct irqdesc *desc,
+                    struct pt_regs *regs)
+{
+       unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
+       unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
+
+       eintpnd &= ~eintmsk;
+
+       if (eintpnd) {
+               irq = fls(eintpnd);
+               irq += (IRQ_EINT4 - (4 + 1));
+
+               desc_handle_irq(irq, irq_desc + irq, regs);
+       }
+}
 
 /* s3c24xx_init_irq
  *
@@ -591,12 +604,12 @@ void __init s3c24xx_init_irq(void)
 
        last = 0;
        for (i = 0; i < 4; i++) {
-               pend = __raw_readl(S3C2410_EINTPEND);
+               pend = __raw_readl(S3C24XX_EINTPEND);
 
                if (pend == 0 || pend == last)
                        break;
 
-               __raw_writel(pend, S3C2410_EINTPEND);
+               __raw_writel(pend, S3C24XX_EINTPEND);
                printk("irq: clearing pending ext status %08x\n", (int)pend);
                last = pend;
        }
@@ -630,12 +643,14 @@ void __init s3c24xx_init_irq(void)
 
        irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
 
-       for (irqno = IRQ_BATT_FLT; irqno <= IRQ_ADCPARENT; irqno++) {
+       for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
                /* set all the s3c2410 internal irqs */
 
                switch (irqno) {
                        /* deal with the special IRQs (cascaded) */
 
+               case IRQ_EINT4t7:
+               case IRQ_EINT8t23:
                case IRQ_UART0:
                case IRQ_UART1:
                case IRQ_UART2:
@@ -659,12 +674,14 @@ void __init s3c24xx_init_irq(void)
 
        /* setup the cascade irq handlers */
 
+       set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint);
+       set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint);
+
        set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
        set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
        set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
        set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
 
-
        /* external interrupts */
 
        for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {