- setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
-}
-
-void __init orion5x_setup_eth_wins(void)
-{
- int i;
-
- /*
- * First, disable and clear windows
- */
- for (i = 0; i < ETH_MAX_WIN; i++) {
- orion5x_write(ETH_WIN_BASE(i), 0);
- orion5x_write(ETH_WIN_SIZE(i), 0);
- orion5x_setbits(ETH_WIN_EN, 1 << i);
- orion5x_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
- if (i < ETH_MAX_REMAP_WIN)
- orion5x_write(ETH_WIN_REMAP(i), 0);
- }
-
- /*
- * Setup windows for DDR banks.
- */
- for (i = 0; i < DDR_MAX_CS; i++) {
- u32 base, size;
- size = orion5x_read(DDR_SIZE_CS(i));
- base = orion5x_read(DDR_BASE_CS(i));
- if (size & DDR_BANK_EN) {
- base = DDR_REG_TO_BASE(base);
- size = DDR_REG_TO_SIZE(size);
- orion5x_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
- orion5x_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
- (ATTR_DDR_CS(i) << 8) |
- TARGET_DDR);
- orion5x_clrbits(ETH_WIN_EN, 1 << i);
- orion5x_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
- }
- }
+ setup_cpu_win(win_alloc_count++, base, size,
+ TARGET_PCIE, ATTR_PCIE_WA, -1);