omap2plus: clockdomain: Trivial fix for build break because of clktrctrl_mask

[pandora-kernel.git] / arch / arm / mach-omap2 / sram34xx.S

diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index de99ba2..7f893a2 100644 (file)
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -32,7 +32,7 @@
 #include <mach/io.h>
 
 #include "sdrc.h"
-#include "cm.h"
+#include "cm2xxx_3xxx.h"
 
        .text
 
@@ -104,6 +104,12 @@
  * touching the SDRAM.  Until that time, users who know that their use case
  * can satisfy the above requirement can enable the CONFIG_OMAP3_SDRC_AC_TIMING
  * option.
+ *
+ * Richard Woodruff notes that any changes to this code must be carefully
+ * audited and tested to ensure that they don't cause a TLB miss while
+ * the SDRAM is inaccessible.  Such a situation will crash the system
+ * since it will cause the ARM MMU to attempt to walk the page tables.
+ * These crashes may be intermittent.
  */
 ENTRY(omap3_sram_configure_core_dpll)
        stmfd   sp!, {r1-r12, lr}       @ store regs to stack
@@ -129,8 +135,11 @@ ENTRY(omap3_sram_configure_core_dpll)
        ldr     r4, [sp, #80]
        str     r4, omap_sdrc_mr_1_val
 skip_cs1_params:
+       mrc     p15, 0, r8, c1, c0, 0   @ read ctrl register
+       bic     r10, r8, #0x800         @ clear Z-bit, disable branch prediction
+       mcr     p15, 0, r10, c1, c0, 0  @ write ctrl register
        dsb                             @ flush buffered writes to interconnect
-
+       isb                             @ prevent speculative exec past here
        cmp     r3, #1                  @ if increasing SDRC clk rate,
        bleq    configure_sdrc          @ program the SDRC regs early (for RFR)
        cmp     r1, #SDRC_UNLOCK_DLL    @ set the intended DLL state
@@ -148,6 +157,7 @@ skip_cs1_params:
        beq     return_to_sdram         @ return to SDRAM code, otherwise,
        bl      configure_sdrc          @ reprogram SDRC regs now
 return_to_sdram:
+       mcr     p15, 0, r8, c1, c0, 0   @ restore ctrl register
        isb                             @ prevent speculative exec past here
        mov     r0, #0                  @ return value
        ldmfd   sp!, {r1-r12, pc}       @ restore regs and return