* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#include <linux/module.h>
+
+#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/io.h>
#include "clock.h"
#include "clock2xxx.h"
#include "cm2xxx_3xxx.h"
-#include "cm44xx.h"
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
+#include "prminst44xx.h"
#include "prm-regbits-24xx.h"
#include "prm-regbits-44xx.h"
#include "control.h"
{
/* XXX This presumably needs modification for 34XX */
if (cpu_is_omap24xx() || cpu_is_omap34xx())
- return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
+ return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
if (cpu_is_omap44xx())
- return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
+ return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
return 0;
}
} else if (cpu_is_omap34xx()) {
prcm_offs = OMAP3430_GR_MOD;
omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
- } else if (cpu_is_omap44xx())
- prcm_offs = OMAP4430_PRM_DEVICE_INST;
- else
+ } else if (cpu_is_omap44xx()) {
+ omap4_prm_global_warm_sw_reset(); /* never returns */
+ } else {
WARN_ON(1);
+ }
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
- prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
- OMAP2_RM_RSTCTRL);
- if (cpu_is_omap44xx())
- prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
- prcm_offs, OMAP4_RM_RSTCTRL);
-}
-
-/* Read a PRM register, AND it, and shift the result down to bit 0 */
-u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
-{
- u32 v;
-
- v = __raw_readl(reg);
- v &= mask;
- v >>= __ffs(mask);
-
- return v;
-}
-
-/* Read-modify-write a register in a PRM module. Caller must lock */
-u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
-{
- u32 v;
-
- v = __raw_readl(reg);
- v &= ~mask;
- v |= bits;
- __raw_writel(v, reg);
-
- return v;
+ /*
+ * As per Errata i520, in some cases, user will not be able to
+ * access DDR memory after warm-reset.
+ * This situation occurs while the warm-reset happens during a read
+ * access to DDR memory. In that particular condition, DDR memory
+ * does not respond to a corrupted read command due to the warm
+ * reset occurrence but SDRC is waiting for read completion.
+ * SDRC is not sensitive to the warm reset, but the interconnect is
+ * reset on the fly, thus causing a misalignment between SDRC logic,
+ * interconnect logic and DDR memory state.
+ * WORKAROUND:
+ * Steps to perform before a Warm reset is trigged:
+ * 1. enable self-refresh on idle request
+ * 2. put SDRC in idle
+ * 3. wait until SDRC goes to idle
+ * 4. generate SW reset (Global SW reset)
+ *
+ * Steps to be performed after warm reset occurs (in bootloader):
+ * if HW warm reset is the source, apply below steps before any
+ * accesses to SDRAM:
+ * 1. Reset SMS and SDRC and wait till reset is complete
+ * 2. Re-initialize SMS, SDRC and memory
+ *
+ * NOTE: Above work around is required only if arch reset is implemented
+ * using Global SW reset(GLOBAL_SW_RST). DPLL3 reset does not need
+ * the WA since it resets SDRC as well as part of cold reset.
+ */
+
+ /* XXX should be moved to some OMAP2/3 specific code */
+ omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
+ OMAP2_RM_RSTCTRL);
+ omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */
}
/**