Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

[pandora-kernel.git] / arch / arm / mach-omap2 / gpmc-onenand.c

diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 3a7d25f..d776ded 100644 (file)
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 }
 
 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
-                               int sync_read, int sync_write, int hf)
+                               int sync_read, int sync_write, int hf, int vhf)
 {
        u32 reg;
 
@@ -114,12 +114,57 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
                reg |= ONENAND_SYS_CFG1_HF;
        else
                reg &= ~ONENAND_SYS_CFG1_HF;
+       if (vhf)
+               reg |= ONENAND_SYS_CFG1_VHF;
+       else
+               reg &= ~ONENAND_SYS_CFG1_VHF;
        writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 }
 
+static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
+                                 void __iomem *onenand_base, bool *clk_dep)
+{
+       u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
+       int freq = 0;
+
+       if (cfg->get_freq) {
+               struct onenand_freq_info fi;
+
+               fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
+               fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
+               fi.ver_id = ver;
+               freq = cfg->get_freq(&fi, clk_dep);
+               if (freq)
+                       return freq;
+       }
+
+       switch ((ver >> 4) & 0xf) {
+       case 0:
+               freq = 40;
+               break;
+       case 1:
+               freq = 54;
+               break;
+       case 2:
+               freq = 66;
+               break;
+       case 3:
+               freq = 83;
+               break;
+       case 4:
+               freq = 104;
+               break;
+       default:
+               freq = 54;
+               break;
+       }
+
+       return freq;
+}
+
 static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                                        void __iomem *onenand_base,
-                                       int freq)
+                                       int *freq_ptr)
 {
        struct gpmc_timings t;
        const int t_cer  = 15;
@@ -130,10 +175,11 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
        const int t_wph  = 30;
        int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
        int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
-       int first_time = 0, hf = 0, sync_read = 0, sync_write = 0;
+       int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
        int err, ticks_cez;
-       int cs = cfg->cs;
+       int cs = cfg->cs, freq = *freq_ptr;
        u32 reg;
+       bool clk_dep = false;
 
        if (cfg->flags & ONENAND_SYNC_READ) {
                sync_read = 1;
@@ -148,27 +194,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                err = omap2_onenand_set_async_mode(cs, onenand_base);
                if (err)
                        return err;
-               reg = readw(onenand_base + ONENAND_REG_VERSION_ID);
-               switch ((reg >> 4) & 0xf) {
-               case 0:
-                       freq = 40;
-                       break;
-               case 1:
-                       freq = 54;
-                       break;
-               case 2:
-                       freq = 66;
-                       break;
-               case 3:
-                       freq = 83;
-                       break;
-               case 4:
-                       freq = 104;
-                       break;
-               default:
-                       freq = 54;
-                       break;
-               }
+               freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
                first_time = 1;
        }
 
@@ -180,7 +206,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                t_avdh  = 2;
                t_ach   = 3;
                t_aavdh = 6;
-               t_rdyo  = 9;
+               t_rdyo  = 6;
                break;
        case 83:
                min_gpmc_clk_period = 12000; /* 83 MHz */
@@ -217,16 +243,36 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
        gpmc_clk_ns = gpmc_ticks_to_ns(div);
        if (gpmc_clk_ns < 15) /* >66Mhz */
                hf = 1;
-       if (hf)
+       if (gpmc_clk_ns < 12) /* >83Mhz */
+               vhf = 1;
+       if (vhf)
+               latency = 8;
+       else if (hf)
                latency = 6;
        else if (gpmc_clk_ns >= 25) /* 40 MHz*/
                latency = 3;
        else
                latency = 4;
 
+       if (clk_dep) {
+               if (gpmc_clk_ns < 12) { /* >83Mhz */
+                       t_ces   = 3;
+                       t_avds  = 4;
+               } else if (gpmc_clk_ns < 15) { /* >66Mhz */
+                       t_ces   = 5;
+                       t_avds  = 4;
+               } else if (gpmc_clk_ns < 25) { /* >40Mhz */
+                       t_ces   = 6;
+                       t_avds  = 5;
+               } else {
+                       t_ces   = 7;
+                       t_avds  = 7;
+               }
+       }
+
        if (first_time)
                set_onenand_cfg(onenand_base, latency,
-                                       sync_read, sync_write, hf);
+                                       sync_read, sync_write, hf, vhf);
 
        if (div == 1) {
                reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -264,6 +310,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
        /* Read */
        t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
        t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
+       /* Force at least 1 clk between AVD High to OE Low */
+       if (t.oe_on <= t.adv_rd_off)
+               t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
        t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
        t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
        t.cs_rd_off = t.oe_off;
@@ -317,18 +366,20 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
        if (err)
                return err;
 
-       set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
+       set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
+
+       *freq_ptr = freq;
 
        return 0;
 }
 
-static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
+static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 {
        struct device *dev = &gpmc_onenand_device.dev;
 
        /* Set sync timings in GPMC */
        if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
-                       freq) < 0) {
+                       freq_ptr) < 0) {
                dev_err(dev, "Unable to set synchronous mode\n");
                return -EINVAL;
        }