Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6
[pandora-kernel.git] / arch / arm / mach-omap2 / cpuidle34xx.c
index 12f0cbf..0d50b45 100644 (file)
 #include <plat/irqs.h>
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
-#include <plat/control.h>
 #include <plat/serial.h>
 
 #include "pm.h"
+#include "control.h"
 
 #ifdef CONFIG_CPU_IDLE
 
@@ -45,6 +45,8 @@
 #define OMAP3_STATE_C6 5 /* C6 - MPU OFF + Core RET */
 #define OMAP3_STATE_C7 6 /* C7 - MPU OFF + Core OFF */
 
+#define OMAP3_STATE_MAX OMAP3_STATE_C7
+
 struct omap3_processor_cx {
        u8 valid;
        u8 type;
@@ -58,7 +60,32 @@ struct omap3_processor_cx {
 
 struct omap3_processor_cx omap3_power_states[OMAP3_MAX_STATES];
 struct omap3_processor_cx current_cx_state;
-struct powerdomain *mpu_pd, *core_pd;
+struct powerdomain *mpu_pd, *core_pd, *per_pd;
+struct powerdomain *cam_pd;
+
+/*
+ * The latencies/thresholds for various C states have
+ * to be configured from the respective board files.
+ * These are some default values (which might not provide
+ * the best power savings) used on boards which do not
+ * pass these details from the board file.
+ */
+static struct cpuidle_params cpuidle_params_table[] = {
+       /* C1 */
+       {1, 2, 2, 5},
+       /* C2 */
+       {1, 10, 10, 30},
+       /* C3 */
+       {1, 50, 50, 300},
+       /* C4 */
+       {1, 1500, 1800, 4000},
+       /* C5 */
+       {1, 2500, 7500, 12000},
+       /* C6 */
+       {1, 3000, 8500, 15000},
+       /* C7 */
+       {1, 10000, 30000, 300000},
+};
 
 static int omap3_idle_bm_check(void)
 {
@@ -104,13 +131,6 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
        local_irq_disable();
        local_fiq_disable();
 
-       if (!enable_off_mode) {
-               if (mpu_state < PWRDM_POWER_RET)
-                       mpu_state = PWRDM_POWER_RET;
-               if (core_state < PWRDM_POWER_RET)
-                       core_state = PWRDM_POWER_RET;
-       }
-
        pwrdm_set_next_pwrst(mpu_pd, mpu_state);
        pwrdm_set_next_pwrst(core_pd, core_state);
 
@@ -140,6 +160,67 @@ return_sleep_time:
        return ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * USEC_PER_SEC;
 }
 
+/**
+ * next_valid_state - Find next valid c-state
+ * @dev: cpuidle device
+ * @state: Currently selected c-state
+ *
+ * If the current state is valid, it is returned back to the caller.
+ * Else, this function searches for a lower c-state which is still
+ * valid (as defined in omap3_power_states[]).
+ */
+static struct cpuidle_state *next_valid_state(struct cpuidle_device *dev,
+                                               struct cpuidle_state *curr)
+{
+       struct cpuidle_state *next = NULL;
+       struct omap3_processor_cx *cx;
+
+       cx = (struct omap3_processor_cx *)cpuidle_get_statedata(curr);
+
+       /* Check if current state is valid */
+       if (cx->valid) {
+               return curr;
+       } else {
+               u8 idx = OMAP3_STATE_MAX;
+
+               /*
+                * Reach the current state starting at highest C-state
+                */
+               for (; idx >= OMAP3_STATE_C1; idx--) {
+                       if (&dev->states[idx] == curr) {
+                               next = &dev->states[idx];
+                               break;
+                       }
+               }
+
+               /*
+                * Should never hit this condition.
+                */
+               WARN_ON(next == NULL);
+
+               /*
+                * Drop to next valid state.
+                * Start search from the next (lower) state.
+                */
+               idx--;
+               for (; idx >= OMAP3_STATE_C1; idx--) {
+                       struct omap3_processor_cx *cx;
+
+                       cx = cpuidle_get_statedata(&dev->states[idx]);
+                       if (cx->valid) {
+                               next = &dev->states[idx];
+                               break;
+                       }
+               }
+               /*
+                * C1 and C2 are always valid.
+                * So, no need to check for 'next==NULL' outside this loop.
+                */
+       }
+
+       return next;
+}
+
 /**
  * omap3_enter_idle_bm - Checks for any bus activity
  * @dev: cpuidle device
@@ -152,19 +233,109 @@ return_sleep_time:
 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
                               struct cpuidle_state *state)
 {
-       struct cpuidle_state *new_state = state;
+       struct cpuidle_state *new_state = next_valid_state(dev, state);
+       u32 core_next_state, per_next_state = 0, per_saved_state = 0;
+       u32 cam_state;
+       struct omap3_processor_cx *cx;
+       int ret;
 
        if ((state->flags & CPUIDLE_FLAG_CHECK_BM) && omap3_idle_bm_check()) {
                BUG_ON(!dev->safe_state);
                new_state = dev->safe_state;
+               goto select_state;
+       }
+
+       cx = cpuidle_get_statedata(state);
+       core_next_state = cx->core_state;
+
+       /*
+        * FIXME: we currently manage device-specific idle states
+        *        for PER and CORE in combination with CPU-specific
+        *        idle states.  This is wrong, and device-specific
+        *        idle managment needs to be separated out into 
+        *        its own code.
+        */
+
+       /*
+        * Prevent idle completely if CAM is active.
+        * CAM does not have wakeup capability in OMAP3.
+        */
+       cam_state = pwrdm_read_pwrst(cam_pd);
+       if (cam_state == PWRDM_POWER_ON) {
+               new_state = dev->safe_state;
+               goto select_state;
        }
 
+       /*
+        * Prevent PER off if CORE is not in retention or off as this
+        * would disable PER wakeups completely.
+        */
+       per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
+       if ((per_next_state == PWRDM_POWER_OFF) &&
+           (core_next_state > PWRDM_POWER_RET))
+               per_next_state = PWRDM_POWER_RET;
+
+       /* Are we changing PER target state? */
+       if (per_next_state != per_saved_state)
+               pwrdm_set_next_pwrst(per_pd, per_next_state);
+
+select_state:
        dev->last_state = new_state;
-       return omap3_enter_idle(dev, new_state);
+       ret = omap3_enter_idle(dev, new_state);
+
+       /* Restore original PER state if it was modified */
+       if (per_next_state != per_saved_state)
+               pwrdm_set_next_pwrst(per_pd, per_saved_state);
+
+       return ret;
 }
 
 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 
+/**
+ * omap3_cpuidle_update_states - Update the cpuidle states.
+ *
+ * Currently, this function toggles the validity of idle states based upon
+ * the flag 'enable_off_mode'. When the flag is set all states are valid.
+ * Else, states leading to OFF state set to be invalid.
+ */
+void omap3_cpuidle_update_states(void)
+{
+       int i;
+
+       for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
+               struct omap3_processor_cx *cx = &omap3_power_states[i];
+
+               if (enable_off_mode) {
+                       cx->valid = 1;
+               } else {
+                       if ((cx->mpu_state == PWRDM_POWER_OFF) ||
+                               (cx->core_state == PWRDM_POWER_OFF))
+                               cx->valid = 0;
+               }
+       }
+}
+
+void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
+{
+       int i;
+
+       if (!cpuidle_board_params)
+               return;
+
+       for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
+               cpuidle_params_table[i].valid =
+                       cpuidle_board_params[i].valid;
+               cpuidle_params_table[i].sleep_latency =
+                       cpuidle_board_params[i].sleep_latency;
+               cpuidle_params_table[i].wake_latency =
+                       cpuidle_board_params[i].wake_latency;
+               cpuidle_params_table[i].threshold =
+                       cpuidle_board_params[i].threshold;
+       }
+       return;
+}
+
 /* omap3_init_power_states - Initialises the OMAP3 specific C states.
  *
  * Below is the desciption of each C state.
@@ -179,75 +350,104 @@ DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 void omap_init_power_states(void)
 {
        /* C1 . MPU WFI + Core active */
-       omap3_power_states[OMAP3_STATE_C1].valid = 1;
+       omap3_power_states[OMAP3_STATE_C1].valid =
+                       cpuidle_params_table[OMAP3_STATE_C1].valid;
        omap3_power_states[OMAP3_STATE_C1].type = OMAP3_STATE_C1;
-       omap3_power_states[OMAP3_STATE_C1].sleep_latency = 2;
-       omap3_power_states[OMAP3_STATE_C1].wakeup_latency = 2;
-       omap3_power_states[OMAP3_STATE_C1].threshold = 5;
+       omap3_power_states[OMAP3_STATE_C1].sleep_latency =
+                       cpuidle_params_table[OMAP3_STATE_C1].sleep_latency;
+       omap3_power_states[OMAP3_STATE_C1].wakeup_latency =
+                       cpuidle_params_table[OMAP3_STATE_C1].wake_latency;
+       omap3_power_states[OMAP3_STATE_C1].threshold =
+                       cpuidle_params_table[OMAP3_STATE_C1].threshold;
        omap3_power_states[OMAP3_STATE_C1].mpu_state = PWRDM_POWER_ON;
        omap3_power_states[OMAP3_STATE_C1].core_state = PWRDM_POWER_ON;
        omap3_power_states[OMAP3_STATE_C1].flags = CPUIDLE_FLAG_TIME_VALID;
 
        /* C2 . MPU WFI + Core inactive */
-       omap3_power_states[OMAP3_STATE_C2].valid = 1;
+       omap3_power_states[OMAP3_STATE_C2].valid =
+                       cpuidle_params_table[OMAP3_STATE_C2].valid;
        omap3_power_states[OMAP3_STATE_C2].type = OMAP3_STATE_C2;
-       omap3_power_states[OMAP3_STATE_C2].sleep_latency = 10;
-       omap3_power_states[OMAP3_STATE_C2].wakeup_latency = 10;
-       omap3_power_states[OMAP3_STATE_C2].threshold = 30;
+       omap3_power_states[OMAP3_STATE_C2].sleep_latency =
+                       cpuidle_params_table[OMAP3_STATE_C2].sleep_latency;
+       omap3_power_states[OMAP3_STATE_C2].wakeup_latency =
+                       cpuidle_params_table[OMAP3_STATE_C2].wake_latency;
+       omap3_power_states[OMAP3_STATE_C2].threshold =
+                       cpuidle_params_table[OMAP3_STATE_C2].threshold;
        omap3_power_states[OMAP3_STATE_C2].mpu_state = PWRDM_POWER_ON;
        omap3_power_states[OMAP3_STATE_C2].core_state = PWRDM_POWER_ON;
-       omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID;
+       omap3_power_states[OMAP3_STATE_C2].flags = CPUIDLE_FLAG_TIME_VALID |
+                               CPUIDLE_FLAG_CHECK_BM;
 
        /* C3 . MPU CSWR + Core inactive */
-       omap3_power_states[OMAP3_STATE_C3].valid = 1;
+       omap3_power_states[OMAP3_STATE_C3].valid =
+                       cpuidle_params_table[OMAP3_STATE_C3].valid;
        omap3_power_states[OMAP3_STATE_C3].type = OMAP3_STATE_C3;
-       omap3_power_states[OMAP3_STATE_C3].sleep_latency = 50;
-       omap3_power_states[OMAP3_STATE_C3].wakeup_latency = 50;
-       omap3_power_states[OMAP3_STATE_C3].threshold = 300;
+       omap3_power_states[OMAP3_STATE_C3].sleep_latency =
+                       cpuidle_params_table[OMAP3_STATE_C3].sleep_latency;
+       omap3_power_states[OMAP3_STATE_C3].wakeup_latency =
+                       cpuidle_params_table[OMAP3_STATE_C3].wake_latency;
+       omap3_power_states[OMAP3_STATE_C3].threshold =
+                       cpuidle_params_table[OMAP3_STATE_C3].threshold;
        omap3_power_states[OMAP3_STATE_C3].mpu_state = PWRDM_POWER_RET;
        omap3_power_states[OMAP3_STATE_C3].core_state = PWRDM_POWER_ON;
        omap3_power_states[OMAP3_STATE_C3].flags = CPUIDLE_FLAG_TIME_VALID |
                                CPUIDLE_FLAG_CHECK_BM;
 
        /* C4 . MPU OFF + Core inactive */
-       omap3_power_states[OMAP3_STATE_C4].valid = 1;
+       omap3_power_states[OMAP3_STATE_C4].valid =
+                       cpuidle_params_table[OMAP3_STATE_C4].valid;
        omap3_power_states[OMAP3_STATE_C4].type = OMAP3_STATE_C4;
-       omap3_power_states[OMAP3_STATE_C4].sleep_latency = 1500;
-       omap3_power_states[OMAP3_STATE_C4].wakeup_latency = 1800;
-       omap3_power_states[OMAP3_STATE_C4].threshold = 4000;
+       omap3_power_states[OMAP3_STATE_C4].sleep_latency =
+                       cpuidle_params_table[OMAP3_STATE_C4].sleep_latency;
+       omap3_power_states[OMAP3_STATE_C4].wakeup_latency =
+                       cpuidle_params_table[OMAP3_STATE_C4].wake_latency;
+       omap3_power_states[OMAP3_STATE_C4].threshold =
+                       cpuidle_params_table[OMAP3_STATE_C4].threshold;
        omap3_power_states[OMAP3_STATE_C4].mpu_state = PWRDM_POWER_OFF;
        omap3_power_states[OMAP3_STATE_C4].core_state = PWRDM_POWER_ON;
        omap3_power_states[OMAP3_STATE_C4].flags = CPUIDLE_FLAG_TIME_VALID |
                                CPUIDLE_FLAG_CHECK_BM;
 
        /* C5 . MPU CSWR + Core CSWR*/
-       omap3_power_states[OMAP3_STATE_C5].valid = 1;
+       omap3_power_states[OMAP3_STATE_C5].valid =
+                       cpuidle_params_table[OMAP3_STATE_C5].valid;
        omap3_power_states[OMAP3_STATE_C5].type = OMAP3_STATE_C5;
-       omap3_power_states[OMAP3_STATE_C5].sleep_latency = 2500;
-       omap3_power_states[OMAP3_STATE_C5].wakeup_latency = 7500;
-       omap3_power_states[OMAP3_STATE_C5].threshold = 12000;
+       omap3_power_states[OMAP3_STATE_C5].sleep_latency =
+                       cpuidle_params_table[OMAP3_STATE_C5].sleep_latency;
+       omap3_power_states[OMAP3_STATE_C5].wakeup_latency =
+                       cpuidle_params_table[OMAP3_STATE_C5].wake_latency;
+       omap3_power_states[OMAP3_STATE_C5].threshold =
+                       cpuidle_params_table[OMAP3_STATE_C5].threshold;
        omap3_power_states[OMAP3_STATE_C5].mpu_state = PWRDM_POWER_RET;
        omap3_power_states[OMAP3_STATE_C5].core_state = PWRDM_POWER_RET;
        omap3_power_states[OMAP3_STATE_C5].flags = CPUIDLE_FLAG_TIME_VALID |
                                CPUIDLE_FLAG_CHECK_BM;
 
        /* C6 . MPU OFF + Core CSWR */
-       omap3_power_states[OMAP3_STATE_C6].valid = 1;
+       omap3_power_states[OMAP3_STATE_C6].valid =
+                       cpuidle_params_table[OMAP3_STATE_C6].valid;
        omap3_power_states[OMAP3_STATE_C6].type = OMAP3_STATE_C6;
-       omap3_power_states[OMAP3_STATE_C6].sleep_latency = 3000;
-       omap3_power_states[OMAP3_STATE_C6].wakeup_latency = 8500;
-       omap3_power_states[OMAP3_STATE_C6].threshold = 15000;
+       omap3_power_states[OMAP3_STATE_C6].sleep_latency =
+                       cpuidle_params_table[OMAP3_STATE_C6].sleep_latency;
+       omap3_power_states[OMAP3_STATE_C6].wakeup_latency =
+                       cpuidle_params_table[OMAP3_STATE_C6].wake_latency;
+       omap3_power_states[OMAP3_STATE_C6].threshold =
+                       cpuidle_params_table[OMAP3_STATE_C6].threshold;
        omap3_power_states[OMAP3_STATE_C6].mpu_state = PWRDM_POWER_OFF;
        omap3_power_states[OMAP3_STATE_C6].core_state = PWRDM_POWER_RET;
        omap3_power_states[OMAP3_STATE_C6].flags = CPUIDLE_FLAG_TIME_VALID |
                                CPUIDLE_FLAG_CHECK_BM;
 
        /* C7 . MPU OFF + Core OFF */
-       omap3_power_states[OMAP3_STATE_C7].valid = 1;
+       omap3_power_states[OMAP3_STATE_C7].valid =
+                       cpuidle_params_table[OMAP3_STATE_C7].valid;
        omap3_power_states[OMAP3_STATE_C7].type = OMAP3_STATE_C7;
-       omap3_power_states[OMAP3_STATE_C7].sleep_latency = 10000;
-       omap3_power_states[OMAP3_STATE_C7].wakeup_latency = 30000;
-       omap3_power_states[OMAP3_STATE_C7].threshold = 300000;
+       omap3_power_states[OMAP3_STATE_C7].sleep_latency =
+                       cpuidle_params_table[OMAP3_STATE_C7].sleep_latency;
+       omap3_power_states[OMAP3_STATE_C7].wakeup_latency =
+                       cpuidle_params_table[OMAP3_STATE_C7].wake_latency;
+       omap3_power_states[OMAP3_STATE_C7].threshold =
+                       cpuidle_params_table[OMAP3_STATE_C7].threshold;
        omap3_power_states[OMAP3_STATE_C7].mpu_state = PWRDM_POWER_OFF;
        omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
        omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
@@ -274,6 +474,8 @@ int __init omap3_idle_init(void)
 
        mpu_pd = pwrdm_lookup("mpu_pwrdm");
        core_pd = pwrdm_lookup("core_pwrdm");
+       per_pd = pwrdm_lookup("per_pwrdm");
+       cam_pd = pwrdm_lookup("cam_pwrdm");
 
        omap_init_power_states();
        cpuidle_register_driver(&omap3_idle_driver);
@@ -302,6 +504,8 @@ int __init omap3_idle_init(void)
                return -EINVAL;
        dev->state_count = count;
 
+       omap3_cpuidle_update_states();
+
        if (cpuidle_register_device(dev)) {
                printk(KERN_ERR "%s: CPUidle register device failed\n",
                       __func__);