ARM: OMAP: Remove cm_rmw_reg_bits()

[pandora-kernel.git] / arch / arm / mach-omap2 / cm.h

diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 8489f30..bacadcb 100644 (file)
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -16,29 +16,25 @@
 
 #include "prcm-common.h"
 
-#ifndef __ASSEMBLER__
-#define OMAP_CM_REGADDR(module, reg)                                   \
-       (void __iomem *)IO_ADDRESS(OMAP2_CM_BASE + (module) + (reg))
-#else
 #define OMAP2420_CM_REGADDR(module, reg)                               \
                        IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
 #define OMAP2430_CM_REGADDR(module, reg)                               \
                        IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
 #define OMAP34XX_CM_REGADDR(module, reg)                               \
                        IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
-#endif
 
 /*
  * Architecture-specific global CM registers
- * Use cm_{read,write}_reg() with these registers.
+ * Use __raw_{read,write}l() with these registers.
  * These registers appear once per CM module.
  */
 
-#define OMAP3430_CM_REVISION           OMAP_CM_REGADDR(OCP_MOD, 0x0000)
-#define OMAP3430_CM_SYSCONFIG          OMAP_CM_REGADDR(OCP_MOD, 0x0010)
-#define OMAP3430_CM_POLCTRL            OMAP_CM_REGADDR(OCP_MOD, 0x009c)
+#define OMAP3430_CM_REVISION           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG          OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL            OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
 
-#define OMAP3430_CM_CLKOUT_CTRL                OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
+#define OMAP3430_CM_CLKOUT_CTRL                                                \
+                               OMAP34XX_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
 
 /*
  * Module specific CM registers from CM_BASE + domain offset
@@ -67,7 +63,6 @@
 #define CM_CLKSEL2                                     0x0044
 #define CM_CLKSTCTRL                                   0x0048
 
-
 /* Architecture-specific registers */
 
 #define OMAP24XX_CM_FCLKEN2                            0x0004
@@ -81,6 +76,7 @@
 #define OMAP3430ES2_CM_FCLKEN3                         0x0008
 #define OMAP3430_CM_IDLEST_PLL                         CM_IDLEST2
 #define OMAP3430_CM_AUTOIDLE_PLL                       CM_AUTOIDLE2
+#define OMAP3430ES2_CM_AUTOIDLE2_PLL                   CM_AUTOIDLE2
 #define OMAP3430_CM_CLKSEL1                            CM_CLKSEL
 #define OMAP3430_CM_CLKSEL1_PLL                                CM_CLKSEL
 #define OMAP3430_CM_CLKSEL2_PLL                                CM_CLKSEL2
@@ -96,15 +92,21 @@
 /* Clock management domain register get/set */
 
 #ifndef __ASSEMBLER__
-static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx)
+
+extern u32 cm_read_mod_reg(s16 module, u16 idx);
+extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
+extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
+
+static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-       __raw_writel(val, OMAP_CM_REGADDR(module, idx));
+       return cm_rmw_mod_reg_bits(bits, bits, module, idx);
 }
 
-static inline u32 cm_read_mod_reg(s16 module, s16 idx)
+static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
 {
-       return __raw_readl(OMAP_CM_REGADDR(module, idx));
+       return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
 }
+
 #endif
 
 /* CM register bits shared between 24XX and 3430 */