Merge branch 'stable-3.2' into pandora-3.2

[pandora-kernel.git] / arch / arm / mach-omap2 / clock44xx_data.c

diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 946bf04..37931a5 100644 (file)
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -270,8 +270,8 @@ static struct clk dpll_abe_ck = {
        .dpll_data      = &dpll_abe_dd,
        .init           = &omap2_init_dpll_parent,
        .ops            = &clkops_omap3_noncore_dpll_ops,
-       .recalc         = &omap3_dpll_recalc,
-       .round_rate     = &omap2_dpll_round_rate,
+       .recalc         = &omap4_dpll_regm4xen_recalc,
+       .round_rate     = &omap4_dpll_regm4xen_round_rate,
        .set_rate       = &omap3_noncore_dpll_set_rate,
 };
 
@@ -1195,11 +1195,25 @@ static struct clk l4_wkup_clk_mux_ck = {
        .recalc         = &omap2_clksel_recalc,
 };
 
+static const struct clksel_rate div2_2to1_rates[] = {
+       { .div = 1, .val = 1, .flags = RATE_IN_4430 },
+       { .div = 2, .val = 0, .flags = RATE_IN_4430 },
+       { .div = 0 },
+};
+
+static const struct clksel ocp_abe_iclk_div[] = {
+       { .parent = &aess_fclk, .rates = div2_2to1_rates },
+       { .parent = NULL },
+};
+
 static struct clk ocp_abe_iclk = {
        .name           = "ocp_abe_iclk",
        .parent         = &aess_fclk,
+       .clksel         = ocp_abe_iclk_div,
+       .clksel_reg     = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+       .clksel_mask    = OMAP4430_CLKSEL_AESS_FCLK_MASK,
        .ops            = &clkops_null,
-       .recalc         = &followparent_recalc,
+       .recalc         = &omap2_clksel_recalc,
 };
 
 static struct clk per_abe_24m_fclk = {
@@ -1398,9 +1412,9 @@ static struct clk dss_dss_clk = {
 };
 
 static const struct clksel_rate div3_8to32_rates[] = {
-       { .div = 8, .val = 0, .flags = RATE_IN_44XX },
-       { .div = 16, .val = 1, .flags = RATE_IN_44XX },
-       { .div = 32, .val = 2, .flags = RATE_IN_44XX },
+       { .div = 8, .val = 0, .flags = RATE_IN_4460 },
+       { .div = 16, .val = 1, .flags = RATE_IN_4460 },
+       { .div = 32, .val = 2, .flags = RATE_IN_4460 },
        { .div = 0 },
 };
 
@@ -3327,17 +3341,6 @@ static struct omap_clk omap44xx_clks[] = {
        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
        CLK(NULL,       "gpmc_ck",                      &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt1_ick",                     &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt2_ick",                     &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt3_ick",                     &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt4_ick",                     &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt5_ick",                     &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt6_ick",                     &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt7_ick",                     &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt8_ick",                     &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt9_ick",                     &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt10_ick",                    &dummy_ck,      CK_443X),
-       CLK(NULL,       "gpt11_ick",                    &dummy_ck,      CK_443X),
        CLK("omap_i2c.1",       "ick",                          &dummy_ck,      CK_443X),
        CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
        CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
@@ -3363,17 +3366,6 @@ static struct omap_clk omap44xx_clks[] = {
        CLK("usbhs-omap.0",     "usbhost_ick",          &dummy_ck,              CK_443X),
        CLK("usbhs-omap.0",     "usbtll_fck",           &dummy_ck,      CK_443X),
        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
-       CLK("omap_timer.1",     "fck",                  &timer1_fck,    CK_443X),
-       CLK("omap_timer.2",     "fck",                  &timer2_fck,    CK_443X),
-       CLK("omap_timer.3",     "fck",                  &timer3_fck,    CK_443X),
-       CLK("omap_timer.4",     "fck",                  &timer4_fck,    CK_443X),
-       CLK("omap_timer.5",     "fck",                  &timer5_fck,    CK_443X),
-       CLK("omap_timer.6",     "fck",                  &timer6_fck,    CK_443X),
-       CLK("omap_timer.7",     "fck",                  &timer7_fck,    CK_443X),
-       CLK("omap_timer.8",     "fck",                  &timer8_fck,    CK_443X),
-       CLK("omap_timer.9",     "fck",                  &timer9_fck,    CK_443X),
-       CLK("omap_timer.10",    "fck",                  &timer10_fck,   CK_443X),
-       CLK("omap_timer.11",    "fck",                  &timer11_fck,   CK_443X),
        CLK("omap_timer.1",     "32k_ck",       &sys_32k_ck,    CK_443X),
        CLK("omap_timer.2",     "32k_ck",       &sys_32k_ck,    CK_443X),
        CLK("omap_timer.3",     "32k_ck",       &sys_32k_ck,    CK_443X),
@@ -3403,12 +3395,12 @@ int __init omap4xxx_clk_init(void)
        struct omap_clk *c;
        u32 cpu_clkflg;
 
-       if (cpu_is_omap44xx()) {
+       if (cpu_is_omap443x()) {
                cpu_mask = RATE_IN_4430;
                cpu_clkflg = CK_443X;
        } else if (cpu_is_omap446x()) {
-               cpu_mask = RATE_IN_4460;
-               cpu_clkflg = CK_446X;
+               cpu_mask = RATE_IN_4460 | RATE_IN_4430;
+               cpu_clkflg = CK_446X | CK_443X;
        } else {
                return 0;
        }