* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
-#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
-#include <asm/arch/prcm.h>
+#include "prcm-regs.h"
+#include "memory.h"
#include "clock.h"
+#undef DEBUG
+
//#define DOWN_VARIABLE_DPLL 1 /* Experimental */
static struct prcm_config *curr_prcm_set;
-static struct memory_timings mem_timings;
static u32 curr_perf_level = PRCM_FULL_SPEED;
+static struct clk *vclk;
+static struct clk *sclk;
/*-------------------------------------------------------------------------
* Omap2 specific clock functions
static u32 omap2_get_dpll_rate(struct clk * tclk)
{
- int dpll_clk, dpll_mult, dpll_div, amult;
+ long long dpll_clk;
+ int dpll_mult, dpll_div, amult;
dpll_mult = (CM_CLKSEL1_PLL >> 12) & 0x03ff; /* 10 bits */
dpll_div = (CM_CLKSEL1_PLL >> 8) & 0x0f; /* 4 bits */
- dpll_clk = (tclk->parent->rate * dpll_mult) / (dpll_div + 1);
+ dpll_clk = (long long)tclk->parent->rate * dpll_mult;
+ do_div(dpll_clk, dpll_div + 1);
amult = CM_CLKSEL2_PLL & 0x3;
dpll_clk *= amult;
propagate_rate(clk);
}
+static void omap2_set_osc_ck(int enable)
+{
+ if (enable)
+ PRCM_CLKSRC_CTRL &= ~(0x3 << 3);
+ else
+ PRCM_CLKSRC_CTRL |= 0x3 << 3;
+}
+
/* Enable an APLL if off */
static void omap2_clk_fixed_enable(struct clk *clk)
{
else if (clk == &apll54_ck)
cval = (1 << 6);
- while (!CM_IDLEST_CKGEN & cval) { /* Wait for lock */
+ while (!(CM_IDLEST_CKGEN & cval)) { /* Wait for lock */
++i;
udelay(1);
- if (i == 100000)
+ if (i == 100000) {
+ printk(KERN_ERR "Clock %s didn't lock\n", clk->name);
+ break;
+ }
+ }
+}
+
+static void omap2_clk_wait_ready(struct clk *clk)
+{
+ unsigned long reg, other_reg, st_reg;
+ u32 bit;
+ int i;
+
+ reg = (unsigned long) clk->enable_reg;
+ if (reg == (unsigned long) &CM_FCLKEN1_CORE ||
+ reg == (unsigned long) &CM_FCLKEN2_CORE)
+ other_reg = (reg & ~0xf0) | 0x10;
+ else if (reg == (unsigned long) &CM_ICLKEN1_CORE ||
+ reg == (unsigned long) &CM_ICLKEN2_CORE)
+ other_reg = (reg & ~0xf0) | 0x00;
+ else
+ return;
+
+ /* No check for DSS or cam clocks */
+ if ((reg & 0x0f) == 0) {
+ if (clk->enable_bit <= 1 || clk->enable_bit == 31)
+ return;
+ }
+
+ /* Check if both functional and interface clocks
+ * are running. */
+ bit = 1 << clk->enable_bit;
+ if (!(__raw_readl(other_reg) & bit))
+ return;
+ st_reg = (other_reg & ~0xf0) | 0x20;
+ i = 0;
+ while (!(__raw_readl(st_reg) & bit)) {
+ i++;
+ if (i == 100000) {
+ printk(KERN_ERR "Timeout enabling clock %s\n", clk->name);
break;
+ }
}
+ if (i)
+ pr_debug("Clock %s stable after %d loops\n", clk->name, i);
}
/* Enables clock without considering parent dependencies or use count
if (clk->flags & ALWAYS_ENABLED)
return 0;
+ if (unlikely(clk == &osc_ck)) {
+ omap2_set_osc_ck(1);
+ return 0;
+ }
+
if (unlikely(clk->enable_reg == 0)) {
printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
clk->name);
regval32 = __raw_readl(clk->enable_reg);
regval32 |= (1 << clk->enable_bit);
__raw_writel(regval32, clk->enable_reg);
+ wmb();
+
+ omap2_clk_wait_ready(clk);
return 0;
}
{
u32 regval32;
+ if (unlikely(clk == &osc_ck)) {
+ omap2_set_osc_ck(0);
+ return;
+ }
+
if (clk->enable_reg == 0)
return;
regval32 = __raw_readl(clk->enable_reg);
regval32 &= ~(1 << clk->enable_bit);
__raw_writel(regval32, clk->enable_reg);
+ wmb();
}
static int omap2_clk_enable(struct clk *clk)
return 0;
}
-static void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
-{
- unsigned long dll_cnt;
- u32 fast_dll = 0;
-
- mem_timings.m_type = !((SDRC_MR_0 & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
-
- /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
- * In the case of 2422, its ok to use CS1 instead of CS0.
- */
-
-#if 0 /* FIXME: Enable after 24xx cpu detection works */
- ctype = get_cpu_type();
- if (cpu_is_omap2422())
- mem_timings.base_cs = 1;
- else
-#endif
- mem_timings.base_cs = 0;
-
- if (mem_timings.m_type != M_DDR)
- return;
-
- /* With DDR we need to determine the low frequency DLL value */
- if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
- mem_timings.dll_mode = M_UNLOCK;
- else
- mem_timings.dll_mode = M_LOCK;
-
- if (mem_timings.base_cs == 0) {
- fast_dll = SDRC_DLLA_CTRL;
- dll_cnt = SDRC_DLLA_STATUS & 0xff00;
- } else {
- fast_dll = SDRC_DLLB_CTRL;
- dll_cnt = SDRC_DLLB_STATUS & 0xff00;
- }
- if (force_lock_to_unlock_mode) {
- fast_dll &= ~0xff00;
- fast_dll |= dll_cnt; /* Current lock mode */
- }
- mem_timings.fast_dll_ctrl = fast_dll;
-
- /* No disruptions, DDR will be offline & C-ABI not followed */
- omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
- mem_timings.fast_dll_ctrl,
- mem_timings.base_cs,
- force_lock_to_unlock_mode);
- mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
-
- /* Turn status into unlock ctrl */
- mem_timings.slow_dll_ctrl |=
- ((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
-
- /* 90 degree phase for anything below 133Mhz */
- mem_timings.slow_dll_ctrl |= (1 << 1);
-}
-
static u32 omap2_reprogram_sdrc(u32 level, u32 force)
{
+ u32 slow_dll_ctrl, fast_dll_ctrl, m_type;
u32 prev = curr_perf_level, flags;
if ((curr_perf_level == level) && !force)
return prev;
+ m_type = omap2_memory_get_type();
+ slow_dll_ctrl = omap2_memory_get_slow_dll_ctrl();
+ fast_dll_ctrl = omap2_memory_get_fast_dll_ctrl();
+
if (level == PRCM_HALF_SPEED) {
local_irq_save(flags);
PRCM_VOLTSETUP = 0xffff;
omap2_sram_reprogram_sdrc(PRCM_HALF_SPEED,
- mem_timings.slow_dll_ctrl,
- mem_timings.m_type);
+ slow_dll_ctrl, m_type);
curr_perf_level = PRCM_HALF_SPEED;
local_irq_restore(flags);
}
local_irq_save(flags);
PRCM_VOLTSETUP = 0xffff;
omap2_sram_reprogram_sdrc(PRCM_FULL_SPEED,
- mem_timings.fast_dll_ctrl,
- mem_timings.m_type);
+ fast_dll_ctrl, m_type);
curr_perf_level = PRCM_FULL_SPEED;
local_irq_restore(flags);
}
case 13: /* dss2 */
mask = 0x1; break;
case 25: /* usb */
- mask = 0xf; break;
+ mask = 0x7; break;
}
}
/* Isolate control register */
div_sel = (SRC_RATE_SEL_MASK & clk->flags);
- div_off = clk->src_offset;
+ div_off = clk->rate_offset;
validrate = omap2_clksel_round_rate(clk, rate, &new_div);
- if(validrate != rate)
+ if (validrate != rate)
return(ret);
field_val = omap2_get_clksel(&div_sel, &field_mask, clk);
if (div_sel == 0)
return ret;
- if(clk->flags & CM_SYSCLKOUT_SEL1){
- switch(new_div){
- case 16: field_val = 4; break;
- case 8: field_val = 3; break;
- case 4: field_val = 2; break;
- case 2: field_val = 1; break;
- case 1: field_val = 0; break;
+ if (clk->flags & CM_SYSCLKOUT_SEL1) {
+ switch (new_div) {
+ case 16:
+ field_val = 4;
+ break;
+ case 8:
+ field_val = 3;
+ break;
+ case 4:
+ field_val = 2;
+ break;
+ case 2:
+ field_val = 1;
+ break;
+ case 1:
+ field_val = 0;
+ break;
}
- }
- else
+ } else
field_val = new_div;
reg = (void __iomem *)div_sel;
reg_val = __raw_readl(reg);
reg_val &= ~(field_mask << div_off);
reg_val |= (field_val << div_off);
-
__raw_writel(reg_val, reg);
+ wmb();
clk->rate = clk->parent->rate / field_val;
- if (clk->flags & DELAYED_APP)
+ if (clk->flags & DELAYED_APP) {
__raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
+ wmb();
+ }
ret = 0;
} else if (clk->set_rate != 0)
ret = clk->set_rate(clk, rate);
val = 0x2;
break;
case CM_WKUP_SEL1:
- src_reg_addr = (u32)&CM_CLKSEL2_CORE;
+ src_reg_addr = (u32)&CM_CLKSEL_WKUP;
mask = 0x3;
if (src_clk == &func_32k_ck)
val = 0x0;
val = 0;
if (src_clk == &sys_ck)
val = 1;
- if (src_clk == &func_54m_ck)
- val = 2;
if (src_clk == &func_96m_ck)
+ val = 2;
+ if (src_clk == &func_54m_ck)
val = 3;
break;
}
reg_val = __raw_readl(reg) & ~(field_mask << src_off);
reg_val |= (field_val << src_off);
__raw_writel(reg_val, reg);
+ wmb();
- if (clk->flags & DELAYED_APP)
+ if (clk->flags & DELAYED_APP) {
__raw_writel(0x1, (void __iomem *)&PRCM_CLKCFG_CTRL);
-
+ wmb();
+ }
if (clk->usecount > 0)
_omap2_clk_enable(clk);
* Omap2 clock reset and init functions
*-------------------------------------------------------------------------*/
+#ifdef CONFIG_OMAP_RESET_CLOCKS
+static void __init omap2_clk_disable_unused(struct clk *clk)
+{
+ u32 regval32;
+
+ regval32 = __raw_readl(clk->enable_reg);
+ if ((regval32 & (1 << clk->enable_bit)) == 0)
+ return;
+
+ printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
+ _omap2_clk_disable(clk);
+}
+#else
+#define omap2_clk_disable_unused NULL
+#endif
+
static struct clk_functions omap2_clk_functions = {
.clk_enable = omap2_clk_enable,
.clk_disable = omap2_clk_disable,
.clk_round_rate = omap2_clk_round_rate,
.clk_set_rate = omap2_clk_set_rate,
.clk_set_parent = omap2_clk_set_parent,
+ .clk_disable_unused = omap2_clk_disable_unused,
};
static void __init omap2_get_crystal_rate(struct clk *osc, struct clk *sys)
sys->rate = sclk;
}
-#ifdef CONFIG_OMAP_RESET_CLOCKS
-static void __init omap2_disable_unused_clocks(void)
+/*
+ * Set clocks for bypass mode for reboot to work.
+ */
+void omap2_clk_prepare_for_reboot(void)
{
- struct clk *ck;
- u32 regval32;
-
- list_for_each_entry(ck, &clocks, node) {
- if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) ||
- ck->enable_reg == 0)
- continue;
+ u32 rate;
- regval32 = __raw_readl(ck->enable_reg);
- if ((regval32 & (1 << ck->enable_bit)) == 0)
- continue;
+ if (vclk == NULL || sclk == NULL)
+ return;
- printk(KERN_INFO "Disabling unused clock \"%s\"\n", ck->name);
- _omap2_clk_disable(ck);
- }
+ rate = clk_get_rate(sclk);
+ clk_set_rate(vclk, rate);
}
-late_initcall(omap2_disable_unused_clocks);
-#endif
/*
* Switch the MPU rate if specified on cmdline.
*/
clk_enable(&sync_32k_ick);
clk_enable(&omapctrl_ick);
+
+ /* Force the APLLs active during bootup to avoid disabling and
+ * enabling them unnecessarily. */
+ clk_enable(&apll96_ck);
+ clk_enable(&apll54_ck);
+
if (cpu_is_omap2430())
clk_enable(&sdrc_ick);
+ /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
+ vclk = clk_get(NULL, "virt_prcm_set");
+ sclk = clk_get(NULL, "sys_ck");
+
+ return 0;
+}
+
+static int __init omap2_disable_aplls(void)
+{
+ clk_disable(&apll96_ck);
+ clk_disable(&apll54_ck);
+
return 0;
}
+late_initcall(omap2_disable_aplls);
git.openpandora.org / pandora-kernel.git / blobdiff