+//kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text)
/*
* linux/arch/arm/mach-omap1/clock.c
*
#include <asm/io.h>
+#include <asm/arch/cpu.h>
#include <asm/arch/usb.h>
#include <asm/arch/clock.h>
#include <asm/arch/sram.h>
{
int retval;
- retval = omap1_clk_use(&api_ck.clk);
+ retval = omap1_clk_enable(&api_ck.clk);
if (!retval) {
- retval = omap1_clk_enable(clk);
- omap1_clk_unuse(&api_ck.clk);
+ retval = omap1_clk_enable_generic(clk);
+ omap1_clk_disable(&api_ck.clk);
}
return retval;
static void omap1_clk_disable_dsp_domain(struct clk *clk)
{
- if (omap1_clk_use(&api_ck.clk) == 0) {
- omap1_clk_disable(clk);
- omap1_clk_unuse(&api_ck.clk);
+ if (omap1_clk_enable(&api_ck.clk) == 0) {
+ omap1_clk_disable_generic(clk);
+ omap1_clk_disable(&api_ck.clk);
}
}
int ret;
struct uart_clk *uclk;
- ret = omap1_clk_enable(clk);
+ ret = omap1_clk_enable_generic(clk);
if (ret == 0) {
/* Set smart idle acknowledgement mode */
uclk = (struct uart_clk *)clk;
uclk = (struct uart_clk *)clk;
omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
- omap1_clk_disable(clk);
+ omap1_clk_disable_generic(clk);
}
static void omap1_clk_allow_idle(struct clk *clk)
* Note that DSP_CKCTL virt addr = phys addr, so
* we must use __raw_readw() instead of omap_readw().
*/
- omap1_clk_use(&api_ck.clk);
+ omap1_clk_enable(&api_ck.clk);
dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
- omap1_clk_unuse(&api_ck.clk);
+ omap1_clk_disable(&api_ck.clk);
if (unlikely(clk->rate == clk->parent->rate / dsor))
return; /* No change, quick exit */
/*
* In most cases we should not need to reprogram DPLL.
* Reprogramming the DPLL is tricky, it must be done from SRAM.
+ * (on 730, bit 13 must always be 1)
*/
- omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
+ if (cpu_is_omap730())
+ omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
+ else
+ omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
ck_dpll1.rate = ptr->pll_rate;
propagate_rate(&ck_dpll1);
*/
for (dsor = 2; dsor < 96; ++dsor) {
if ((dsor & 1) && dsor > 8)
- continue;
+ continue;
if (rate >= 96000000 / dsor)
break;
}
clk-> rate = 96000000 / dsor;
}
-static int omap1_clk_use(struct clk *clk)
+static int omap1_clk_enable(struct clk *clk)
{
int ret = 0;
if (clk->usecount++ == 0) {
if (likely(clk->parent)) {
- ret = omap1_clk_use(clk->parent);
+ ret = omap1_clk_enable(clk->parent);
if (unlikely(ret != 0)) {
clk->usecount--;
ret = clk->enable(clk);
if (unlikely(ret != 0) && clk->parent) {
- omap1_clk_unuse(clk->parent);
+ omap1_clk_disable(clk->parent);
clk->usecount--;
}
}
return ret;
}
-static void omap1_clk_unuse(struct clk *clk)
+static void omap1_clk_disable(struct clk *clk)
{
if (clk->usecount > 0 && !(--clk->usecount)) {
clk->disable(clk);
if (likely(clk->parent)) {
- omap1_clk_unuse(clk->parent);
+ omap1_clk_disable(clk->parent);
if (clk->flags & CLOCK_NO_IDLE_PARENT)
if (!cpu_is_omap24xx())
omap1_clk_allow_idle(clk->parent);
}
}
-static int omap1_clk_enable(struct clk *clk)
+static int omap1_clk_enable_generic(struct clk *clk)
{
__u16 regval16;
__u32 regval32;
return 0;
}
-static void omap1_clk_disable(struct clk *clk)
+static void omap1_clk_disable_generic(struct clk *clk)
{
__u16 regval16;
__u32 regval32;
#endif
static struct clk_functions omap1_clk_functions = {
- .clk_use = omap1_clk_use,
- .clk_unuse = omap1_clk_unuse,
+ .clk_enable = omap1_clk_enable,
+ .clk_disable = omap1_clk_disable,
.clk_round_rate = omap1_clk_round_rate,
.clk_set_rate = omap1_clk_set_rate,
};
clk_register(*clkp);
continue;
}
+
+ if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) {
+ clk_register(*clkp);
+ continue;
+ }
}
info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
printk(KERN_ERR "System frequencies not set. Check your config.\n");
/* Guess sane values (60MHz) */
omap_writew(0x2290, DPLL_CTL);
- omap_writew(0x1005, ARM_CKCTL);
+ omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL);
ck_dpll1.rate = 60000000;
propagate_rate(&ck_dpll1);
}
ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
-#ifdef CONFIG_MACH_OMAP_PERSEUS2
+#if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
/* Select slicer output as OMAP input clock */
omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL);
#endif
/* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
- omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
+ /* (on 730, bit 13 must not be cleared) */
+ if (cpu_is_omap730())
+ omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
+ else
+ omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
/* Put DSP/MPUI into reset until needed */
omap_writew(0, ARM_RSTCT1);
* Only enable those clocks we will need, let the drivers
* enable other clocks as necessary
*/
- clk_use(&armper_ck.clk);
- clk_use(&armxor_ck.clk);
- clk_use(&armtim_ck.clk); /* This should be done by timer code */
+ clk_enable(&armper_ck.clk);
+ clk_enable(&armxor_ck.clk);
+ clk_enable(&armtim_ck.clk); /* This should be done by timer code */
- if (cpu_is_omap1510())
+ if (cpu_is_omap15xx())
clk_enable(&arm_gpio_ck);
return 0;
git.openpandora.org / pandora-kernel.git / blobdiff