Merge branch 'next' of git://github.com/kernelslacker/cpufreq

[pandora-kernel.git] / arch / arm / mach-mxs / clock-mx28.c

diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
index 1ad97fe..229ae34 100644 (file)
--- a/arch/arm/mach-mxs/clock-mx28.c
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -295,11 +295,11 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)           \
        unsigned long diff, parent_rate, calc_rate;                     \
        int i;                                                          \
                                                                        \
-       parent_rate = clk_get_rate(clk->parent);                        \
        div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV;       \
        bm_busy = BM_CLKCTRL_##dr##_BUSY;                               \
                                                                        \
        if (clk->parent == &ref_xtal_clk) {                             \
+               parent_rate = clk_get_rate(clk->parent);                \
                div = DIV_ROUND_UP(parent_rate, rate);                  \
                if (clk == &cpu_clk) {                                  \
                        div_max = BM_CLKCTRL_CPU_DIV_XTAL >>            \
@@ -309,6 +309,11 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)            \
                if (div == 0 || div > div_max)                          \
                        return -EINVAL;                                 \
        } else {                                                        \
+               /*                                                      \
+                * hack alert: this block modifies clk->parent, too,    \
+                * so the base to use it the grand parent.              \
+                */                                                     \
+               parent_rate = clk_get_rate(clk->parent->parent);        \
                rate >>= PARENT_RATE_SHIFT;                             \
                parent_rate >>= PARENT_RATE_SHIFT;                      \
                diff = parent_rate;                                     \
@@ -344,7 +349,7 @@ static int name##_set_rate(struct clk *clk, unsigned long rate)             \
                                                                        \
                reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
                reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC;                   \
-               reg |= frac;                                            \
+               reg |= frac << BP_CLKCTRL_##fr##_##fs##FRAC;            \
                __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
        }                                                               \
                                                                        \
@@ -635,6 +640,8 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
        _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
        _REGISTER_CLOCK("imx28-fb", NULL, lcdif_clk)
+       _REGISTER_CLOCK("mxs-saif.0", NULL, saif0_clk)
+       _REGISTER_CLOCK("mxs-saif.1", NULL, saif1_clk)
 };
 
 static int clk_misc_init(void)
@@ -703,11 +710,11 @@ static int clk_misc_init(void)
 
        /* SAIF has to use frac div for functional operation */
        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
-       reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
+       reg |= BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
 
        reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
-       reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
+       reg |= BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
        __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
 
        /*
@@ -733,11 +740,17 @@ static int clk_misc_init(void)
        __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
                        CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
 
-       /* Extra fec clock setting */
-       reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
-       reg &= ~BM_CLKCTRL_ENET_SLEEP;
-       reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
-       __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+       /*
+        * Extra fec clock setting
+        * The DENX M28 uses an external clock source
+        * and the clock output must not be enabled
+        */
+       if (!machine_is_m28evk()) {
+               reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+               reg &= ~BM_CLKCTRL_ENET_SLEEP;
+               reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
+               __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
+       }
 
        /*
         * 480 MHz seems too high to be ssp clock source directly,
@@ -769,6 +782,8 @@ int __init mx28_clocks_init(void)
        clk_enable(&uart_clk);
 
        clk_set_parent(&lcdif_clk, &ref_pix_clk);
+       clk_set_parent(&saif0_clk, &pll0_clk);
+       clk_set_parent(&saif1_clk, &pll0_clk);
 
        clkdev_add_table(lookups, ARRAY_SIZE(lookups));