#include <linux/fec.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include "devices.h"
#include "cpu_op-mx51.h"
-#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */
-#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */
-#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */
-#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */
-#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */
+#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
+#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
+#define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5)
+#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
+#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
+#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
+#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
.nbuttons = ARRAY_SIZE(babbage_buttons),
};
-static struct pad_desc mx51babbage_pads[] = {
+static iomux_v3_cfg_t mx51babbage_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
MX51_PAD_KEY_COL5__I2C2_SDA,
/* HSI2C */
- MX51_PAD_I2C1_CLK__HSI2C_CLK,
- MX51_PAD_I2C1_DAT__HSI2C_DAT,
+ MX51_PAD_I2C1_CLK__I2C1_CLK,
+ MX51_PAD_I2C1_DAT__I2C1_DAT,
/* USB HOST1 */
MX51_PAD_USBH1_CLK__USBH1_CLK,
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
/* USB HUB reset line*/
- MX51_PAD_GPIO_1_7__GPIO_1_7,
+ MX51_PAD_GPIO1_7__GPIO1_7,
/* FEC */
MX51_PAD_EIM_EB2__FEC_MDIO,
- MX51_PAD_EIM_EB3__FEC_RDAT1,
- MX51_PAD_EIM_CS2__FEC_RDAT2,
- MX51_PAD_EIM_CS3__FEC_RDAT3,
+ MX51_PAD_EIM_EB3__FEC_RDATA1,
+ MX51_PAD_EIM_CS2__FEC_RDATA2,
+ MX51_PAD_EIM_CS3__FEC_RDATA3,
MX51_PAD_EIM_CS4__FEC_RX_ER,
MX51_PAD_EIM_CS5__FEC_CRS,
MX51_PAD_NANDF_RB2__FEC_COL,
- MX51_PAD_NANDF_RB3__FEC_RXCLK,
- MX51_PAD_NANDF_RB6__FEC_RDAT0,
- MX51_PAD_NANDF_RB7__FEC_TDAT0,
+ MX51_PAD_NANDF_RB3__FEC_RX_CLK,
+ MX51_PAD_NANDF_D9__FEC_RDATA0,
+ MX51_PAD_NANDF_D8__FEC_TDATA0,
MX51_PAD_NANDF_CS2__FEC_TX_ER,
MX51_PAD_NANDF_CS3__FEC_MDC,
- MX51_PAD_NANDF_CS4__FEC_TDAT1,
- MX51_PAD_NANDF_CS5__FEC_TDAT2,
- MX51_PAD_NANDF_CS6__FEC_TDAT3,
+ MX51_PAD_NANDF_CS4__FEC_TDATA1,
+ MX51_PAD_NANDF_CS5__FEC_TDATA2,
+ MX51_PAD_NANDF_CS6__FEC_TDATA3,
MX51_PAD_NANDF_CS7__FEC_TX_EN,
MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
/* FEC PHY reset line */
- MX51_PAD_EIM_A20__GPIO_2_14,
+ MX51_PAD_EIM_A20__GPIO2_14,
/* SD 1 */
MX51_PAD_SD1_CMD__SD1_CMD,
MX51_PAD_SD2_DATA1__SD2_DATA1,
MX51_PAD_SD2_DATA2__SD2_DATA2,
MX51_PAD_SD2_DATA3__SD2_DATA3,
+
+ /* eCSPI1 */
+ MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
+ MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
+ MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
+ MX51_PAD_CSPI1_SS0__GPIO4_24,
+ MX51_PAD_CSPI1_SS1__GPIO4_25,
};
/* Serial ports */
static int gpio_usbh1_active(void)
{
- struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
- struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5;
+ iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
+ iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5;
int ret;
/* Set USBH1_STP to GPIO and toggle it */
- mxc_iomux_v3_setup_pad(&usbh1stp_gpio);
+ mxc_iomux_v3_setup_pad(usbh1stp_gpio);
ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
if (ret) {
gpio_free(BABBAGE_USBH1_STP);
/* De-assert USB PHY RESETB */
- mxc_iomux_v3_setup_pad(&phyreset_gpio);
+ mxc_iomux_v3_setup_pad(phyreset_gpio);
ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
if (ret) {
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+ if (!usb_base)
+ return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* Set the PHY clock to 19.2MHz */
void __iomem *usbother_base;
usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+ if (!usb_base)
+ return -ENOMEM;
usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
/* The clock for the USBH1 ULPI port will come externally from the PHY. */
}
__setup("otg_mode=", babbage_otg_mode);
+static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
+ {
+ .modalias = "mtd_dataflash",
+ .max_speed_hz = 25000000,
+ .bus_num = 0,
+ .chip_select = 1,
+ .mode = SPI_MODE_0,
+ .platform_data = NULL,
+ },
+};
+
+static int mx51_babbage_spi_cs[] = {
+ BABBAGE_ECSPI1_CS0,
+ BABBAGE_ECSPI1_CS1,
+};
+
+static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
+ .chipselect = mx51_babbage_spi_cs,
+ .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
+};
+
/*
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
- struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
- struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21;
+ iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
+ iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
+ MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
#if defined(CONFIG_CPU_FREQ_IMX)
get_cpu_op = mx51_get_cpu_op;
imx51_add_fec(NULL);
/* Set the PAD settings for the pwr key. */
- power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2;
- mxc_iomux_v3_setup_pad(&power_key);
+ mxc_iomux_v3_setup_pad(power_key);
imx51_add_gpio_keys(&imx_button_data);
imx51_add_imx_i2c(0, &babbage_i2c_data);
gpio_usbh1_active();
mxc_register_device(&mxc_usbh1_device, &usbh1_config);
/* setback USBH1_STP to be function */
- mxc_iomux_v3_setup_pad(&usbh1stp);
+ mxc_iomux_v3_setup_pad(usbh1stp);
babbage_usbhub_reset();
- imx51_add_esdhc(0, NULL);
- imx51_add_esdhc(1, NULL);
+ imx51_add_sdhci_esdhc_imx(0, NULL);
+ imx51_add_sdhci_esdhc_imx(1, NULL);
+
+ spi_register_board_info(mx51_babbage_spi_board_info,
+ ARRAY_SIZE(mx51_babbage_spi_board_info));
+ imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
+ imx51_add_imx2_wdt(0, NULL);
}
static void __init mx51_babbage_timer_init(void)
git.openpandora.org / pandora-kernel.git / blobdiff