#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
-#define CCM_CSCR_USB_OFFSET 28
-#define CCM_CSCR_USB_MASK (0x7 << 28)
+#define CCM_CSCR_PRESC_OFFSET 29
+#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
+
+#define CCM_CSCR_USB_OFFSET 26
+#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
#define CCM_CSCR_SD_OFFSET 24
-#define CCM_CSCR_SD_MASK (0x3 << 24)
-#define CCM_CSCR_SSI2 (1 << 23)
-#define CCM_CSCR_SSI2_OFFSET 23
-#define CCM_CSCR_SSI1 (1 << 22)
-#define CCM_CSCR_SSI1_OFFSET 22
-#define CCM_CSCR_VPU (1 << 21)
-#define CCM_CSCR_VPU_OFFSET 21
-#define CCM_CSCR_MSHC (1 << 20)
-#define CCM_CSCR_SPLLRES (1 << 19)
-#define CCM_CSCR_MPLLRES (1 << 18)
+#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
+#define CCM_CSCR_SPLLRES (1 << 22)
+#define CCM_CSCR_MPLLRES (1 << 21)
+#define CCM_CSCR_SSI2_OFFSET 20
+#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
+#define CCM_CSCR_SSI1_OFFSET 19
+#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
+#define CCM_CSCR_FIR_OFFSET 18
+#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
#define CCM_CSCR_SP (1 << 17)
#define CCM_CSCR_MCU (1 << 16)
-/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
-#define CCM_CSCR_ARM_SRC (1 << 15)
-#define CCM_CSCR_ARM_OFFSET 12
-#define CCM_CSCR_ARM_MASK (0x3 << 12)
-/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/
-#define CCM_CSCR_PRESC_OFFSET 13
-#define CCM_CSCR_PRESC_MASK (0x7 << 13)
-#define CCM_CSCR_BCLK_OFFSET 9
-#define CCM_CSCR_BCLK_MASK (0xf << 9)
-#define CCM_CSCR_IPDIV_OFFSET 8
-#define CCM_CSCR_IPDIV (1 << 8)
-/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
-#define CCM_CSCR_AHB_OFFSET 8
-#define CCM_CSCR_AHB_MASK (0x3 << 8)
-/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
+#define CCM_CSCR_BCLK_OFFSET 10
+#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
+#define CCM_CSCR_IPDIV_OFFSET 9
+#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
+
#define CCM_CSCR_OSC26MDIV (1 << 4)
#define CCM_CSCR_OSC26M (1 << 3)
#define CCM_CSCR_FPM (1 << 2)
#define CCM_CSCR_SPEN (1 << 1)
#define CCM_CSCR_MPEN 1
+
+
#define CCM_MPCTL0_CPLM (1 << 31)
#define CCM_MPCTL0_PD_OFFSET 26
#define CCM_MPCTL0_PD_MASK (0xf << 26)
#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
-#define CCM_PCDR0_CLKO_EN 25
-#define CCM_PCDR0_CLKODIV_OFFSET 22
-#define CCM_PCDR0_CLKODIV_MASK (0x7 << 22)
#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
-/*The difinition for i.MX27 TO2*/
-#define CCM_PCDR0_VPUDIV2_OFFSET 10
-#define CCM_PCDR0_VPUDIV2_MASK (0x3f << 10)
-#define CCM_PCDR0_NFCDIV2_OFFSET 6
-#define CCM_PCDR0_NFCDIV2_MASK (0xf << 6)
-#define CCM_PCDR0_MSHCDIV2_MASK 0x3f
-/*The difinition for i.MX27 TO2*/
#define CCM_PCDR0_NFCDIV_OFFSET 12
#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
-#define CCM_PCDR0_VPUDIV_OFFSET 8
-#define CCM_PCDR0_VPUDIV_MASK (0xf << 8)
-#define CCM_PCDR0_MSHCDIV_OFFSET 0
-#define CCM_PCDR0_MSHCDIV_MASK 0x1f
-
+#define CCM_PCDR0_48MDIV_OFFSET 5
+#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
+#define CCM_PCDR0_FIRIDIV_OFFSET 0
+#define CCM_PCDR0_FIRIDIV_MASK 0x1f
#define CCM_PCDR1_PERDIV4_OFFSET 24
#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
#define CCM_PCDR1_PERDIV3_OFFSET 16
#define CCM_PCDR1_PERDIV1_OFFSET 0
#define CCM_PCDR1_PERDIV1_MASK 0x3f
-#define CCM_PCCR0_CSPI1_OFFSET 31
-#define CCM_PCCR0_CSPI1_MASK (1 << 31)
-#define CCM_PCCR0_CSPI2_OFFSET 30
-#define CCM_PCCR0_CSPI2_MASK (1 << 30)
-#define CCM_PCCR0_CSPI3_OFFSET 29
-#define CCM_PCCR0_CSPI3_MASK (1 << 29)
-#define CCM_PCCR0_DMA_OFFSET 28
-#define CCM_PCCR0_DMA_MASK (1 << 28)
-#define CCM_PCCR0_EMMA_OFFSET 27
-#define CCM_PCCR0_EMMA_MASK (1 << 27)
-#define CCM_PCCR0_FEC_OFFSET 26
-#define CCM_PCCR0_FEC_MASK (1 << 26)
-#define CCM_PCCR0_GPIO_OFFSET 25
-#define CCM_PCCR0_GPIO_MASK (1 << 25)
-#define CCM_PCCR0_GPT1_OFFSET 24
-#define CCM_PCCR0_GPT1_MASK (1 << 24)
-#define CCM_PCCR0_GPT2_OFFSET 23
-#define CCM_PCCR0_GPT2_MASK (1 << 23)
-#define CCM_PCCR0_GPT3_OFFSET 22
-#define CCM_PCCR0_GPT3_MASK (1 << 22)
-#define CCM_PCCR0_GPT4_OFFSET 21
-#define CCM_PCCR0_GPT4_MASK (1 << 21)
-#define CCM_PCCR0_GPT5_OFFSET 20
-#define CCM_PCCR0_GPT5_MASK (1 << 20)
-#define CCM_PCCR0_GPT6_OFFSET 19
-#define CCM_PCCR0_GPT6_MASK (1 << 19)
-#define CCM_PCCR0_I2C1_OFFSET 18
-#define CCM_PCCR0_I2C1_MASK (1 << 18)
-#define CCM_PCCR0_I2C2_OFFSET 17
-#define CCM_PCCR0_I2C2_MASK (1 << 17)
-#define CCM_PCCR0_IIM_OFFSET 16
-#define CCM_PCCR0_IIM_MASK (1 << 16)
-#define CCM_PCCR0_KPP_OFFSET 15
-#define CCM_PCCR0_KPP_MASK (1 << 15)
-#define CCM_PCCR0_LCDC_OFFSET 14
-#define CCM_PCCR0_LCDC_MASK (1 << 14)
-#define CCM_PCCR0_MSHC_OFFSET 13
-#define CCM_PCCR0_MSHC_MASK (1 << 13)
-#define CCM_PCCR0_OWIRE_OFFSET 12
-#define CCM_PCCR0_OWIRE_MASK (1 << 12)
-#define CCM_PCCR0_PWM_OFFSET 11
-#define CCM_PCCR0_PWM_MASK (1 << 11)
-#define CCM_PCCR0_RTC_OFFSET 9
-#define CCM_PCCR0_RTC_MASK (1 << 9)
-#define CCM_PCCR0_RTIC_OFFSET 8
-#define CCM_PCCR0_RTIC_MASK (1 << 8)
-#define CCM_PCCR0_SAHARA_OFFSET 7
-#define CCM_PCCR0_SAHARA_MASK (1 << 7)
-#define CCM_PCCR0_SCC_OFFSET 6
-#define CCM_PCCR0_SCC_MASK (1 << 6)
-#define CCM_PCCR0_SDHC1_OFFSET 5
-#define CCM_PCCR0_SDHC1_MASK (1 << 5)
-#define CCM_PCCR0_SDHC2_OFFSET 4
-#define CCM_PCCR0_SDHC2_MASK (1 << 4)
-#define CCM_PCCR0_SDHC3_OFFSET 3
-#define CCM_PCCR0_SDHC3_MASK (1 << 3)
-#define CCM_PCCR0_SLCDC_OFFSET 2
-#define CCM_PCCR0_SLCDC_MASK (1 << 2)
-#define CCM_PCCR0_SSI1_IPG_OFFSET 1
-#define CCM_PCCR0_SSI1_IPG_MASK (1 << 1)
-#define CCM_PCCR0_SSI2_IPG_OFFSET 0
-#define CCM_PCCR0_SSI2_IPG_MASK (1 << 0)
+#define CCM_PCCR_HCLK_CSI_OFFSET 31
+#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_DMA_OFFSET 30
+#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_BROM_OFFSET 28
+#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_EMMA_OFFSET 27
+#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_LCDC_OFFSET 26
+#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
+#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
+#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
+#define CCM_PCCR_HCLK_BMI_OFFSET 23
+#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
+#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
+#define CCM_PCCR_PERCLK4_OFFSET 22
+#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
+#define CCM_PCCR_SLCDC_OFFSET 21
+#define CCM_PCCR_SLCDC_REG CCM_PCCR0
+#define CCM_PCCR_FIRI_BAUD_OFFSET 20
+#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
+#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
+#define CCM_PCCR_NFC_OFFSET 19
+#define CCM_PCCR_NFC_REG CCM_PCCR0
+#define CCM_PCCR_LCDC_OFFSET 18
+#define CCM_PCCR_LCDC_REG CCM_PCCR0
+#define CCM_PCCR_SSI1_BAUD_OFFSET 17
+#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
+#define CCM_PCCR_SSI2_BAUD_OFFSET 16
+#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
+#define CCM_PCCR_EMMA_OFFSET 15
+#define CCM_PCCR_EMMA_REG CCM_PCCR0
+#define CCM_PCCR_USBOTG_OFFSET 14
+#define CCM_PCCR_USBOTG_REG CCM_PCCR0
+#define CCM_PCCR_DMA_OFFSET 13
+#define CCM_PCCR_DMA_REG CCM_PCCR0
+#define CCM_PCCR_I2C1_OFFSET 12
+#define CCM_PCCR_I2C1_REG CCM_PCCR0
+#define CCM_PCCR_GPIO_OFFSET 11
+#define CCM_PCCR_GPIO_REG CCM_PCCR0
+#define CCM_PCCR_SDHC2_OFFSET 10
+#define CCM_PCCR_SDHC2_REG CCM_PCCR0
+#define CCM_PCCR_SDHC1_OFFSET 9
+#define CCM_PCCR_SDHC1_REG CCM_PCCR0
+#define CCM_PCCR_FIRI_OFFSET 8
+#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
+#define CCM_PCCR_FIRI_REG CCM_PCCR0
+#define CCM_PCCR_SSI2_IPG_OFFSET 7
+#define CCM_PCCR_SSI2_REG CCM_PCCR0
+#define CCM_PCCR_SSI1_IPG_OFFSET 6
+#define CCM_PCCR_SSI1_REG CCM_PCCR0
+#define CCM_PCCR_CSPI2_OFFSET 5
+#define CCM_PCCR_CSPI2_REG CCM_PCCR0
+#define CCM_PCCR_CSPI1_OFFSET 4
+#define CCM_PCCR_CSPI1_REG CCM_PCCR0
+#define CCM_PCCR_UART4_OFFSET 3
+#define CCM_PCCR_UART4_REG CCM_PCCR0
+#define CCM_PCCR_UART3_OFFSET 2
+#define CCM_PCCR_UART3_REG CCM_PCCR0
+#define CCM_PCCR_UART2_OFFSET 1
+#define CCM_PCCR_UART2_REG CCM_PCCR0
+#define CCM_PCCR_UART1_OFFSET 0
+#define CCM_PCCR_UART1_REG CCM_PCCR0
+
+#define CCM_PCCR_OWIRE_OFFSET 31
+#define CCM_PCCR_OWIRE_REG CCM_PCCR1
+#define CCM_PCCR_KPP_OFFSET 30
+#define CCM_PCCR_KPP_REG CCM_PCCR1
+#define CCM_PCCR_RTC_OFFSET 29
+#define CCM_PCCR_RTC_REG CCM_PCCR1
+#define CCM_PCCR_PWM_OFFSET 28
+#define CCM_PCCR_PWM_REG CCM_PCCR1
+#define CCM_PCCR_GPT3_OFFSET 27
+#define CCM_PCCR_GPT3_REG CCM_PCCR1
+#define CCM_PCCR_GPT2_OFFSET 26
+#define CCM_PCCR_GPT2_REG CCM_PCCR1
+#define CCM_PCCR_GPT1_OFFSET 25
+#define CCM_PCCR_GPT1_REG CCM_PCCR1
+#define CCM_PCCR_WDT_OFFSET 24
+#define CCM_PCCR_WDT_REG CCM_PCCR1
+#define CCM_PCCR_CSPI3_OFFSET 23
+#define CCM_PCCR_CSPI3_REG CCM_PCCR1
+
+#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
+#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
+#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
+#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
+#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
+#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
+#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
+#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
+#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
+#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
+#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
+#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
+#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
+#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
+#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
+#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
+#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
+#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
+#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
+#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
+#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
+#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
+#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
+#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
+#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
+#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
+#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
+#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
+#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
+#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
+#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
+#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
+#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
+#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
+#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
+#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
+#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
-#define CCM_PCCR1_UART1_OFFSET 31
-#define CCM_PCCR1_UART1_MASK (1 << 31)
-#define CCM_PCCR1_UART2_OFFSET 30
-#define CCM_PCCR1_UART2_MASK (1 << 30)
-#define CCM_PCCR1_UART3_OFFSET 29
-#define CCM_PCCR1_UART3_MASK (1 << 29)
-#define CCM_PCCR1_UART4_OFFSET 28
-#define CCM_PCCR1_UART4_MASK (1 << 28)
-#define CCM_PCCR1_UART5_OFFSET 27
-#define CCM_PCCR1_UART5_MASK (1 << 27)
-#define CCM_PCCR1_UART6_OFFSET 26
-#define CCM_PCCR1_UART6_MASK (1 << 26)
-#define CCM_PCCR1_USBOTG_OFFSET 25
-#define CCM_PCCR1_USBOTG_MASK (1 << 25)
-#define CCM_PCCR1_WDT_OFFSET 24
-#define CCM_PCCR1_WDT_MASK (1 << 24)
-#define CCM_PCCR1_HCLK_ATA_OFFSET 23
-#define CCM_PCCR1_HCLK_ATA_MASK (1 << 23)
-#define CCM_PCCR1_HCLK_BROM_OFFSET 22
-#define CCM_PCCR1_HCLK_BROM_MASK (1 << 22)
-#define CCM_PCCR1_HCLK_CSI_OFFSET 21
-#define CCM_PCCR1_HCLK_CSI_MASK (1 << 21)
-#define CCM_PCCR1_HCLK_DMA_OFFSET 20
-#define CCM_PCCR1_HCLK_DMA_MASK (1 << 20)
-#define CCM_PCCR1_HCLK_EMI_OFFSET 19
-#define CCM_PCCR1_HCLK_EMI_MASK (1 << 19)
-#define CCM_PCCR1_HCLK_EMMA_OFFSET 18
-#define CCM_PCCR1_HCLK_EMMA_MASK (1 << 18)
-#define CCM_PCCR1_HCLK_FEC_OFFSET 17
-#define CCM_PCCR1_HCLK_FEC_MASK (1 << 17)
-#define CCM_PCCR1_HCLK_VPU_OFFSET 16
-#define CCM_PCCR1_HCLK_VPU_MASK (1 << 16)
-#define CCM_PCCR1_HCLK_LCDC_OFFSET 15
-#define CCM_PCCR1_HCLK_LCDC_MASK (1 << 15)
-#define CCM_PCCR1_HCLK_RTIC_OFFSET 14
-#define CCM_PCCR1_HCLK_RTIC_MASK (1 << 14)
-#define CCM_PCCR1_HCLK_SAHARA_OFFSET 13
-#define CCM_PCCR1_HCLK_SAHARA_MASK (1 << 13)
-#define CCM_PCCR1_HCLK_SLCDC_OFFSET 12
-#define CCM_PCCR1_HCLK_SLCDC_MASK (1 << 12)
-#define CCM_PCCR1_HCLK_USBOTG_OFFSET 11
-#define CCM_PCCR1_HCLK_USBOTG_MASK (1 << 11)
-#define CCM_PCCR1_PERCLK1_OFFSET 10
-#define CCM_PCCR1_PERCLK1_MASK (1 << 10)
-#define CCM_PCCR1_PERCLK2_OFFSET 9
-#define CCM_PCCR1_PERCLK2_MASK (1 << 9)
-#define CCM_PCCR1_PERCLK3_OFFSET 8
-#define CCM_PCCR1_PERCLK3_MASK (1 << 8)
-#define CCM_PCCR1_PERCLK4_OFFSET 7
-#define CCM_PCCR1_PERCLK4_MASK (1 << 7)
-#define CCM_PCCR1_VPU_BAUD_OFFSET 6
-#define CCM_PCCR1_VPU_BAUD_MASK (1 << 6)
-#define CCM_PCCR1_SSI1_BAUD_OFFSET 5
-#define CCM_PCCR1_SSI1_BAUD_MASK (1 << 5)
-#define CCM_PCCR1_SSI2_BAUD_OFFSET 4
-#define CCM_PCCR1_SSI2_BAUD_MASK (1 << 4)
-#define CCM_PCCR1_NFC_BAUD_OFFSET 3
-#define CCM_PCCR1_NFC_BAUD_MASK (1 << 3)
-#define CCM_PCCR1_MSHC_BAUD_OFFSET 2
-#define CCM_PCCR1_MSHC_BAUD_MASK (1 << 2)
#define CCM_CCSR_32KSR (1 << 15)
+
#define CCM_CCSR_CLKMODE1 (1 << 9)
#define CCM_CCSR_CLKMODE0 (1 << 8)
+
#define CCM_CCSR_CLKOSEL_OFFSET 0
#define CCM_CCSR_CLKOSEL_MASK 0x1f
git.openpandora.org / pandora-kernel.git / blobdiff