Merge branch 'iop-raid6' into async-tx-next

[pandora-kernel.git] / arch / arm / mach-mv78xx0 / include / mach / mv78xx0.h

diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 582cffc..d715b92 100644 (file)
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -59,37 +59,6 @@
  * Core-specific peripheral registers.
  */
 #define BRIDGE_VIRT_BASE       (MV78XX0_CORE_REGS_VIRT_BASE)
-#define  CPU_CONTROL           (BRIDGE_VIRT_BASE | 0x0104)
-#define   L2_WRITETHROUGH      0x00020000
-#define  RSTOUTn_MASK          (BRIDGE_VIRT_BASE | 0x0108)
-#define   SOFT_RESET_OUT_EN    0x00000004
-#define  SYSTEM_SOFT_RESET     (BRIDGE_VIRT_BASE | 0x010c)
-#define   SOFT_RESET           0x00000001
-#define  BRIDGE_CAUSE          (BRIDGE_VIRT_BASE | 0x0110)
-#define  BRIDGE_MASK           (BRIDGE_VIRT_BASE | 0x0114)
-#define   BRIDGE_INT_TIMER0    0x0002
-#define   BRIDGE_INT_TIMER1    0x0004
-#define   BRIDGE_INT_TIMER1_CLR        (~0x0004)
-#define  IRQ_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0200)
-#define   IRQ_CAUSE_ERR_OFF    0x0000
-#define   IRQ_CAUSE_LOW_OFF    0x0004
-#define   IRQ_CAUSE_HIGH_OFF   0x0008
-#define   IRQ_MASK_ERR_OFF     0x000c
-#define   IRQ_MASK_LOW_OFF     0x0010
-#define   IRQ_MASK_HIGH_OFF    0x0014
-#define  TIMER_VIRT_BASE       (BRIDGE_VIRT_BASE | 0x0300)
-
-/*
- * Supported devices and revisions.
- */
-#define MV78X00_Z0_DEV_ID      0x6381
-#define MV78X00_REV_Z0         1
-
-#define MV78100_DEV_ID         0x7810
-#define MV78100_REV_A0         1
-
-#define MV78200_DEV_ID         0x7820
-#define MV78200_REV_A0         1
 
 /*
  * Register Map
@@ -135,5 +104,16 @@
 
 #define SATA_PHYS_BASE         (MV78XX0_REGS_PHYS_BASE | 0xa0000)
 
+/*
+ * Supported devices and revisions.
+ */
+#define MV78X00_Z0_DEV_ID      0x6381
+#define MV78X00_REV_Z0         1
+
+#define MV78100_DEV_ID         0x7810
+#define MV78100_REV_A0         1
+
+#define MV78200_DEV_ID         0x7820
+#define MV78200_REV_A0         1
 
 #endif