Merge branch 'at91/cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm...

[pandora-kernel.git] / arch / arm / mach-exynos4 / include / mach / regs-clock.h

diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1..d493fdb 100644 (file)
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
 #define S5P_CLKDIV_STAT_RIGHTBUS       S5P_CLKREG(0x08600)
 #define S5P_CLKGATE_IP_RIGHTBUS                S5P_CLKREG(0x08800)
 
+#define S5P_EPLL_LOCK                  S5P_CLKREG(0x0C010)
+#define S5P_VPLL_LOCK                  S5P_CLKREG(0x0C020)
+
 #define S5P_EPLL_CON0                  S5P_CLKREG(0x0C110)
 #define S5P_EPLL_CON1                  S5P_CLKREG(0x0C114)
 #define S5P_VPLL_CON0                  S5P_CLKREG(0x0C120)
@@ -33,7 +36,9 @@
 #define S5P_CLKSRC_TOP0                        S5P_CLKREG(0x0C210)
 #define S5P_CLKSRC_TOP1                        S5P_CLKREG(0x0C214)
 #define S5P_CLKSRC_CAM                 S5P_CLKREG(0x0C220)
+#define S5P_CLKSRC_TV                  S5P_CLKREG(0x0C224)
 #define S5P_CLKSRC_MFC                 S5P_CLKREG(0x0C228)
+#define S5P_CLKSRC_G3D                 S5P_CLKREG(0x0C22C)
 #define S5P_CLKSRC_IMAGE               S5P_CLKREG(0x0C230)
 #define S5P_CLKSRC_LCD0                        S5P_CLKREG(0x0C234)
 #define S5P_CLKSRC_LCD1                        S5P_CLKREG(0x0C238)
@@ -61,6 +66,7 @@
 #define S5P_CLKDIV_PERIL3              S5P_CLKREG(0x0C55C)
 #define S5P_CLKDIV_PERIL4              S5P_CLKREG(0x0C560)
 #define S5P_CLKDIV_PERIL5              S5P_CLKREG(0x0C564)
+#define S5P_CLKDIV2_RATIO              S5P_CLKREG(0x0C580)
 
 #define S5P_CLKSRC_MASK_TOP            S5P_CLKREG(0x0C310)
 #define S5P_CLKSRC_MASK_CAM            S5P_CLKREG(0x0C320)
@@ -120,6 +126,12 @@
 #define S5P_APLL_VAL_1000              ((250 << 16) | (6 << 8) | 1)
 #define S5P_APLL_VAL_800               ((200 << 16) | (6 << 8) | 1)
 
+#define S5P_EPLLCON0_ENABLE_SHIFT      (31)
+#define S5P_EPLLCON0_LOCKED_SHIFT      (29)
+
+#define S5P_VPLLCON0_ENABLE_SHIFT      (31)
+#define S5P_VPLLCON0_LOCKED_SHIFT      (29)
+
 #define S5P_CLKSRC_CPU_MUXCORE_SHIFT   (16)
 #define S5P_CLKMUX_STATCPU_MUXCORE_MASK        (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)