Merge branch 'fix/misc' into for-linus

[pandora-kernel.git] / arch / arm / mach-davinci / include / mach / da8xx.h

diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 9070491..03acfd3 100644 (file)
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -3,7 +3,7 @@
  *
  * Author: Mark A. Greer <mgreer@mvista.com>
  *
- * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * 2007, 2009-2010 (c) MontaVista Software, Inc. This file is licensed under
  * the terms of the GNU General Public License version 2. This program
  * is licensed "as is" without any warranty of any kind, whether express
  * or implied.
@@ -13,15 +13,19 @@
 
 #include <video/da8xx-fb.h>
 
+#include <linux/platform_device.h>
+#include <linux/davinci_emac.h>
+
 #include <mach/serial.h>
 #include <mach/edma.h>
 #include <mach/i2c.h>
-#include <mach/emac.h>
 #include <mach/asp.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
+#include <mach/pm.h>
 
-extern void __iomem *da8xx_syscfg_base;
+extern void __iomem *da8xx_syscfg0_base;
+extern void __iomem *da8xx_syscfg1_base;
 
 /*
  * The cp_intc interrupt controller for the da8xx isn't in the same
@@ -34,13 +38,17 @@ extern void __iomem *da8xx_syscfg_base;
 #define DA8XX_CP_INTC_SIZE     SZ_8K
 #define DA8XX_CP_INTC_VIRT     (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
 
-#define DA8XX_SYSCFG_BASE      (IO_PHYS + 0x14000)
-#define DA8XX_SYSCFG_VIRT(x)   (da8xx_syscfg_base + (x))
+#define DA8XX_SYSCFG0_BASE     (IO_PHYS + 0x14000)
+#define DA8XX_SYSCFG0_VIRT(x)  (da8xx_syscfg0_base + (x))
 #define DA8XX_JTAG_ID_REG      0x18
 #define DA8XX_CFGCHIP0_REG     0x17c
 #define DA8XX_CFGCHIP2_REG     0x184
 #define DA8XX_CFGCHIP3_REG     0x188
 
+#define DA8XX_SYSCFG1_BASE     (IO_PHYS + 0x22C000)
+#define DA8XX_SYSCFG1_VIRT(x)  (da8xx_syscfg1_base + (x))
+#define DA8XX_DEEPSLEEP_REG    0x8
+
 #define DA8XX_PSC0_BASE                0x01c10000
 #define DA8XX_PLL0_BASE                0x01c11000
 #define DA8XX_TIMER64P0_BASE   0x01c20000
@@ -48,11 +56,13 @@ extern void __iomem *da8xx_syscfg_base;
 #define DA8XX_GPIO_BASE                0x01e26000
 #define DA8XX_PSC1_BASE                0x01e27000
 #define DA8XX_LCD_CNTRL_BASE   0x01e13000
+#define DA8XX_PLL1_BASE                0x01e1a000
 #define DA8XX_MMCSD0_BASE      0x01c40000
 #define DA8XX_AEMIF_CS2_BASE   0x60000000
 #define DA8XX_AEMIF_CS3_BASE   0x62000000
 #define DA8XX_AEMIF_CTL_BASE   0x68000000
 #define DA8XX_DDR2_CTL_BASE    0xb0000000
+#define DA8XX_ARM_RAM_BASE     0xffff0000
 
 #define PINMUX0                        0x00
 #define PINMUX1                        0x04
@@ -90,6 +100,8 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
 int da8xx_register_rtc(void);
 int da850_register_cpufreq(void);
 int da8xx_register_cpuidle(void);
+void __iomem * __init da8xx_get_mem_ctlr(void);
+int da850_register_pm(struct platform_device *pdev);
 
 extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
@@ -134,6 +146,10 @@ extern const short da850_mmcsd0_pins[];
 extern const short da850_nand_pins[];
 extern const short da850_nor_pins[];
 
+#ifdef CONFIG_DAVINCI_MUX
 int da8xx_pinmux_setup(const short pins[]);
+#else
+static inline int da8xx_pinmux_setup(const short pins[]) { return 0; }
+#endif
 
 #endif /* __ASM_ARCH_DAVINCI_DA8XX_H */