Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6

[pandora-kernel.git] / arch / arm / mach-at91 / include / mach / at91_dbgu.h

diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 6dcaa77..dbfe455 100644 (file)
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -16,22 +16,25 @@
 #ifndef AT91_DBGU_H
 #define AT91_DBGU_H
 
+#define dbgu_readl(dbgu, field) \
+       __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
+
 #ifdef AT91_DBGU
-#define AT91_DBGU_CR           (AT91_DBGU + 0x00)      /* Control Register */
-#define AT91_DBGU_MR           (AT91_DBGU + 0x04)      /* Mode Register */
-#define AT91_DBGU_IER          (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
+#define AT91_DBGU_CR           (0x00)  /* Control Register */
+#define AT91_DBGU_MR           (0x04)  /* Mode Register */
+#define AT91_DBGU_IER          (0x08)  /* Interrupt Enable Register */
 #define                AT91_DBGU_TXRDY         (1 << 1)                /* Transmitter Ready */
 #define                AT91_DBGU_TXEMPTY       (1 << 9)                /* Transmitter Empty */
-#define AT91_DBGU_IDR          (AT91_DBGU + 0x0c)      /* Interrupt Disable Register */
-#define AT91_DBGU_IMR          (AT91_DBGU + 0x10)      /* Interrupt Mask Register */
-#define AT91_DBGU_SR           (AT91_DBGU + 0x14)      /* Status Register */
-#define AT91_DBGU_RHR          (AT91_DBGU + 0x18)      /* Receiver Holding Register */
-#define AT91_DBGU_THR          (AT91_DBGU + 0x1c)      /* Transmitter Holding Register */
-#define AT91_DBGU_BRGR         (AT91_DBGU + 0x20)      /* Baud Rate Generator Register */
+#define AT91_DBGU_IDR          (0x0c)  /* Interrupt Disable Register */
+#define AT91_DBGU_IMR          (0x10)  /* Interrupt Mask Register */
+#define AT91_DBGU_SR           (0x14)  /* Status Register */
+#define AT91_DBGU_RHR          (0x18)  /* Receiver Holding Register */
+#define AT91_DBGU_THR          (0x1c)  /* Transmitter Holding Register */
+#define AT91_DBGU_BRGR         (0x20)  /* Baud Rate Generator Register */
 
-#define AT91_DBGU_CIDR         (AT91_DBGU + 0x40)      /* Chip ID Register */
-#define AT91_DBGU_EXID         (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
-#define AT91_DBGU_FNR          (AT91_DBGU + 0x48)      /* Force NTRST Register [SAM9 only] */
+#define AT91_DBGU_CIDR         (0x40)  /* Chip ID Register */
+#define AT91_DBGU_EXID         (0x44)  /* Chip ID Extension Register */
+#define AT91_DBGU_FNR          (0x48)  /* Force NTRST Register [SAM9 only] */
 #define                AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
 
 #endif /* AT91_DBGU */