Merge master.kernel.org:/pub/scm/linux/kernel/git/sfrench/cifs-2.6

[pandora-kernel.git] / arch / arm / mach-at91 / at91sam9260.c

diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index ffc4c09..6ea41d8 100644 (file)
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -14,6 +14,7 @@
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
@@ -27,7 +28,11 @@ static struct map_desc at91sam9260_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
                .length         = SZ_16K,
                .type           = MT_DEVICE,
-       }, {
+       }
+};
+
+static struct map_desc at91sam9260_sram_desc[] __initdata = {
+       {
                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9260_SRAM0_SIZE,
                .pfn            = __phys_to_pfn(AT91SAM9260_SRAM0_BASE),
                .length         = AT91SAM9260_SRAM0_SIZE,
@@ -37,7 +42,14 @@ static struct map_desc at91sam9260_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(AT91SAM9260_SRAM1_BASE),
                .length         = AT91SAM9260_SRAM1_SIZE,
                .type           = MT_DEVICE,
-       },
+       }
+};
+
+static struct map_desc at91sam9xe_sram_desc[] __initdata = {
+       {
+               .pfn            = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
+               .type           = MT_DEVICE,
+       }
 };
 
 /* --------------------------------------------------------------------
@@ -107,13 +119,28 @@ static struct clk spi1_clk = {
        .pmc_mask       = 1 << AT91SAM9260_ID_SPI1,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk tc0_clk = {
+       .name           = "tc0_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC0,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+       .name           = "tc1_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC1,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+       .name           = "tc2_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC2,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
 static struct clk ohci_clk = {
        .name           = "ohci_clk",
        .pmc_mask       = 1 << AT91SAM9260_ID_UHP,
        .type           = CLK_TYPE_PERIPHERAL,
 };
-static struct clk ether_clk = {
-       .name           = "ether_clk",
+static struct clk macb_clk = {
+       .name           = "macb_clk",
        .pmc_mask       = 1 << AT91SAM9260_ID_EMAC,
        .type           = CLK_TYPE_PERIPHERAL,
 };
@@ -137,6 +164,21 @@ static struct clk usart5_clk = {
        .pmc_mask       = 1 << AT91SAM9260_ID_US5,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk tc3_clk = {
+       .name           = "tc3_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC3,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc4_clk = {
+       .name           = "tc4_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC4,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc5_clk = {
+       .name           = "tc5_clk",
+       .pmc_mask       = 1 << AT91SAM9260_ID_TC5,
+       .type           = CLK_TYPE_PERIPHERAL,
+};
 
 static struct clk *periph_clocks[] __initdata = {
        &pioA_clk,
@@ -152,14 +194,18 @@ static struct clk *periph_clocks[] __initdata = {
        &spi0_clk,
        &spi1_clk,
        // ssc
-       // tc0 .. tc2
+       &tc0_clk,
+       &tc1_clk,
+       &tc2_clk,
        &ohci_clk,
-       &ether_clk,
+       &macb_clk,
        &isi_clk,
        &usart3_clk,
        &usart4_clk,
        &usart5_clk,
-       // tc3 .. tc5
+       &tc3_clk,
+       &tc4_clk,
+       &tc5_clk,
        // irq0 .. irq2
 };
 
@@ -213,7 +259,7 @@ static struct at91_gpio_bank at91sam9260_gpio[] = {
 
 static void at91sam9260_reset(void)
 {
-       at91_sys_write(AT91_RSTC_CR, (0xA5 << 24) | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+       at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
 
@@ -221,11 +267,37 @@ static void at91sam9260_reset(void)
  *  AT91SAM9260 processor initialization
  * -------------------------------------------------------------------- */
 
+static void __init at91sam9xe_initialize(void)
+{
+       unsigned long cidr, sram_size;
+
+       cidr = at91_sys_read(AT91_DBGU_CIDR);
+
+       switch (cidr & AT91_CIDR_SRAMSIZ) {
+               case AT91_CIDR_SRAMSIZ_32K:
+                       sram_size = 2 * SZ_16K;
+                       break;
+               case AT91_CIDR_SRAMSIZ_16K:
+               default:
+                       sram_size = SZ_16K;
+       }
+
+       at91sam9xe_sram_desc->virtual = AT91_IO_VIRT_BASE - sram_size;
+       at91sam9xe_sram_desc->length = sram_size;
+
+       iotable_init(at91sam9xe_sram_desc, ARRAY_SIZE(at91sam9xe_sram_desc));
+}
+
 void __init at91sam9260_initialize(unsigned long main_clock)
 {
        /* Map peripherals */
        iotable_init(at91sam9260_io_desc, ARRAY_SIZE(at91sam9260_io_desc));
 
+       if (cpu_is_at91sam9xe())
+               at91sam9xe_initialize();
+       else
+               iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
+
        at91_arch_reset = at91sam9260_reset;
        at91_extern_irq = (1 << AT91SAM9260_ID_IRQ0) | (1 << AT91SAM9260_ID_IRQ1)
                        | (1 << AT91SAM9260_ID_IRQ2);