Merge branch 'next' of git://github.com/kernelslacker/cpufreq

[pandora-kernel.git] / arch / arm / kernel / perf_event_v6.c

diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index 8390128..e63d811 100644 (file)
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -433,6 +433,7 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
                      int idx)
 {
        unsigned long val, mask, evt, flags;
+       struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
        if (ARMV6_CYCLE_COUNTER == idx) {
                mask    = 0;
@@ -454,12 +455,12 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
         * Mask out the current event and set the counter to count the event
         * that we're interested in.
         */
-       raw_spin_lock_irqsave(&pmu_lock, flags);
+       raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = armv6_pmcr_read();
        val &= ~mask;
        val |= evt;
        armv6_pmcr_write(val);
-       raw_spin_unlock_irqrestore(&pmu_lock, flags);
+       raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static int counter_is_active(unsigned long pmcr, int idx)
@@ -485,7 +486,7 @@ armv6pmu_handle_irq(int irq_num,
 {
        unsigned long pmcr = armv6_pmcr_read();
        struct perf_sample_data data;
-       struct cpu_hw_events *cpuc;
+       struct pmu_hw_events *cpuc;
        struct pt_regs *regs;
        int idx;
 
@@ -504,7 +505,7 @@ armv6pmu_handle_irq(int irq_num,
        perf_sample_data_init(&data, 0);
 
        cpuc = &__get_cpu_var(cpu_hw_events);
-       for (idx = 0; idx < armpmu->num_events; ++idx) {
+       for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
                struct perf_event *event = cpuc->events[idx];
                struct hw_perf_event *hwc;
 
@@ -525,7 +526,7 @@ armv6pmu_handle_irq(int irq_num,
                        continue;
 
                if (perf_event_overflow(event, &data, regs))
-                       armpmu->disable(hwc, idx);
+                       cpu_pmu->disable(hwc, idx);
        }
 
        /*
@@ -544,28 +545,30 @@ static void
 armv6pmu_start(void)
 {
        unsigned long flags, val;
+       struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-       raw_spin_lock_irqsave(&pmu_lock, flags);
+       raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = armv6_pmcr_read();
        val |= ARMV6_PMCR_ENABLE;
        armv6_pmcr_write(val);
-       raw_spin_unlock_irqrestore(&pmu_lock, flags);
+       raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void
 armv6pmu_stop(void)
 {
        unsigned long flags, val;
+       struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
-       raw_spin_lock_irqsave(&pmu_lock, flags);
+       raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = armv6_pmcr_read();
        val &= ~ARMV6_PMCR_ENABLE;
        armv6_pmcr_write(val);
-       raw_spin_unlock_irqrestore(&pmu_lock, flags);
+       raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static int
-armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
+armv6pmu_get_event_idx(struct pmu_hw_events *cpuc,
                       struct hw_perf_event *event)
 {
        /* Always place a cycle counter into the cycle counter. */
@@ -595,6 +598,7 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
                       int idx)
 {
        unsigned long val, mask, evt, flags;
+       struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
        if (ARMV6_CYCLE_COUNTER == idx) {
                mask    = ARMV6_PMCR_CCOUNT_IEN;
@@ -615,12 +619,12 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
         * of ETM bus signal assertion cycles. The external reporting should
         * be disabled and so this should never increment.
         */
-       raw_spin_lock_irqsave(&pmu_lock, flags);
+       raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = armv6_pmcr_read();
        val &= ~mask;
        val |= evt;
        armv6_pmcr_write(val);
-       raw_spin_unlock_irqrestore(&pmu_lock, flags);
+       raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 }
 
 static void
@@ -628,6 +632,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
                              int idx)
 {
        unsigned long val, mask, flags, evt = 0;
+       struct pmu_hw_events *events = cpu_pmu->get_hw_events();
 
        if (ARMV6_CYCLE_COUNTER == idx) {
                mask    = ARMV6_PMCR_CCOUNT_IEN;
@@ -644,12 +649,18 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
         * Unlike UP ARMv6, we don't have a way of stopping the counters. We
         * simply disable the interrupt reporting.
         */
-       raw_spin_lock_irqsave(&pmu_lock, flags);
+       raw_spin_lock_irqsave(&events->pmu_lock, flags);
        val = armv6_pmcr_read();
        val &= ~mask;
        val |= evt;
        armv6_pmcr_write(val);
-       raw_spin_unlock_irqrestore(&pmu_lock, flags);
+       raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
+}
+
+static int armv6_map_event(struct perf_event *event)
+{
+       return map_cpu_event(event, &armv6_perf_map,
+                               &armv6_perf_cache_map, 0xFF);
 }
 
 static struct arm_pmu armv6pmu = {
@@ -663,9 +674,7 @@ static struct arm_pmu armv6pmu = {
        .get_event_idx          = armv6pmu_get_event_idx,
        .start                  = armv6pmu_start,
        .stop                   = armv6pmu_stop,
-       .cache_map              = &armv6_perf_cache_map,
-       .event_map              = &armv6_perf_map,
-       .raw_event_mask         = 0xFF,
+       .map_event              = armv6_map_event,
        .num_events             = 3,
        .max_period             = (1LLU << 32) - 1,
 };
@@ -682,6 +691,13 @@ static struct arm_pmu *__init armv6pmu_init(void)
  * disable the interrupt reporting and update the event. When unthrottling we
  * reset the period and enable the interrupt reporting.
  */
+
+static int armv6mpcore_map_event(struct perf_event *event)
+{
+       return map_cpu_event(event, &armv6mpcore_perf_map,
+                               &armv6mpcore_perf_cache_map, 0xFF);
+}
+
 static struct arm_pmu armv6mpcore_pmu = {
        .id                     = ARM_PERF_PMU_ID_V6MP,
        .name                   = "v6mpcore",
@@ -693,9 +709,7 @@ static struct arm_pmu armv6mpcore_pmu = {
        .get_event_idx          = armv6pmu_get_event_idx,
        .start                  = armv6pmu_start,
        .stop                   = armv6pmu_stop,
-       .cache_map              = &armv6mpcore_perf_cache_map,
-       .event_map              = &armv6mpcore_perf_map,
-       .raw_event_mask         = 0xFF,
+       .map_event              = armv6mpcore_map_event,
        .num_events             = 3,
        .max_period             = (1LLU << 32) - 1,
 };