Merge branch 'devel-stable' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git...

[pandora-kernel.git] / arch / arm / common / gic.c

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 016c1ae..a8fc6b2 100644 (file)
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -37,7 +37,7 @@
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
 
-static DEFINE_SPINLOCK(irq_controller_lock);
+static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 
 /* Address of GIC 0 CPU interface */
 void __iomem *gic_cpu_base_addr __read_mostly;
@@ -86,30 +86,30 @@ static void gic_mask_irq(struct irq_data *d)
 {
        u32 mask = 1 << (d->irq % 32);
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
        if (gic_arch_extn.irq_mask)
                gic_arch_extn.irq_mask(d);
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 }
 
 static void gic_unmask_irq(struct irq_data *d)
 {
        u32 mask = 1 << (d->irq % 32);
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
        if (gic_arch_extn.irq_unmask)
                gic_arch_extn.irq_unmask(d);
        writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 }
 
 static void gic_eoi_irq(struct irq_data *d)
 {
        if (gic_arch_extn.irq_eoi) {
-               spin_lock(&irq_controller_lock);
+               raw_spin_lock(&irq_controller_lock);
                gic_arch_extn.irq_eoi(d);
-               spin_unlock(&irq_controller_lock);
+               raw_spin_unlock(&irq_controller_lock);
        }
 
        writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
@@ -133,7 +133,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
        if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
                return -EINVAL;
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
 
        if (gic_arch_extn.irq_set_type)
                gic_arch_extn.irq_set_type(d, type);
@@ -158,7 +158,7 @@ static int gic_set_type(struct irq_data *d, unsigned int type)
        if (enabled)
                writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
 
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 
        return 0;
 }
@@ -186,10 +186,10 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
        mask = 0xff << shift;
        bit = 1 << (cpu_logical_map(cpu) + shift);
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
        val = readl_relaxed(reg) & ~mask;
        writel_relaxed(val | bit, reg);
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 
        return IRQ_SET_MASK_OK;
 }
@@ -219,9 +219,9 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 
        chained_irq_enter(chip, desc);
 
-       spin_lock(&irq_controller_lock);
+       raw_spin_lock(&irq_controller_lock);
        status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
-       spin_unlock(&irq_controller_lock);
+       raw_spin_unlock(&irq_controller_lock);
 
        gic_irq = (status & 0x3ff);
        if (gic_irq == 1023)