Merge tag 'mfd-for-linus-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

[pandora-kernel.git] / arch / arm / boot / dts / rk3288.dtsi

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 910dcad..d771f68 100644 (file)
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -149,8 +149,22 @@
                clock-frequency = <24000000>;
        };
 
+       timer: timer@ff810000 {
+               compatible = "rockchip,rk3288-timer";
+               reg = <0xff810000 0x20>;
+               interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&xin24m>, <&cru PCLK_TIMER>;
+               clock-names = "timer", "pclk";
+       };
+
+       display-subsystem {
+               compatible = "rockchip,display-subsystem";
+               ports = <&vopl_out>, <&vopb_out>;
+       };
+
        sdmmc: dwmmc@ff0c0000 {
                compatible = "rockchip,rk3288-dw-mshc";
+               clock-freq-min-max = <400000 150000000>;
                clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x100>;
@@ -161,6 +175,7 @@
 
        sdio0: dwmmc@ff0d0000 {
                compatible = "rockchip,rk3288-dw-mshc";
+               clock-freq-min-max = <400000 150000000>;
                clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x100>;
@@ -171,6 +186,7 @@
 
        sdio1: dwmmc@ff0e0000 {
                compatible = "rockchip,rk3288-dw-mshc";
+               clock-freq-min-max = <400000 150000000>;
                clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x100>;
@@ -181,6 +197,7 @@
 
        emmc: dwmmc@ff0f0000 {
                compatible = "rockchip,rk3288-dw-mshc";
+               clock-freq-min-max = <400000 150000000>;
                clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
                clock-names = "biu", "ciu";
                fifo-depth = <0x100>;
@@ -518,6 +535,11 @@
                };
        };
 
+       sram@ff720000 {
+               compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
+               reg = <0xff720000 0x1000>;
+       };
+
        pmu: power-management@ff730000 {
                compatible = "rockchip,rk3288-pmu", "syscon";
                reg = <0xff730000 0x100>;
@@ -554,6 +576,7 @@
        wdt: watchdog@ff800000 {
                compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
                reg = <0xff800000 0x100>;
+               clocks = <&cru PCLK_WDT>;
                interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -573,6 +596,28 @@
                status = "disabled";
        };
 
+       vopb: vop@ff930000 {
+               compatible = "rockchip,rk3288-vop";
+               reg = <0xff930000 0x19c>;
+               interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
+               reset-names = "axi", "ahb", "dclk";
+               iommus = <&vopb_mmu>;
+               status = "disabled";
+
+               vopb_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       vopb_out_hdmi: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&hdmi_in_vopb>;
+                       };
+               };
+       };
+
        vopb_mmu: iommu@ff930300 {
                compatible = "rockchip,iommu";
                reg = <0xff930300 0x100>;
@@ -582,6 +627,28 @@
                status = "disabled";
        };
 
+       vopl: vop@ff940000 {
+               compatible = "rockchip,rk3288-vop";
+               reg = <0xff940000 0x19c>;
+               interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
+               clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+               resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
+               reset-names = "axi", "ahb", "dclk";
+               iommus = <&vopl_mmu>;
+               status = "disabled";
+
+               vopl_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       vopl_out_hdmi: endpoint@0 {
+                               reg = <0>;
+                               remote-endpoint = <&hdmi_in_vopl>;
+                       };
+               };
+       };
+
        vopl_mmu: iommu@ff940300 {
                compatible = "rockchip,iommu";
                reg = <0xff940300 0x100>;
@@ -591,6 +658,32 @@
                status = "disabled";
        };
 
+       hdmi: hdmi@ff980000 {
+               compatible = "rockchip,rk3288-dw-hdmi";
+               reg = <0xff980000 0x20000>;
+               reg-io-width = <4>;
+               rockchip,grf = <&grf>;
+               interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
+               clock-names = "iahb", "isfr";
+               status = "disabled";
+
+               ports {
+                       hdmi_in: port {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+                               hdmi_in_vopb: endpoint@0 {
+                                       reg = <0>;
+                                       remote-endpoint = <&vopb_out_hdmi>;
+                               };
+                               hdmi_in_vopl: endpoint@1 {
+                                       reg = <1>;
+                                       remote-endpoint = <&vopl_out_hdmi>;
+                               };
+                       };
+               };
+       };
+
        gic: interrupt-controller@ffc01000 {
                compatible = "arm,gic-400";
                interrupt-controller;
@@ -746,6 +839,24 @@
                        drive-strength = <12>;
                };
 
+               sleep {
+                       global_pwroff: global-pwroff {
+                               rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       ddrio_pwroff: ddrio-pwroff {
+                               rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       ddr0_retention: ddr0-retention {
+                               rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+
+                       ddr1_retention: ddr1-retention {
+                               rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
                i2c0 {
                        i2c0_xfer: i2c0-xfer {
                                rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,