sound/soc/codecs/wm8994.c

   1 /*
   2  * wm8994.c  --  WM8994 ALSA SoC Audio driver
   3  *
   4  * Copyright 2009 Wolfson Microelectronics plc
   5  *
   6  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
   7  *
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/moduleparam.h>
  16 #include <linux/init.h>
  17 #include <linux/delay.h>
  18 #include <linux/pm.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/slab.h>
  24 #include <sound/core.h>
  25 #include <sound/jack.h>
  26 #include <sound/pcm.h>
  27 #include <sound/pcm_params.h>
  28 #include <sound/soc.h>
  29 #include <sound/initval.h>
  30 #include <sound/tlv.h>
  31
  32 #include <linux/mfd/wm8994/core.h>
  33 #include <linux/mfd/wm8994/registers.h>
  34 #include <linux/mfd/wm8994/pdata.h>
  35 #include <linux/mfd/wm8994/gpio.h>
  36
  37 #include "wm8994.h"
  38 #include "wm_hubs.h"
  39
  40 struct fll_config {
  41         int src;
  42         int in;
  43         int out;
  44 };
  45
  46 #define WM8994_NUM_DRC 3
  47 #define WM8994_NUM_EQ  3
  48
  49 static int wm8994_drc_base[] = {
  50         WM8994_AIF1_DRC1_1,
  51         WM8994_AIF1_DRC2_1,
  52         WM8994_AIF2_DRC_1,
  53 };
  54
  55 static int wm8994_retune_mobile_base[] = {
  56         WM8994_AIF1_DAC1_EQ_GAINS_1,
  57         WM8994_AIF1_DAC2_EQ_GAINS_1,
  58         WM8994_AIF2_EQ_GAINS_1,
  59 };
  60
  61 struct wm8994_micdet {
  62         struct snd_soc_jack *jack;
  63         int det;
  64         int shrt;
  65 };
  66
  67 /* codec private data */
  68 struct wm8994_priv {
  69         struct wm_hubs_data hubs;
  70         enum snd_soc_control_type control_type;
  71         void *control_data;
  72         struct snd_soc_codec *codec;
  73         int sysclk[2];
  74         int sysclk_rate[2];
  75         int mclk[2];
  76         int aifclk[2];
  77         struct fll_config fll[2], fll_suspend[2];
  78
  79         int dac_rates[2];
  80         int lrclk_shared[2];
  81
  82         int mbc_ena[3];
  83
  84         /* Platform dependant DRC configuration */
  85         const char **drc_texts;
  86         int drc_cfg[WM8994_NUM_DRC];
  87         struct soc_enum drc_enum;
  88
  89         /* Platform dependant ReTune mobile configuration */
  90         int num_retune_mobile_texts;
  91         const char **retune_mobile_texts;
  92         int retune_mobile_cfg[WM8994_NUM_EQ];
  93         struct soc_enum retune_mobile_enum;
  94
  95         /* Platform dependant MBC configuration */
  96         int mbc_cfg;
  97         const char **mbc_texts;
  98         struct soc_enum mbc_enum;
  99
 100         struct wm8994_micdet micdet[2];
 101
 102         wm8958_micdet_cb jack_cb;
 103         void *jack_cb_data;
 104         bool jack_is_mic;
 105         bool jack_is_video;
 106
 107         int revision;
 108         struct wm8994_pdata *pdata;
 109 };
 110
 111 static int wm8994_readable(unsigned int reg)
 112 {
 113         switch (reg) {
 114         case WM8994_GPIO_1:
 115         case WM8994_GPIO_2:
 116         case WM8994_GPIO_3:
 117         case WM8994_GPIO_4:
 118         case WM8994_GPIO_5:
 119         case WM8994_GPIO_6:
 120         case WM8994_GPIO_7:
 121         case WM8994_GPIO_8:
 122         case WM8994_GPIO_9:
 123         case WM8994_GPIO_10:
 124         case WM8994_GPIO_11:
 125         case WM8994_INTERRUPT_STATUS_1:
 126         case WM8994_INTERRUPT_STATUS_2:
 127         case WM8994_INTERRUPT_RAW_STATUS_2:
 128                 return 1;
 129         default:
 130                 break;
 131         }
 132
 133         if (reg >= WM8994_CACHE_SIZE)
 134                 return 0;
 135         return wm8994_access_masks[reg].readable != 0;
 136 }
 137
 138 static int wm8994_volatile(unsigned int reg)
 139 {
 140         if (reg >= WM8994_CACHE_SIZE)
 141                 return 1;
 142
 143         switch (reg) {
 144         case WM8994_SOFTWARE_RESET:
 145         case WM8994_CHIP_REVISION:
 146         case WM8994_DC_SERVO_1:
 147         case WM8994_DC_SERVO_READBACK:
 148         case WM8994_RATE_STATUS:
 149         case WM8994_LDO_1:
 150         case WM8994_LDO_2:
 151         case WM8958_DSP2_EXECCONTROL:
 152         case WM8958_MIC_DETECT_3:
 153                 return 1;
 154         default:
 155                 return 0;
 156         }
 157 }
 158
 159 static int wm8994_write(struct snd_soc_codec *codec, unsigned int reg,
 160         unsigned int value)
 161 {
 162         int ret;
 163
 164         BUG_ON(reg > WM8994_MAX_REGISTER);
 165
 166         if (!wm8994_volatile(reg)) {
 167                 ret = snd_soc_cache_write(codec, reg, value);
 168                 if (ret != 0)
 169                         dev_err(codec->dev, "Cache write to %x failed: %d\n",
 170                                 reg, ret);
 171         }
 172
 173         return wm8994_reg_write(codec->control_data, reg, value);
 174 }
 175
 176 static unsigned int wm8994_read(struct snd_soc_codec *codec,
 177                                 unsigned int reg)
 178 {
 179         unsigned int val;
 180         int ret;
 181
 182         BUG_ON(reg > WM8994_MAX_REGISTER);
 183
 184         if (!wm8994_volatile(reg) && wm8994_readable(reg) &&
 185             reg < codec->driver->reg_cache_size) {
 186                 ret = snd_soc_cache_read(codec, reg, &val);
 187                 if (ret >= 0)
 188                         return val;
 189                 else
 190                         dev_err(codec->dev, "Cache read from %x failed: %d\n",
 191                                 reg, ret);
 192         }
 193
 194         return wm8994_reg_read(codec->control_data, reg);
 195 }
 196
 197 static int configure_aif_clock(struct snd_soc_codec *codec, int aif)
 198 {
 199         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 200         int rate;
 201         int reg1 = 0;
 202         int offset;
 203
 204         if (aif)
 205                 offset = 4;
 206         else
 207                 offset = 0;
 208
 209         switch (wm8994->sysclk[aif]) {
 210         case WM8994_SYSCLK_MCLK1:
 211                 rate = wm8994->mclk[0];
 212                 break;
 213
 214         case WM8994_SYSCLK_MCLK2:
 215                 reg1 |= 0x8;
 216                 rate = wm8994->mclk[1];
 217                 break;
 218
 219         case WM8994_SYSCLK_FLL1:
 220                 reg1 |= 0x10;
 221                 rate = wm8994->fll[0].out;
 222                 break;
 223
 224         case WM8994_SYSCLK_FLL2:
 225                 reg1 |= 0x18;
 226                 rate = wm8994->fll[1].out;
 227                 break;
 228
 229         default:
 230                 return -EINVAL;
 231         }
 232
 233         if (rate >= 13500000) {
 234                 rate /= 2;
 235                 reg1 |= WM8994_AIF1CLK_DIV;
 236
 237                 dev_dbg(codec->dev, "Dividing AIF%d clock to %dHz\n",
 238                         aif + 1, rate);
 239         }
 240
 241         if (rate && rate < 3000000)
 242                 dev_warn(codec->dev, "AIF%dCLK is %dHz, should be >=3MHz for optimal performance\n",
 243                          aif + 1, rate);
 244
 245         wm8994->aifclk[aif] = rate;
 246
 247         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1 + offset,
 248                             WM8994_AIF1CLK_SRC_MASK | WM8994_AIF1CLK_DIV,
 249                             reg1);
 250
 251         return 0;
 252 }
 253
 254 static int configure_clock(struct snd_soc_codec *codec)
 255 {
 256         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 257         int old, new;
 258
 259         /* Bring up the AIF clocks first */
 260         configure_aif_clock(codec, 0);
 261         configure_aif_clock(codec, 1);
 262
 263         /* Then switch CLK_SYS over to the higher of them; a change
 264          * can only happen as a result of a clocking change which can
 265          * only be made outside of DAPM so we can safely redo the
 266          * clocking.
 267          */
 268
 269         /* If they're equal it doesn't matter which is used */
 270         if (wm8994->aifclk[0] == wm8994->aifclk[1])
 271                 return 0;
 272
 273         if (wm8994->aifclk[0] < wm8994->aifclk[1])
 274                 new = WM8994_SYSCLK_SRC;
 275         else
 276                 new = 0;
 277
 278         old = snd_soc_read(codec, WM8994_CLOCKING_1) & WM8994_SYSCLK_SRC;
 279
 280         /* If there's no change then we're done. */
 281         if (old == new)
 282                 return 0;
 283
 284         snd_soc_update_bits(codec, WM8994_CLOCKING_1, WM8994_SYSCLK_SRC, new);
 285
 286         snd_soc_dapm_sync(&codec->dapm);
 287
 288         return 0;
 289 }
 290
 291 static int check_clk_sys(struct snd_soc_dapm_widget *source,
 292                          struct snd_soc_dapm_widget *sink)
 293 {
 294         int reg = snd_soc_read(source->codec, WM8994_CLOCKING_1);
 295         const char *clk;
 296
 297         /* Check what we're currently using for CLK_SYS */
 298         if (reg & WM8994_SYSCLK_SRC)
 299                 clk = "AIF2CLK";
 300         else
 301                 clk = "AIF1CLK";
 302
 303         return strcmp(source->name, clk) == 0;
 304 }
 305
 306 static const char *sidetone_hpf_text[] = {
 307         "2.7kHz", "1.35kHz", "675Hz", "370Hz", "180Hz", "90Hz", "45Hz"
 308 };
 309
 310 static const struct soc_enum sidetone_hpf =
 311         SOC_ENUM_SINGLE(WM8994_SIDETONE, 7, 7, sidetone_hpf_text);
 312
 313 static const DECLARE_TLV_DB_SCALE(aif_tlv, 0, 600, 0);
 314 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
 315 static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
 316 static const DECLARE_TLV_DB_SCALE(wm8994_3d_tlv, -1600, 183, 0);
 317 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
 318
 319 #define WM8994_DRC_SWITCH(xname, reg, shift) \
 320 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 321         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
 322         .put = wm8994_put_drc_sw, \
 323         .private_value =  SOC_SINGLE_VALUE(reg, shift, 1, 0) }
 324
 325 static int wm8994_put_drc_sw(struct snd_kcontrol *kcontrol,
 326                              struct snd_ctl_elem_value *ucontrol)
 327 {
 328         struct soc_mixer_control *mc =
 329                 (struct soc_mixer_control *)kcontrol->private_value;
 330         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 331         int mask, ret;
 332
 333         /* Can't enable both ADC and DAC paths simultaneously */
 334         if (mc->shift == WM8994_AIF1DAC1_DRC_ENA_SHIFT)
 335                 mask = WM8994_AIF1ADC1L_DRC_ENA_MASK |
 336                         WM8994_AIF1ADC1R_DRC_ENA_MASK;
 337         else
 338                 mask = WM8994_AIF1DAC1_DRC_ENA_MASK;
 339
 340         ret = snd_soc_read(codec, mc->reg);
 341         if (ret < 0)
 342                 return ret;
 343         if (ret & mask)
 344                 return -EINVAL;
 345
 346         return snd_soc_put_volsw(kcontrol, ucontrol);
 347 }
 348
 349 static void wm8994_set_drc(struct snd_soc_codec *codec, int drc)
 350 {
 351         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 352         struct wm8994_pdata *pdata = wm8994->pdata;
 353         int base = wm8994_drc_base[drc];
 354         int cfg = wm8994->drc_cfg[drc];
 355         int save, i;
 356
 357         /* Save any enables; the configuration should clear them. */
 358         save = snd_soc_read(codec, base);
 359         save &= WM8994_AIF1DAC1_DRC_ENA | WM8994_AIF1ADC1L_DRC_ENA |
 360                 WM8994_AIF1ADC1R_DRC_ENA;
 361
 362         for (i = 0; i < WM8994_DRC_REGS; i++)
 363                 snd_soc_update_bits(codec, base + i, 0xffff,
 364                                     pdata->drc_cfgs[cfg].regs[i]);
 365
 366         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_DRC_ENA |
 367                              WM8994_AIF1ADC1L_DRC_ENA |
 368                              WM8994_AIF1ADC1R_DRC_ENA, save);
 369 }
 370
 371 /* Icky as hell but saves code duplication */
 372 static int wm8994_get_drc(const char *name)
 373 {
 374         if (strcmp(name, "AIF1DRC1 Mode") == 0)
 375                 return 0;
 376         if (strcmp(name, "AIF1DRC2 Mode") == 0)
 377                 return 1;
 378         if (strcmp(name, "AIF2DRC Mode") == 0)
 379                 return 2;
 380         return -EINVAL;
 381 }
 382
 383 static int wm8994_put_drc_enum(struct snd_kcontrol *kcontrol,
 384                                struct snd_ctl_elem_value *ucontrol)
 385 {
 386         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 387         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 388         struct wm8994_pdata *pdata = wm8994->pdata;
 389         int drc = wm8994_get_drc(kcontrol->id.name);
 390         int value = ucontrol->value.integer.value[0];
 391
 392         if (drc < 0)
 393                 return drc;
 394
 395         if (value >= pdata->num_drc_cfgs)
 396                 return -EINVAL;
 397
 398         wm8994->drc_cfg[drc] = value;
 399
 400         wm8994_set_drc(codec, drc);
 401
 402         return 0;
 403 }
 404
 405 static int wm8994_get_drc_enum(struct snd_kcontrol *kcontrol,
 406                                struct snd_ctl_elem_value *ucontrol)
 407 {
 408         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 409         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 410         int drc = wm8994_get_drc(kcontrol->id.name);
 411
 412         ucontrol->value.enumerated.item[0] = wm8994->drc_cfg[drc];
 413
 414         return 0;
 415 }
 416
 417 static void wm8994_set_retune_mobile(struct snd_soc_codec *codec, int block)
 418 {
 419         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 420         struct wm8994_pdata *pdata = wm8994->pdata;
 421         int base = wm8994_retune_mobile_base[block];
 422         int iface, best, best_val, save, i, cfg;
 423
 424         if (!pdata || !wm8994->num_retune_mobile_texts)
 425                 return;
 426
 427         switch (block) {
 428         case 0:
 429         case 1:
 430                 iface = 0;
 431                 break;
 432         case 2:
 433                 iface = 1;
 434                 break;
 435         default:
 436                 return;
 437         }
 438
 439         /* Find the version of the currently selected configuration
 440          * with the nearest sample rate. */
 441         cfg = wm8994->retune_mobile_cfg[block];
 442         best = 0;
 443         best_val = INT_MAX;
 444         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
 445                 if (strcmp(pdata->retune_mobile_cfgs[i].name,
 446                            wm8994->retune_mobile_texts[cfg]) == 0 &&
 447                     abs(pdata->retune_mobile_cfgs[i].rate
 448                         - wm8994->dac_rates[iface]) < best_val) {
 449                         best = i;
 450                         best_val = abs(pdata->retune_mobile_cfgs[i].rate
 451                                        - wm8994->dac_rates[iface]);
 452                 }
 453         }
 454
 455         dev_dbg(codec->dev, "ReTune Mobile %d %s/%dHz for %dHz sample rate\n",
 456                 block,
 457                 pdata->retune_mobile_cfgs[best].name,
 458                 pdata->retune_mobile_cfgs[best].rate,
 459                 wm8994->dac_rates[iface]);
 460
 461         /* The EQ will be disabled while reconfiguring it, remember the
 462          * current configuration.
 463          */
 464         save = snd_soc_read(codec, base);
 465         save &= WM8994_AIF1DAC1_EQ_ENA;
 466
 467         for (i = 0; i < WM8994_EQ_REGS; i++)
 468                 snd_soc_update_bits(codec, base + i, 0xffff,
 469                                 pdata->retune_mobile_cfgs[best].regs[i]);
 470
 471         snd_soc_update_bits(codec, base, WM8994_AIF1DAC1_EQ_ENA, save);
 472 }
 473
 474 /* Icky as hell but saves code duplication */
 475 static int wm8994_get_retune_mobile_block(const char *name)
 476 {
 477         if (strcmp(name, "AIF1.1 EQ Mode") == 0)
 478                 return 0;
 479         if (strcmp(name, "AIF1.2 EQ Mode") == 0)
 480                 return 1;
 481         if (strcmp(name, "AIF2 EQ Mode") == 0)
 482                 return 2;
 483         return -EINVAL;
 484 }
 485
 486 static int wm8994_put_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 487                                          struct snd_ctl_elem_value *ucontrol)
 488 {
 489         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 490         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 491         struct wm8994_pdata *pdata = wm8994->pdata;
 492         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 493         int value = ucontrol->value.integer.value[0];
 494
 495         if (block < 0)
 496                 return block;
 497
 498         if (value >= pdata->num_retune_mobile_cfgs)
 499                 return -EINVAL;
 500
 501         wm8994->retune_mobile_cfg[block] = value;
 502
 503         wm8994_set_retune_mobile(codec, block);
 504
 505         return 0;
 506 }
 507
 508 static int wm8994_get_retune_mobile_enum(struct snd_kcontrol *kcontrol,
 509                                          struct snd_ctl_elem_value *ucontrol)
 510 {
 511         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 512         struct wm8994_priv *wm8994 =snd_soc_codec_get_drvdata(codec);
 513         int block = wm8994_get_retune_mobile_block(kcontrol->id.name);
 514
 515         ucontrol->value.enumerated.item[0] = wm8994->retune_mobile_cfg[block];
 516
 517         return 0;
 518 }
 519
 520 static const char *aif_chan_src_text[] = {
 521         "Left", "Right"
 522 };
 523
 524 static const struct soc_enum aif1adcl_src =
 525         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 15, 2, aif_chan_src_text);
 526
 527 static const struct soc_enum aif1adcr_src =
 528         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_1, 14, 2, aif_chan_src_text);
 529
 530 static const struct soc_enum aif2adcl_src =
 531         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 15, 2, aif_chan_src_text);
 532
 533 static const struct soc_enum aif2adcr_src =
 534         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_1, 14, 2, aif_chan_src_text);
 535
 536 static const struct soc_enum aif1dacl_src =
 537         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 15, 2, aif_chan_src_text);
 538
 539 static const struct soc_enum aif1dacr_src =
 540         SOC_ENUM_SINGLE(WM8994_AIF1_CONTROL_2, 14, 2, aif_chan_src_text);
 541
 542 static const struct soc_enum aif2dacl_src =
 543         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 15, 2, aif_chan_src_text);
 544
 545 static const struct soc_enum aif2dacr_src =
 546         SOC_ENUM_SINGLE(WM8994_AIF2_CONTROL_2, 14, 2, aif_chan_src_text);
 547
 548 static void wm8958_mbc_apply(struct snd_soc_codec *codec, int mbc, int start)
 549 {
 550         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 551         struct wm8994_pdata *pdata = wm8994->pdata;
 552         int pwr_reg = snd_soc_read(codec, WM8994_POWER_MANAGEMENT_5);
 553         int ena, reg, aif, i;
 554
 555         switch (mbc) {
 556         case 0:
 557                 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA);
 558                 aif = 0;
 559                 break;
 560         case 1:
 561                 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA);
 562                 aif = 0;
 563                 break;
 564         case 2:
 565                 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA);
 566                 aif = 1;
 567                 break;
 568         default:
 569                 BUG();
 570                 return;
 571         }
 572
 573         /* We can only enable the MBC if the AIF is enabled and we
 574          * want it to be enabled. */
 575         ena = pwr_reg && wm8994->mbc_ena[mbc];
 576
 577         reg = snd_soc_read(codec, WM8958_DSP2_PROGRAM);
 578
 579         dev_dbg(codec->dev, "MBC %d startup: %d, power: %x, DSP: %x\n",
 580                 mbc, start, pwr_reg, reg);
 581
 582         if (start && ena) {
 583                 /* If the DSP is already running then noop */
 584                 if (reg & WM8958_DSP2_ENA)
 585                         return;
 586
 587                 /* Switch the clock over to the appropriate AIF */
 588                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 589                                     WM8958_DSP2CLK_SRC | WM8958_DSP2CLK_ENA,
 590                                     aif << WM8958_DSP2CLK_SRC_SHIFT |
 591                                     WM8958_DSP2CLK_ENA);
 592
 593                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 594                                     WM8958_DSP2_ENA, WM8958_DSP2_ENA);
 595
 596                 /* If we've got user supplied MBC settings use them */
 597                 if (pdata && pdata->num_mbc_cfgs) {
 598                         struct wm8958_mbc_cfg *cfg
 599                                 = &pdata->mbc_cfgs[wm8994->mbc_cfg];
 600
 601                         for (i = 0; i < ARRAY_SIZE(cfg->coeff_regs); i++)
 602                                 snd_soc_write(codec, i + WM8958_MBC_BAND_1_K_1,
 603                                               cfg->coeff_regs[i]);
 604
 605                         for (i = 0; i < ARRAY_SIZE(cfg->cutoff_regs); i++)
 606                                 snd_soc_write(codec,
 607                                               i + WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1,
 608                                               cfg->cutoff_regs[i]);
 609                 }
 610
 611                 /* Run the DSP */
 612                 snd_soc_write(codec, WM8958_DSP2_EXECCONTROL,
 613                               WM8958_DSP2_RUNR);
 614
 615                 /* And we're off! */
 616                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 617                                     WM8958_MBC_ENA | WM8958_MBC_SEL_MASK,
 618                                     mbc << WM8958_MBC_SEL_SHIFT |
 619                                     WM8958_MBC_ENA);
 620         } else {
 621                 /* If the DSP is already stopped then noop */
 622                 if (!(reg & WM8958_DSP2_ENA))
 623                         return;
 624
 625                 snd_soc_update_bits(codec, WM8958_DSP2_CONFIG,
 626                                     WM8958_MBC_ENA, 0);
 627                 snd_soc_update_bits(codec, WM8958_DSP2_PROGRAM,
 628                                     WM8958_DSP2_ENA, 0);
 629                 snd_soc_update_bits(codec, WM8994_CLOCKING_1,
 630                                     WM8958_DSP2CLK_ENA, 0);
 631         }
 632 }
 633
 634 static int wm8958_aif_ev(struct snd_soc_dapm_widget *w,
 635                     struct snd_kcontrol *kcontrol, int event)
 636 {
 637         struct snd_soc_codec *codec = w->codec;
 638         int mbc;
 639
 640         switch (w->shift) {
 641         case 13:
 642         case 12:
 643                 mbc = 2;
 644                 break;
 645         case 11:
 646         case 10:
 647                 mbc = 1;
 648                 break;
 649         case 9:
 650         case 8:
 651                 mbc = 0;
 652                 break;
 653         default:
 654                 BUG();
 655                 return -EINVAL;
 656         }
 657
 658         switch (event) {
 659         case SND_SOC_DAPM_POST_PMU:
 660                 wm8958_mbc_apply(codec, mbc, 1);
 661                 break;
 662         case SND_SOC_DAPM_POST_PMD:
 663                 wm8958_mbc_apply(codec, mbc, 0);
 664                 break;
 665         }
 666
 667         return 0;
 668 }
 669
 670 static int wm8958_put_mbc_enum(struct snd_kcontrol *kcontrol,
 671                                struct snd_ctl_elem_value *ucontrol)
 672 {
 673         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 674         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 675         struct wm8994_pdata *pdata = wm8994->pdata;
 676         int value = ucontrol->value.integer.value[0];
 677         int reg;
 678
 679         /* Don't allow on the fly reconfiguration */
 680         reg = snd_soc_read(codec, WM8994_CLOCKING_1);
 681         if (reg < 0 || reg & WM8958_DSP2CLK_ENA)
 682                 return -EBUSY;
 683
 684         if (value >= pdata->num_mbc_cfgs)
 685                 return -EINVAL;
 686
 687         wm8994->mbc_cfg = value;
 688
 689         return 0;
 690 }
 691
 692 static int wm8958_get_mbc_enum(struct snd_kcontrol *kcontrol,
 693                                struct snd_ctl_elem_value *ucontrol)
 694 {
 695         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 696         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 697
 698         ucontrol->value.enumerated.item[0] = wm8994->mbc_cfg;
 699
 700         return 0;
 701 }
 702
 703 static int wm8958_mbc_info(struct snd_kcontrol *kcontrol,
 704                            struct snd_ctl_elem_info *uinfo)
 705 {
 706         uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
 707         uinfo->count = 1;
 708         uinfo->value.integer.min = 0;
 709         uinfo->value.integer.max = 1;
 710         return 0;
 711 }
 712
 713 static int wm8958_mbc_get(struct snd_kcontrol *kcontrol,
 714                           struct snd_ctl_elem_value *ucontrol)
 715 {
 716         int mbc = kcontrol->private_value;
 717         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 718         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 719
 720         ucontrol->value.integer.value[0] = wm8994->mbc_ena[mbc];
 721
 722         return 0;
 723 }
 724
 725 static int wm8958_mbc_put(struct snd_kcontrol *kcontrol,
 726                           struct snd_ctl_elem_value *ucontrol)
 727 {
 728         int mbc = kcontrol->private_value;
 729         int i;
 730         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 731         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 732
 733         if (ucontrol->value.integer.value[0] > 1)
 734                 return -EINVAL;
 735
 736         for (i = 0; i < ARRAY_SIZE(wm8994->mbc_ena); i++) {
 737                 if (mbc != i && wm8994->mbc_ena[i]) {
 738                         dev_dbg(codec->dev, "MBC %d active already\n", mbc);
 739                         return -EBUSY;
 740                 }
 741         }
 742
 743         wm8994->mbc_ena[mbc] = ucontrol->value.integer.value[0];
 744
 745         wm8958_mbc_apply(codec, mbc, wm8994->mbc_ena[mbc]);
 746
 747         return 0;
 748 }
 749
 750 #define WM8958_MBC_SWITCH(xname, xval) {\
 751         .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 752         .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,\
 753         .info = wm8958_mbc_info, \
 754         .get = wm8958_mbc_get, .put = wm8958_mbc_put, \
 755         .private_value = xval }
 756
 757 static const struct snd_kcontrol_new wm8994_snd_controls[] = {
 758 SOC_DOUBLE_R_TLV("AIF1ADC1 Volume", WM8994_AIF1_ADC1_LEFT_VOLUME,
 759                  WM8994_AIF1_ADC1_RIGHT_VOLUME,
 760                  1, 119, 0, digital_tlv),
 761 SOC_DOUBLE_R_TLV("AIF1ADC2 Volume", WM8994_AIF1_ADC2_LEFT_VOLUME,
 762                  WM8994_AIF1_ADC2_RIGHT_VOLUME,
 763                  1, 119, 0, digital_tlv),
 764 SOC_DOUBLE_R_TLV("AIF2ADC Volume", WM8994_AIF2_ADC_LEFT_VOLUME,
 765                  WM8994_AIF2_ADC_RIGHT_VOLUME,
 766                  1, 119, 0, digital_tlv),
 767
 768 SOC_ENUM("AIF1ADCL Source", aif1adcl_src),
 769 SOC_ENUM("AIF1ADCR Source", aif1adcr_src),
 770 SOC_ENUM("AIF2ADCL Source", aif1adcl_src),
 771 SOC_ENUM("AIF2ADCR Source", aif1adcr_src),
 772
 773 SOC_ENUM("AIF1DACL Source", aif1dacl_src),
 774 SOC_ENUM("AIF1DACR Source", aif1dacr_src),
 775 SOC_ENUM("AIF2DACL Source", aif1dacl_src),
 776 SOC_ENUM("AIF2DACR Source", aif1dacr_src),
 777
 778 SOC_DOUBLE_R_TLV("AIF1DAC1 Volume", WM8994_AIF1_DAC1_LEFT_VOLUME,
 779                  WM8994_AIF1_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 780 SOC_DOUBLE_R_TLV("AIF1DAC2 Volume", WM8994_AIF1_DAC2_LEFT_VOLUME,
 781                  WM8994_AIF1_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 782 SOC_DOUBLE_R_TLV("AIF2DAC Volume", WM8994_AIF2_DAC_LEFT_VOLUME,
 783                  WM8994_AIF2_DAC_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 784
 785 SOC_SINGLE_TLV("AIF1 Boost Volume", WM8994_AIF1_CONTROL_2, 10, 3, 0, aif_tlv),
 786 SOC_SINGLE_TLV("AIF2 Boost Volume", WM8994_AIF2_CONTROL_2, 10, 3, 0, aif_tlv),
 787
 788 SOC_SINGLE("AIF1DAC1 EQ Switch", WM8994_AIF1_DAC1_EQ_GAINS_1, 0, 1, 0),
 789 SOC_SINGLE("AIF1DAC2 EQ Switch", WM8994_AIF1_DAC2_EQ_GAINS_1, 0, 1, 0),
 790 SOC_SINGLE("AIF2 EQ Switch", WM8994_AIF2_EQ_GAINS_1, 0, 1, 0),
 791
 792 WM8994_DRC_SWITCH("AIF1DAC1 DRC Switch", WM8994_AIF1_DRC1_1, 2),
 793 WM8994_DRC_SWITCH("AIF1ADC1L DRC Switch", WM8994_AIF1_DRC1_1, 1),
 794 WM8994_DRC_SWITCH("AIF1ADC1R DRC Switch", WM8994_AIF1_DRC1_1, 0),
 795
 796 WM8994_DRC_SWITCH("AIF1DAC2 DRC Switch", WM8994_AIF1_DRC2_1, 2),
 797 WM8994_DRC_SWITCH("AIF1ADC2L DRC Switch", WM8994_AIF1_DRC2_1, 1),
 798 WM8994_DRC_SWITCH("AIF1ADC2R DRC Switch", WM8994_AIF1_DRC2_1, 0),
 799
 800 WM8994_DRC_SWITCH("AIF2DAC DRC Switch", WM8994_AIF2_DRC_1, 2),
 801 WM8994_DRC_SWITCH("AIF2ADCL DRC Switch", WM8994_AIF2_DRC_1, 1),
 802 WM8994_DRC_SWITCH("AIF2ADCR DRC Switch", WM8994_AIF2_DRC_1, 0),
 803
 804 SOC_SINGLE_TLV("DAC1 Right Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 805                5, 12, 0, st_tlv),
 806 SOC_SINGLE_TLV("DAC1 Left Sidetone Volume", WM8994_DAC1_MIXER_VOLUMES,
 807                0, 12, 0, st_tlv),
 808 SOC_SINGLE_TLV("DAC2 Right Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 809                5, 12, 0, st_tlv),
 810 SOC_SINGLE_TLV("DAC2 Left Sidetone Volume", WM8994_DAC2_MIXER_VOLUMES,
 811                0, 12, 0, st_tlv),
 812 SOC_ENUM("Sidetone HPF Mux", sidetone_hpf),
 813 SOC_SINGLE("Sidetone HPF Switch", WM8994_SIDETONE, 6, 1, 0),
 814
 815 SOC_DOUBLE_R_TLV("DAC1 Volume", WM8994_DAC1_LEFT_VOLUME,
 816                  WM8994_DAC1_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 817 SOC_DOUBLE_R("DAC1 Switch", WM8994_DAC1_LEFT_VOLUME,
 818              WM8994_DAC1_RIGHT_VOLUME, 9, 1, 1),
 819
 820 SOC_DOUBLE_R_TLV("DAC2 Volume", WM8994_DAC2_LEFT_VOLUME,
 821                  WM8994_DAC2_RIGHT_VOLUME, 1, 96, 0, digital_tlv),
 822 SOC_DOUBLE_R("DAC2 Switch", WM8994_DAC2_LEFT_VOLUME,
 823              WM8994_DAC2_RIGHT_VOLUME, 9, 1, 1),
 824
 825 SOC_SINGLE_TLV("SPKL DAC2 Volume", WM8994_SPKMIXL_ATTENUATION,
 826                6, 1, 1, wm_hubs_spkmix_tlv),
 827 SOC_SINGLE_TLV("SPKL DAC1 Volume", WM8994_SPKMIXL_ATTENUATION,
 828                2, 1, 1, wm_hubs_spkmix_tlv),
 829
 830 SOC_SINGLE_TLV("SPKR DAC2 Volume", WM8994_SPKMIXR_ATTENUATION,
 831                6, 1, 1, wm_hubs_spkmix_tlv),
 832 SOC_SINGLE_TLV("SPKR DAC1 Volume", WM8994_SPKMIXR_ATTENUATION,
 833                2, 1, 1, wm_hubs_spkmix_tlv),
 834
 835 SOC_SINGLE_TLV("AIF1DAC1 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 836                10, 15, 0, wm8994_3d_tlv),
 837 SOC_SINGLE("AIF1DAC1 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 838            8, 1, 0),
 839 SOC_SINGLE_TLV("AIF1DAC2 3D Stereo Volume", WM8994_AIF1_DAC2_FILTERS_2,
 840                10, 15, 0, wm8994_3d_tlv),
 841 SOC_SINGLE("AIF1DAC2 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 842            8, 1, 0),
 843 SOC_SINGLE_TLV("AIF2DAC 3D Stereo Volume", WM8994_AIF1_DAC1_FILTERS_2,
 844                10, 15, 0, wm8994_3d_tlv),
 845 SOC_SINGLE("AIF2DAC 3D Stereo Switch", WM8994_AIF1_DAC2_FILTERS_2,
 846            8, 1, 0),
 847 };
 848
 849 static const struct snd_kcontrol_new wm8994_eq_controls[] = {
 850 SOC_SINGLE_TLV("AIF1DAC1 EQ1 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 11, 31, 0,
 851                eq_tlv),
 852 SOC_SINGLE_TLV("AIF1DAC1 EQ2 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 6, 31, 0,
 853                eq_tlv),
 854 SOC_SINGLE_TLV("AIF1DAC1 EQ3 Volume", WM8994_AIF1_DAC1_EQ_GAINS_1, 1, 31, 0,
 855                eq_tlv),
 856 SOC_SINGLE_TLV("AIF1DAC1 EQ4 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 11, 31, 0,
 857                eq_tlv),
 858 SOC_SINGLE_TLV("AIF1DAC1 EQ5 Volume", WM8994_AIF1_DAC1_EQ_GAINS_2, 6, 31, 0,
 859                eq_tlv),
 860
 861 SOC_SINGLE_TLV("AIF1DAC2 EQ1 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 11, 31, 0,
 862                eq_tlv),
 863 SOC_SINGLE_TLV("AIF1DAC2 EQ2 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 6, 31, 0,
 864                eq_tlv),
 865 SOC_SINGLE_TLV("AIF1DAC2 EQ3 Volume", WM8994_AIF1_DAC2_EQ_GAINS_1, 1, 31, 0,
 866                eq_tlv),
 867 SOC_SINGLE_TLV("AIF1DAC2 EQ4 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 11, 31, 0,
 868                eq_tlv),
 869 SOC_SINGLE_TLV("AIF1DAC2 EQ5 Volume", WM8994_AIF1_DAC2_EQ_GAINS_2, 6, 31, 0,
 870                eq_tlv),
 871
 872 SOC_SINGLE_TLV("AIF2 EQ1 Volume", WM8994_AIF2_EQ_GAINS_1, 11, 31, 0,
 873                eq_tlv),
 874 SOC_SINGLE_TLV("AIF2 EQ2 Volume", WM8994_AIF2_EQ_GAINS_1, 6, 31, 0,
 875                eq_tlv),
 876 SOC_SINGLE_TLV("AIF2 EQ3 Volume", WM8994_AIF2_EQ_GAINS_1, 1, 31, 0,
 877                eq_tlv),
 878 SOC_SINGLE_TLV("AIF2 EQ4 Volume", WM8994_AIF2_EQ_GAINS_2, 11, 31, 0,
 879                eq_tlv),
 880 SOC_SINGLE_TLV("AIF2 EQ5 Volume", WM8994_AIF2_EQ_GAINS_2, 6, 31, 0,
 881                eq_tlv),
 882 };
 883
 884 static const struct snd_kcontrol_new wm8958_snd_controls[] = {
 885 SOC_SINGLE_TLV("AIF3 Boost Volume", WM8958_AIF3_CONTROL_2, 10, 3, 0, aif_tlv),
 886 WM8958_MBC_SWITCH("AIF1DAC1 MBC Switch", 0),
 887 WM8958_MBC_SWITCH("AIF1DAC2 MBC Switch", 1),
 888 WM8958_MBC_SWITCH("AIF2DAC MBC Switch", 2),
 889 };
 890
 891 static int clk_sys_event(struct snd_soc_dapm_widget *w,
 892                          struct snd_kcontrol *kcontrol, int event)
 893 {
 894         struct snd_soc_codec *codec = w->codec;
 895
 896         switch (event) {
 897         case SND_SOC_DAPM_PRE_PMU:
 898                 return configure_clock(codec);
 899
 900         case SND_SOC_DAPM_POST_PMD:
 901                 configure_clock(codec);
 902                 break;
 903         }
 904
 905         return 0;
 906 }
 907
 908 static void wm8994_update_class_w(struct snd_soc_codec *codec)
 909 {
 910         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
 911         int enable = 1;
 912         int source = 0;  /* GCC flow analysis can't track enable */
 913         int reg, reg_r;
 914
 915         /* Only support direct DAC->headphone paths */
 916         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_1);
 917         if (!(reg & WM8994_DAC1L_TO_HPOUT1L)) {
 918                 dev_vdbg(codec->dev, "HPL connected to output mixer\n");
 919                 enable = 0;
 920         }
 921
 922         reg = snd_soc_read(codec, WM8994_OUTPUT_MIXER_2);
 923         if (!(reg & WM8994_DAC1R_TO_HPOUT1R)) {
 924                 dev_vdbg(codec->dev, "HPR connected to output mixer\n");
 925                 enable = 0;
 926         }
 927
 928         /* We also need the same setting for L/R and only one path */
 929         reg = snd_soc_read(codec, WM8994_DAC1_LEFT_MIXER_ROUTING);
 930         switch (reg) {
 931         case WM8994_AIF2DACL_TO_DAC1L:
 932                 dev_vdbg(codec->dev, "Class W source AIF2DAC\n");
 933                 source = 2 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 934                 break;
 935         case WM8994_AIF1DAC2L_TO_DAC1L:
 936                 dev_vdbg(codec->dev, "Class W source AIF1DAC2\n");
 937                 source = 1 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 938                 break;
 939         case WM8994_AIF1DAC1L_TO_DAC1L:
 940                 dev_vdbg(codec->dev, "Class W source AIF1DAC1\n");
 941                 source = 0 << WM8994_CP_DYN_SRC_SEL_SHIFT;
 942                 break;
 943         default:
 944                 dev_vdbg(codec->dev, "DAC mixer setting: %x\n", reg);
 945                 enable = 0;
 946                 break;
 947         }
 948
 949         reg_r = snd_soc_read(codec, WM8994_DAC1_RIGHT_MIXER_ROUTING);
 950         if (reg_r != reg) {
 951                 dev_vdbg(codec->dev, "Left and right DAC mixers different\n");
 952                 enable = 0;
 953         }
 954
 955         if (enable) {
 956                 dev_dbg(codec->dev, "Class W enabled\n");
 957                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 958                                     WM8994_CP_DYN_PWR |
 959                                     WM8994_CP_DYN_SRC_SEL_MASK,
 960                                     source | WM8994_CP_DYN_PWR);
 961                 wm8994->hubs.class_w = true;
 962
 963         } else {
 964                 dev_dbg(codec->dev, "Class W disabled\n");
 965                 snd_soc_update_bits(codec, WM8994_CLASS_W_1,
 966                                     WM8994_CP_DYN_PWR, 0);
 967                 wm8994->hubs.class_w = false;
 968         }
 969 }
 970
 971 static const char *hp_mux_text[] = {
 972         "Mixer",
 973         "DAC",
 974 };
 975
 976 #define WM8994_HP_ENUM(xname, xenum) \
 977 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
 978         .info = snd_soc_info_enum_double, \
 979         .get = snd_soc_dapm_get_enum_double, \
 980         .put = wm8994_put_hp_enum, \
 981         .private_value = (unsigned long)&xenum }
 982
 983 static int wm8994_put_hp_enum(struct snd_kcontrol *kcontrol,
 984                               struct snd_ctl_elem_value *ucontrol)
 985 {
 986         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
 987         struct snd_soc_codec *codec = w->codec;
 988         int ret;
 989
 990         ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
 991
 992         wm8994_update_class_w(codec);
 993
 994         return ret;
 995 }
 996
 997 static const struct soc_enum hpl_enum =
 998         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_1, 8, 2, hp_mux_text);
 999
1000 static const struct snd_kcontrol_new hpl_mux =
1001         WM8994_HP_ENUM("Left Headphone Mux", hpl_enum);
1002
1003 static const struct soc_enum hpr_enum =
1004         SOC_ENUM_SINGLE(WM8994_OUTPUT_MIXER_2, 8, 2, hp_mux_text);
1005
1006 static const struct snd_kcontrol_new hpr_mux =
1007         WM8994_HP_ENUM("Right Headphone Mux", hpr_enum);
1008
1009 static const char *adc_mux_text[] = {
1010         "ADC",
1011         "DMIC",
1012 };
1013
1014 static const struct soc_enum adc_enum =
1015         SOC_ENUM_SINGLE(0, 0, 2, adc_mux_text);
1016
1017 static const struct snd_kcontrol_new adcl_mux =
1018         SOC_DAPM_ENUM_VIRT("ADCL Mux", adc_enum);
1019
1020 static const struct snd_kcontrol_new adcr_mux =
1021         SOC_DAPM_ENUM_VIRT("ADCR Mux", adc_enum);
1022
1023 static const struct snd_kcontrol_new left_speaker_mixer[] = {
1024 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 9, 1, 0),
1025 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 7, 1, 0),
1026 SOC_DAPM_SINGLE("IN1LP Switch", WM8994_SPEAKER_MIXER, 5, 1, 0),
1027 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 3, 1, 0),
1028 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 1, 1, 0),
1029 };
1030
1031 static const struct snd_kcontrol_new right_speaker_mixer[] = {
1032 SOC_DAPM_SINGLE("DAC2 Switch", WM8994_SPEAKER_MIXER, 8, 1, 0),
1033 SOC_DAPM_SINGLE("Input Switch", WM8994_SPEAKER_MIXER, 6, 1, 0),
1034 SOC_DAPM_SINGLE("IN1RP Switch", WM8994_SPEAKER_MIXER, 4, 1, 0),
1035 SOC_DAPM_SINGLE("Output Switch", WM8994_SPEAKER_MIXER, 2, 1, 0),
1036 SOC_DAPM_SINGLE("DAC1 Switch", WM8994_SPEAKER_MIXER, 0, 1, 0),
1037 };
1038
1039 /* Debugging; dump chip status after DAPM transitions */
1040 static int post_ev(struct snd_soc_dapm_widget *w,
1041             struct snd_kcontrol *kcontrol, int event)
1042 {
1043         struct snd_soc_codec *codec = w->codec;
1044         dev_dbg(codec->dev, "SRC status: %x\n",
1045                 snd_soc_read(codec,
1046                              WM8994_RATE_STATUS));
1047         return 0;
1048 }
1049
1050 static const struct snd_kcontrol_new aif1adc1l_mix[] = {
1051 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1052                 1, 1, 0),
1053 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_LEFT_MIXER_ROUTING,
1054                 0, 1, 0),
1055 };
1056
1057 static const struct snd_kcontrol_new aif1adc1r_mix[] = {
1058 SOC_DAPM_SINGLE("ADC/DMIC Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1059                 1, 1, 0),
1060 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC1_RIGHT_MIXER_ROUTING,
1061                 0, 1, 0),
1062 };
1063
1064 static const struct snd_kcontrol_new aif1adc2l_mix[] = {
1065 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1066                 1, 1, 0),
1067 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_LEFT_MIXER_ROUTING,
1068                 0, 1, 0),
1069 };
1070
1071 static const struct snd_kcontrol_new aif1adc2r_mix[] = {
1072 SOC_DAPM_SINGLE("DMIC Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1073                 1, 1, 0),
1074 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_AIF1_ADC2_RIGHT_MIXER_ROUTING,
1075                 0, 1, 0),
1076 };
1077
1078 static const struct snd_kcontrol_new aif2dac2l_mix[] = {
1079 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1080                 5, 1, 0),
1081 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1082                 4, 1, 0),
1083 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1084                 2, 1, 0),
1085 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1086                 1, 1, 0),
1087 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_LEFT_MIXER_ROUTING,
1088                 0, 1, 0),
1089 };
1090
1091 static const struct snd_kcontrol_new aif2dac2r_mix[] = {
1092 SOC_DAPM_SINGLE("Right Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1093                 5, 1, 0),
1094 SOC_DAPM_SINGLE("Left Sidetone Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1095                 4, 1, 0),
1096 SOC_DAPM_SINGLE("AIF2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1097                 2, 1, 0),
1098 SOC_DAPM_SINGLE("AIF1.2 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1099                 1, 1, 0),
1100 SOC_DAPM_SINGLE("AIF1.1 Switch", WM8994_DAC2_RIGHT_MIXER_ROUTING,
1101                 0, 1, 0),
1102 };
1103
1104 #define WM8994_CLASS_W_SWITCH(xname, reg, shift, max, invert) \
1105 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1106         .info = snd_soc_info_volsw, \
1107         .get = snd_soc_dapm_get_volsw, .put = wm8994_put_class_w, \
1108         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
1109
1110 static int wm8994_put_class_w(struct snd_kcontrol *kcontrol,
1111                               struct snd_ctl_elem_value *ucontrol)
1112 {
1113         struct snd_soc_dapm_widget *w = snd_kcontrol_chip(kcontrol);
1114         struct snd_soc_codec *codec = w->codec;
1115         int ret;
1116
1117         ret = snd_soc_dapm_put_volsw(kcontrol, ucontrol);
1118
1119         wm8994_update_class_w(codec);
1120
1121         return ret;
1122 }
1123
1124 static const struct snd_kcontrol_new dac1l_mix[] = {
1125 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1126                       5, 1, 0),
1127 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1128                       4, 1, 0),
1129 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1130                       2, 1, 0),
1131 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1132                       1, 1, 0),
1133 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_LEFT_MIXER_ROUTING,
1134                       0, 1, 0),
1135 };
1136
1137 static const struct snd_kcontrol_new dac1r_mix[] = {
1138 WM8994_CLASS_W_SWITCH("Right Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1139                       5, 1, 0),
1140 WM8994_CLASS_W_SWITCH("Left Sidetone Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1141                       4, 1, 0),
1142 WM8994_CLASS_W_SWITCH("AIF2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1143                       2, 1, 0),
1144 WM8994_CLASS_W_SWITCH("AIF1.2 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1145                       1, 1, 0),
1146 WM8994_CLASS_W_SWITCH("AIF1.1 Switch", WM8994_DAC1_RIGHT_MIXER_ROUTING,
1147                       0, 1, 0),
1148 };
1149
1150 static const char *sidetone_text[] = {
1151         "ADC/DMIC1", "DMIC2",
1152 };
1153
1154 static const struct soc_enum sidetone1_enum =
1155         SOC_ENUM_SINGLE(WM8994_SIDETONE, 0, 2, sidetone_text);
1156
1157 static const struct snd_kcontrol_new sidetone1_mux =
1158         SOC_DAPM_ENUM("Left Sidetone Mux", sidetone1_enum);
1159
1160 static const struct soc_enum sidetone2_enum =
1161         SOC_ENUM_SINGLE(WM8994_SIDETONE, 1, 2, sidetone_text);
1162
1163 static const struct snd_kcontrol_new sidetone2_mux =
1164         SOC_DAPM_ENUM("Right Sidetone Mux", sidetone2_enum);
1165
1166 static const char *aif1dac_text[] = {
1167         "AIF1DACDAT", "AIF3DACDAT",
1168 };
1169
1170 static const struct soc_enum aif1dac_enum =
1171         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 0, 2, aif1dac_text);
1172
1173 static const struct snd_kcontrol_new aif1dac_mux =
1174         SOC_DAPM_ENUM("AIF1DAC Mux", aif1dac_enum);
1175
1176 static const char *aif2dac_text[] = {
1177         "AIF2DACDAT", "AIF3DACDAT",
1178 };
1179
1180 static const struct soc_enum aif2dac_enum =
1181         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 1, 2, aif2dac_text);
1182
1183 static const struct snd_kcontrol_new aif2dac_mux =
1184         SOC_DAPM_ENUM("AIF2DAC Mux", aif2dac_enum);
1185
1186 static const char *aif2adc_text[] = {
1187         "AIF2ADCDAT", "AIF3DACDAT",
1188 };
1189
1190 static const struct soc_enum aif2adc_enum =
1191         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 2, 2, aif2adc_text);
1192
1193 static const struct snd_kcontrol_new aif2adc_mux =
1194         SOC_DAPM_ENUM("AIF2ADC Mux", aif2adc_enum);
1195
1196 static const char *aif3adc_text[] = {
1197         "AIF1ADCDAT", "AIF2ADCDAT", "AIF2DACDAT", "Mono PCM",
1198 };
1199
1200 static const struct soc_enum wm8994_aif3adc_enum =
1201         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 3, aif3adc_text);
1202
1203 static const struct snd_kcontrol_new wm8994_aif3adc_mux =
1204         SOC_DAPM_ENUM("AIF3ADC Mux", wm8994_aif3adc_enum);
1205
1206 static const struct soc_enum wm8958_aif3adc_enum =
1207         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 3, 4, aif3adc_text);
1208
1209 static const struct snd_kcontrol_new wm8958_aif3adc_mux =
1210         SOC_DAPM_ENUM("AIF3ADC Mux", wm8958_aif3adc_enum);
1211
1212 static const char *mono_pcm_out_text[] = {
1213         "None", "AIF2ADCL", "AIF2ADCR",
1214 };
1215
1216 static const struct soc_enum mono_pcm_out_enum =
1217         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 9, 3, mono_pcm_out_text);
1218
1219 static const struct snd_kcontrol_new mono_pcm_out_mux =
1220         SOC_DAPM_ENUM("Mono PCM Out Mux", mono_pcm_out_enum);
1221
1222 static const char *aif2dac_src_text[] = {
1223         "AIF2", "AIF3",
1224 };
1225
1226 /* Note that these two control shouldn't be simultaneously switched to AIF3 */
1227 static const struct soc_enum aif2dacl_src_enum =
1228         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 7, 2, aif2dac_src_text);
1229
1230 static const struct snd_kcontrol_new aif2dacl_src_mux =
1231         SOC_DAPM_ENUM("AIF2DACL Mux", aif2dacl_src_enum);
1232
1233 static const struct soc_enum aif2dacr_src_enum =
1234         SOC_ENUM_SINGLE(WM8994_POWER_MANAGEMENT_6, 8, 2, aif2dac_src_text);
1235
1236 static const struct snd_kcontrol_new aif2dacr_src_mux =
1237         SOC_DAPM_ENUM("AIF2DACR Mux", aif2dacr_src_enum);
1238
1239 static const struct snd_soc_dapm_widget wm8994_dapm_widgets[] = {
1240 SND_SOC_DAPM_INPUT("DMIC1DAT"),
1241 SND_SOC_DAPM_INPUT("DMIC2DAT"),
1242 SND_SOC_DAPM_INPUT("Clock"),
1243
1244 SND_SOC_DAPM_SUPPLY("CLK_SYS", SND_SOC_NOPM, 0, 0, clk_sys_event,
1245                     SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1246
1247 SND_SOC_DAPM_SUPPLY("DSP1CLK", WM8994_CLOCKING_1, 3, 0, NULL, 0),
1248 SND_SOC_DAPM_SUPPLY("DSP2CLK", WM8994_CLOCKING_1, 2, 0, NULL, 0),
1249 SND_SOC_DAPM_SUPPLY("DSPINTCLK", WM8994_CLOCKING_1, 1, 0, NULL, 0),
1250
1251 SND_SOC_DAPM_SUPPLY("AIF1CLK", WM8994_AIF1_CLOCKING_1, 0, 0, NULL, 0),
1252 SND_SOC_DAPM_SUPPLY("AIF2CLK", WM8994_AIF2_CLOCKING_1, 0, 0, NULL, 0),
1253
1254 SND_SOC_DAPM_AIF_OUT("AIF1ADC1L", "AIF1 Capture",
1255                      0, WM8994_POWER_MANAGEMENT_4, 9, 0),
1256 SND_SOC_DAPM_AIF_OUT("AIF1ADC1R", "AIF1 Capture",
1257                      0, WM8994_POWER_MANAGEMENT_4, 8, 0),
1258 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1L", NULL, 0,
1259                       WM8994_POWER_MANAGEMENT_5, 9, 0, wm8958_aif_ev,
1260                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1261 SND_SOC_DAPM_AIF_IN_E("AIF1DAC1R", NULL, 0,
1262                       WM8994_POWER_MANAGEMENT_5, 8, 0, wm8958_aif_ev,
1263                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1264
1265 SND_SOC_DAPM_AIF_OUT("AIF1ADC2L", "AIF1 Capture",
1266                      0, WM8994_POWER_MANAGEMENT_4, 11, 0),
1267 SND_SOC_DAPM_AIF_OUT("AIF1ADC2R", "AIF1 Capture",
1268                      0, WM8994_POWER_MANAGEMENT_4, 10, 0),
1269 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2L", NULL, 0,
1270                       WM8994_POWER_MANAGEMENT_5, 11, 0, wm8958_aif_ev,
1271                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1272 SND_SOC_DAPM_AIF_IN_E("AIF1DAC2R", NULL, 0,
1273                       WM8994_POWER_MANAGEMENT_5, 10, 0, wm8958_aif_ev,
1274                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1275
1276 SND_SOC_DAPM_MIXER("AIF1ADC1L Mixer", SND_SOC_NOPM, 0, 0,
1277                    aif1adc1l_mix, ARRAY_SIZE(aif1adc1l_mix)),
1278 SND_SOC_DAPM_MIXER("AIF1ADC1R Mixer", SND_SOC_NOPM, 0, 0,
1279                    aif1adc1r_mix, ARRAY_SIZE(aif1adc1r_mix)),
1280
1281 SND_SOC_DAPM_MIXER("AIF1ADC2L Mixer", SND_SOC_NOPM, 0, 0,
1282                    aif1adc2l_mix, ARRAY_SIZE(aif1adc2l_mix)),
1283 SND_SOC_DAPM_MIXER("AIF1ADC2R Mixer", SND_SOC_NOPM, 0, 0,
1284                    aif1adc2r_mix, ARRAY_SIZE(aif1adc2r_mix)),
1285
1286 SND_SOC_DAPM_MIXER("AIF2DAC2L Mixer", SND_SOC_NOPM, 0, 0,
1287                    aif2dac2l_mix, ARRAY_SIZE(aif2dac2l_mix)),
1288 SND_SOC_DAPM_MIXER("AIF2DAC2R Mixer", SND_SOC_NOPM, 0, 0,
1289                    aif2dac2r_mix, ARRAY_SIZE(aif2dac2r_mix)),
1290
1291 SND_SOC_DAPM_MUX("Left Sidetone", SND_SOC_NOPM, 0, 0, &sidetone1_mux),
1292 SND_SOC_DAPM_MUX("Right Sidetone", SND_SOC_NOPM, 0, 0, &sidetone2_mux),
1293
1294 SND_SOC_DAPM_MIXER("DAC1L Mixer", SND_SOC_NOPM, 0, 0,
1295                    dac1l_mix, ARRAY_SIZE(dac1l_mix)),
1296 SND_SOC_DAPM_MIXER("DAC1R Mixer", SND_SOC_NOPM, 0, 0,
1297                    dac1r_mix, ARRAY_SIZE(dac1r_mix)),
1298
1299 SND_SOC_DAPM_AIF_OUT("AIF2ADCL", NULL, 0,
1300                      WM8994_POWER_MANAGEMENT_4, 13, 0),
1301 SND_SOC_DAPM_AIF_OUT("AIF2ADCR", NULL, 0,
1302                      WM8994_POWER_MANAGEMENT_4, 12, 0),
1303 SND_SOC_DAPM_AIF_IN_E("AIF2DACL", NULL, 0,
1304                       WM8994_POWER_MANAGEMENT_5, 13, 0, wm8958_aif_ev,
1305                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1306 SND_SOC_DAPM_AIF_IN_E("AIF2DACR", NULL, 0,
1307                       WM8994_POWER_MANAGEMENT_5, 12, 0, wm8958_aif_ev,
1308                       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
1309
1310 SND_SOC_DAPM_AIF_IN("AIF1DACDAT", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1311 SND_SOC_DAPM_AIF_IN("AIF2DACDAT", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
1312 SND_SOC_DAPM_AIF_OUT("AIF2ADCDAT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
1313
1314 SND_SOC_DAPM_MUX("AIF1DAC Mux", SND_SOC_NOPM, 0, 0, &aif1dac_mux),
1315 SND_SOC_DAPM_MUX("AIF2DAC Mux", SND_SOC_NOPM, 0, 0, &aif2dac_mux),
1316 SND_SOC_DAPM_MUX("AIF2ADC Mux", SND_SOC_NOPM, 0, 0, &aif2adc_mux),
1317
1318 SND_SOC_DAPM_AIF_IN("AIF3DACDAT", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
1319 SND_SOC_DAPM_AIF_IN("AIF3ADCDAT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
1320
1321 SND_SOC_DAPM_SUPPLY("TOCLK", WM8994_CLOCKING_1, 4, 0, NULL, 0),
1322
1323 SND_SOC_DAPM_ADC("DMIC2L", NULL, WM8994_POWER_MANAGEMENT_4, 5, 0),
1324 SND_SOC_DAPM_ADC("DMIC2R", NULL, WM8994_POWER_MANAGEMENT_4, 4, 0),
1325 SND_SOC_DAPM_ADC("DMIC1L", NULL, WM8994_POWER_MANAGEMENT_4, 3, 0),
1326 SND_SOC_DAPM_ADC("DMIC1R", NULL, WM8994_POWER_MANAGEMENT_4, 2, 0),
1327
1328 /* Power is done with the muxes since the ADC power also controls the
1329  * downsampling chain, the chip will automatically manage the analogue
1330  * specific portions.
1331  */
1332 SND_SOC_DAPM_ADC("ADCL", NULL, SND_SOC_NOPM, 1, 0),
1333 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1334
1335 SND_SOC_DAPM_MUX("ADCL Mux", WM8994_POWER_MANAGEMENT_4, 1, 0, &adcl_mux),
1336 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1337
1338 SND_SOC_DAPM_DAC("DAC2L", NULL, WM8994_POWER_MANAGEMENT_5, 3, 0),
1339 SND_SOC_DAPM_DAC("DAC2R", NULL, WM8994_POWER_MANAGEMENT_5, 2, 0),
1340 SND_SOC_DAPM_DAC("DAC1L", NULL, WM8994_POWER_MANAGEMENT_5, 1, 0),
1341 SND_SOC_DAPM_DAC("DAC1R", NULL, WM8994_POWER_MANAGEMENT_5, 0, 0),
1342
1343 SND_SOC_DAPM_MUX("Left Headphone Mux", SND_SOC_NOPM, 0, 0, &hpl_mux),
1344 SND_SOC_DAPM_MUX("Right Headphone Mux", SND_SOC_NOPM, 0, 0, &hpr_mux),
1345
1346 SND_SOC_DAPM_MIXER("SPKL", WM8994_POWER_MANAGEMENT_3, 8, 0,
1347                    left_speaker_mixer, ARRAY_SIZE(left_speaker_mixer)),
1348 SND_SOC_DAPM_MIXER("SPKR", WM8994_POWER_MANAGEMENT_3, 9, 0,
1349                    right_speaker_mixer, ARRAY_SIZE(right_speaker_mixer)),
1350
1351 SND_SOC_DAPM_POST("Debug log", post_ev),
1352 };
1353
1354 static const struct snd_soc_dapm_widget wm8994_specific_dapm_widgets[] = {
1355 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8994_aif3adc_mux),
1356 };
1357
1358 static const struct snd_soc_dapm_widget wm8958_dapm_widgets[] = {
1359 SND_SOC_DAPM_MUX("Mono PCM Out Mux", SND_SOC_NOPM, 0, 0, &mono_pcm_out_mux),
1360 SND_SOC_DAPM_MUX("AIF2DACL Mux", SND_SOC_NOPM, 0, 0, &aif2dacl_src_mux),
1361 SND_SOC_DAPM_MUX("AIF2DACR Mux", SND_SOC_NOPM, 0, 0, &aif2dacr_src_mux),
1362 SND_SOC_DAPM_MUX("AIF3ADC Mux", SND_SOC_NOPM, 0, 0, &wm8958_aif3adc_mux),
1363 };
1364
1365 static const struct snd_soc_dapm_route intercon[] = {
1366         { "CLK_SYS", NULL, "AIF1CLK", check_clk_sys },
1367         { "CLK_SYS", NULL, "AIF2CLK", check_clk_sys },
1368
1369         { "DSP1CLK", NULL, "CLK_SYS" },
1370         { "DSP2CLK", NULL, "CLK_SYS" },
1371         { "DSPINTCLK", NULL, "CLK_SYS" },
1372
1373         { "AIF1ADC1L", NULL, "AIF1CLK" },
1374         { "AIF1ADC1L", NULL, "DSP1CLK" },
1375         { "AIF1ADC1R", NULL, "AIF1CLK" },
1376         { "AIF1ADC1R", NULL, "DSP1CLK" },
1377         { "AIF1ADC1R", NULL, "DSPINTCLK" },
1378
1379         { "AIF1DAC1L", NULL, "AIF1CLK" },
1380         { "AIF1DAC1L", NULL, "DSP1CLK" },
1381         { "AIF1DAC1R", NULL, "AIF1CLK" },
1382         { "AIF1DAC1R", NULL, "DSP1CLK" },
1383         { "AIF1DAC1R", NULL, "DSPINTCLK" },
1384
1385         { "AIF1ADC2L", NULL, "AIF1CLK" },
1386         { "AIF1ADC2L", NULL, "DSP1CLK" },
1387         { "AIF1ADC2R", NULL, "AIF1CLK" },
1388         { "AIF1ADC2R", NULL, "DSP1CLK" },
1389         { "AIF1ADC2R", NULL, "DSPINTCLK" },
1390
1391         { "AIF1DAC2L", NULL, "AIF1CLK" },
1392         { "AIF1DAC2L", NULL, "DSP1CLK" },
1393         { "AIF1DAC2R", NULL, "AIF1CLK" },
1394         { "AIF1DAC2R", NULL, "DSP1CLK" },
1395         { "AIF1DAC2R", NULL, "DSPINTCLK" },
1396
1397         { "AIF2ADCL", NULL, "AIF2CLK" },
1398         { "AIF2ADCL", NULL, "DSP2CLK" },
1399         { "AIF2ADCR", NULL, "AIF2CLK" },
1400         { "AIF2ADCR", NULL, "DSP2CLK" },
1401         { "AIF2ADCR", NULL, "DSPINTCLK" },
1402
1403         { "AIF2DACL", NULL, "AIF2CLK" },
1404         { "AIF2DACL", NULL, "DSP2CLK" },
1405         { "AIF2DACR", NULL, "AIF2CLK" },
1406         { "AIF2DACR", NULL, "DSP2CLK" },
1407         { "AIF2DACR", NULL, "DSPINTCLK" },
1408
1409         { "DMIC1L", NULL, "DMIC1DAT" },
1410         { "DMIC1L", NULL, "CLK_SYS" },
1411         { "DMIC1R", NULL, "DMIC1DAT" },
1412         { "DMIC1R", NULL, "CLK_SYS" },
1413         { "DMIC2L", NULL, "DMIC2DAT" },
1414         { "DMIC2L", NULL, "CLK_SYS" },
1415         { "DMIC2R", NULL, "DMIC2DAT" },
1416         { "DMIC2R", NULL, "CLK_SYS" },
1417
1418         { "ADCL", NULL, "AIF1CLK" },
1419         { "ADCL", NULL, "DSP1CLK" },
1420         { "ADCL", NULL, "DSPINTCLK" },
1421
1422         { "ADCR", NULL, "AIF1CLK" },
1423         { "ADCR", NULL, "DSP1CLK" },
1424         { "ADCR", NULL, "DSPINTCLK" },
1425
1426         { "ADCL Mux", "ADC", "ADCL" },
1427         { "ADCL Mux", "DMIC", "DMIC1L" },
1428         { "ADCR Mux", "ADC", "ADCR" },
1429         { "ADCR Mux", "DMIC", "DMIC1R" },
1430
1431         { "DAC1L", NULL, "AIF1CLK" },
1432         { "DAC1L", NULL, "DSP1CLK" },
1433         { "DAC1L", NULL, "DSPINTCLK" },
1434
1435         { "DAC1R", NULL, "AIF1CLK" },
1436         { "DAC1R", NULL, "DSP1CLK" },
1437         { "DAC1R", NULL, "DSPINTCLK" },
1438
1439         { "DAC2L", NULL, "AIF2CLK" },
1440         { "DAC2L", NULL, "DSP2CLK" },
1441         { "DAC2L", NULL, "DSPINTCLK" },
1442
1443         { "DAC2R", NULL, "AIF2DACR" },
1444         { "DAC2R", NULL, "AIF2CLK" },
1445         { "DAC2R", NULL, "DSP2CLK" },
1446         { "DAC2R", NULL, "DSPINTCLK" },
1447
1448         { "TOCLK", NULL, "CLK_SYS" },
1449
1450         /* AIF1 outputs */
1451         { "AIF1ADC1L", NULL, "AIF1ADC1L Mixer" },
1452         { "AIF1ADC1L Mixer", "ADC/DMIC Switch", "ADCL Mux" },
1453         { "AIF1ADC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1454
1455         { "AIF1ADC1R", NULL, "AIF1ADC1R Mixer" },
1456         { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1457         { "AIF1ADC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1458
1459         { "AIF1ADC2L", NULL, "AIF1ADC2L Mixer" },
1460         { "AIF1ADC2L Mixer", "DMIC Switch", "DMIC2L" },
1461         { "AIF1ADC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1462
1463         { "AIF1ADC2R", NULL, "AIF1ADC2R Mixer" },
1464         { "AIF1ADC2R Mixer", "DMIC Switch", "DMIC2R" },
1465         { "AIF1ADC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1466
1467         /* Pin level routing for AIF3 */
1468         { "AIF1DAC1L", NULL, "AIF1DAC Mux" },
1469         { "AIF1DAC1R", NULL, "AIF1DAC Mux" },
1470         { "AIF1DAC2L", NULL, "AIF1DAC Mux" },
1471         { "AIF1DAC2R", NULL, "AIF1DAC Mux" },
1472
1473         { "AIF1DAC Mux", "AIF1DACDAT", "AIF1DACDAT" },
1474         { "AIF1DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1475         { "AIF2DAC Mux", "AIF2DACDAT", "AIF2DACDAT" },
1476         { "AIF2DAC Mux", "AIF3DACDAT", "AIF3DACDAT" },
1477         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCL" },
1478         { "AIF2ADC Mux", "AIF2ADCDAT", "AIF2ADCR" },
1479         { "AIF2ADC Mux", "AIF3DACDAT", "AIF3ADCDAT" },
1480
1481         /* DAC1 inputs */
1482         { "DAC1L", NULL, "DAC1L Mixer" },
1483         { "DAC1L Mixer", "AIF2 Switch", "AIF2DACL" },
1484         { "DAC1L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1485         { "DAC1L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1486         { "DAC1L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1487         { "DAC1L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1488
1489         { "DAC1R", NULL, "DAC1R Mixer" },
1490         { "DAC1R Mixer", "AIF2 Switch", "AIF2DACR" },
1491         { "DAC1R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1492         { "DAC1R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1493         { "DAC1R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1494         { "DAC1R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1495
1496         /* DAC2/AIF2 outputs  */
1497         { "AIF2ADCL", NULL, "AIF2DAC2L Mixer" },
1498         { "DAC2L", NULL, "AIF2DAC2L Mixer" },
1499         { "AIF2DAC2L Mixer", "AIF2 Switch", "AIF2DACL" },
1500         { "AIF2DAC2L Mixer", "AIF1.2 Switch", "AIF1DAC2L" },
1501         { "AIF2DAC2L Mixer", "AIF1.1 Switch", "AIF1DAC1L" },
1502         { "AIF2DAC2L Mixer", "Left Sidetone Switch", "Left Sidetone" },
1503         { "AIF2DAC2L Mixer", "Right Sidetone Switch", "Right Sidetone" },
1504
1505         { "AIF2ADCR", NULL, "AIF2DAC2R Mixer" },
1506         { "DAC2R", NULL, "AIF2DAC2R Mixer" },
1507         { "AIF2DAC2R Mixer", "AIF2 Switch", "AIF2DACR" },
1508         { "AIF2DAC2R Mixer", "AIF1.2 Switch", "AIF1DAC2R" },
1509         { "AIF2DAC2R Mixer", "AIF1.1 Switch", "AIF1DAC1R" },
1510         { "AIF2DAC2R Mixer", "Left Sidetone Switch", "Left Sidetone" },
1511         { "AIF2DAC2R Mixer", "Right Sidetone Switch", "Right Sidetone" },
1512
1513         { "AIF2ADCDAT", NULL, "AIF2ADC Mux" },
1514
1515         /* AIF3 output */
1516         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1L" },
1517         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC1R" },
1518         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2L" },
1519         { "AIF3ADCDAT", "AIF1ADCDAT", "AIF1ADC2R" },
1520         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCL" },
1521         { "AIF3ADCDAT", "AIF2ADCDAT", "AIF2ADCR" },
1522         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACL" },
1523         { "AIF3ADCDAT", "AIF2DACDAT", "AIF2DACR" },
1524
1525         /* Sidetone */
1526         { "Left Sidetone", "ADC/DMIC1", "ADCL Mux" },
1527         { "Left Sidetone", "DMIC2", "DMIC2L" },
1528         { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
1529         { "Right Sidetone", "DMIC2", "DMIC2R" },
1530
1531         /* Output stages */
1532         { "Left Output Mixer", "DAC Switch", "DAC1L" },
1533         { "Right Output Mixer", "DAC Switch", "DAC1R" },
1534
1535         { "SPKL", "DAC1 Switch", "DAC1L" },
1536         { "SPKL", "DAC2 Switch", "DAC2L" },
1537
1538         { "SPKR", "DAC1 Switch", "DAC1R" },
1539         { "SPKR", "DAC2 Switch", "DAC2R" },
1540
1541         { "Left Headphone Mux", "DAC", "DAC1L" },
1542         { "Right Headphone Mux", "DAC", "DAC1R" },
1543 };
1544
1545 static const struct snd_soc_dapm_route wm8994_intercon[] = {
1546         { "AIF2DACL", NULL, "AIF2DAC Mux" },
1547         { "AIF2DACR", NULL, "AIF2DAC Mux" },
1548 };
1549
1550 static const struct snd_soc_dapm_route wm8958_intercon[] = {
1551         { "AIF2DACL", NULL, "AIF2DACL Mux" },
1552         { "AIF2DACR", NULL, "AIF2DACR Mux" },
1553
1554         { "AIF2DACL Mux", "AIF2", "AIF2DAC Mux" },
1555         { "AIF2DACL Mux", "AIF3", "AIF3DACDAT" },
1556         { "AIF2DACR Mux", "AIF2", "AIF2DAC Mux" },
1557         { "AIF2DACR Mux", "AIF3", "AIF3DACDAT" },
1558
1559         { "Mono PCM Out Mux", "AIF2ADCL", "AIF2ADCL" },
1560         { "Mono PCM Out Mux", "AIF2ADCR", "AIF2ADCR" },
1561
1562         { "AIF3ADC Mux", "Mono PCM", "Mono PCM Out Mux" },
1563 };
1564
1565 /* The size in bits of the FLL divide multiplied by 10
1566  * to allow rounding later */
1567 #define FIXED_FLL_SIZE ((1 << 16) * 10)
1568
1569 struct fll_div {
1570         u16 outdiv;
1571         u16 n;
1572         u16 k;
1573         u16 clk_ref_div;
1574         u16 fll_fratio;
1575 };
1576
1577 static int wm8994_get_fll_config(struct fll_div *fll,
1578                                  int freq_in, int freq_out)
1579 {
1580         u64 Kpart;
1581         unsigned int K, Ndiv, Nmod;
1582
1583         pr_debug("FLL input=%dHz, output=%dHz\n", freq_in, freq_out);
1584
1585         /* Scale the input frequency down to <= 13.5MHz */
1586         fll->clk_ref_div = 0;
1587         while (freq_in > 13500000) {
1588                 fll->clk_ref_div++;
1589                 freq_in /= 2;
1590
1591                 if (fll->clk_ref_div > 3)
1592                         return -EINVAL;
1593         }
1594         pr_debug("CLK_REF_DIV=%d, Fref=%dHz\n", fll->clk_ref_div, freq_in);
1595
1596         /* Scale the output to give 90MHz<=Fvco<=100MHz */
1597         fll->outdiv = 3;
1598         while (freq_out * (fll->outdiv + 1) < 90000000) {
1599                 fll->outdiv++;
1600                 if (fll->outdiv > 63)
1601                         return -EINVAL;
1602         }
1603         freq_out *= fll->outdiv + 1;
1604         pr_debug("OUTDIV=%d, Fvco=%dHz\n", fll->outdiv, freq_out);
1605
1606         if (freq_in > 1000000) {
1607                 fll->fll_fratio = 0;
1608         } else if (freq_in > 256000) {
1609                 fll->fll_fratio = 1;
1610                 freq_in *= 2;
1611         } else if (freq_in > 128000) {
1612                 fll->fll_fratio = 2;
1613                 freq_in *= 4;
1614         } else if (freq_in > 64000) {
1615                 fll->fll_fratio = 3;
1616                 freq_in *= 8;
1617         } else {
1618                 fll->fll_fratio = 4;
1619                 freq_in *= 16;
1620         }
1621         pr_debug("FLL_FRATIO=%d, Fref=%dHz\n", fll->fll_fratio, freq_in);
1622
1623         /* Now, calculate N.K */
1624         Ndiv = freq_out / freq_in;
1625
1626         fll->n = Ndiv;
1627         Nmod = freq_out % freq_in;
1628         pr_debug("Nmod=%d\n", Nmod);
1629
1630         /* Calculate fractional part - scale up so we can round. */
1631         Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1632
1633         do_div(Kpart, freq_in);
1634
1635         K = Kpart & 0xFFFFFFFF;
1636
1637         if ((K % 10) >= 5)
1638                 K += 5;
1639
1640         /* Move down to proper range now rounding is done */
1641         fll->k = K / 10;
1642
1643         pr_debug("N=%x K=%x\n", fll->n, fll->k);
1644
1645         return 0;
1646 }
1647
1648 static int _wm8994_set_fll(struct snd_soc_codec *codec, int id, int src,
1649                           unsigned int freq_in, unsigned int freq_out)
1650 {
1651         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1652         int reg_offset, ret;
1653         struct fll_div fll;
1654         u16 reg, aif1, aif2;
1655
1656         aif1 = snd_soc_read(codec, WM8994_AIF1_CLOCKING_1)
1657                 & WM8994_AIF1CLK_ENA;
1658
1659         aif2 = snd_soc_read(codec, WM8994_AIF2_CLOCKING_1)
1660                 & WM8994_AIF2CLK_ENA;
1661
1662         switch (id) {
1663         case WM8994_FLL1:
1664                 reg_offset = 0;
1665                 id = 0;
1666                 break;
1667         case WM8994_FLL2:
1668                 reg_offset = 0x20;
1669                 id = 1;
1670                 break;
1671         default:
1672                 return -EINVAL;
1673         }
1674
1675         switch (src) {
1676         case 0:
1677                 /* Allow no source specification when stopping */
1678                 if (freq_out)
1679                         return -EINVAL;
1680                 src = wm8994->fll[id].src;
1681                 break;
1682         case WM8994_FLL_SRC_MCLK1:
1683         case WM8994_FLL_SRC_MCLK2:
1684         case WM8994_FLL_SRC_LRCLK:
1685         case WM8994_FLL_SRC_BCLK:
1686                 break;
1687         default:
1688                 return -EINVAL;
1689         }
1690
1691         /* Are we changing anything? */
1692         if (wm8994->fll[id].src == src &&
1693             wm8994->fll[id].in == freq_in && wm8994->fll[id].out == freq_out)
1694                 return 0;
1695
1696         /* If we're stopping the FLL redo the old config - no
1697          * registers will actually be written but we avoid GCC flow
1698          * analysis bugs spewing warnings.
1699          */
1700         if (freq_out)
1701                 ret = wm8994_get_fll_config(&fll, freq_in, freq_out);
1702         else
1703                 ret = wm8994_get_fll_config(&fll, wm8994->fll[id].in,
1704                                             wm8994->fll[id].out);
1705         if (ret < 0)
1706                 return ret;
1707
1708         /* Gate the AIF clocks while we reclock */
1709         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1710                             WM8994_AIF1CLK_ENA, 0);
1711         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1712                             WM8994_AIF2CLK_ENA, 0);
1713
1714         /* We always need to disable the FLL while reconfiguring */
1715         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1716                             WM8994_FLL1_ENA, 0);
1717
1718         reg = (fll.outdiv << WM8994_FLL1_OUTDIV_SHIFT) |
1719                 (fll.fll_fratio << WM8994_FLL1_FRATIO_SHIFT);
1720         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_2 + reg_offset,
1721                             WM8994_FLL1_OUTDIV_MASK |
1722                             WM8994_FLL1_FRATIO_MASK, reg);
1723
1724         snd_soc_write(codec, WM8994_FLL1_CONTROL_3 + reg_offset, fll.k);
1725
1726         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_4 + reg_offset,
1727                             WM8994_FLL1_N_MASK,
1728                                     fll.n << WM8994_FLL1_N_SHIFT);
1729
1730         snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_5 + reg_offset,
1731                             WM8994_FLL1_REFCLK_DIV_MASK |
1732                             WM8994_FLL1_REFCLK_SRC_MASK,
1733                             (fll.clk_ref_div << WM8994_FLL1_REFCLK_DIV_SHIFT) |
1734                             (src - 1));
1735
1736         /* Enable (with fractional mode if required) */
1737         if (freq_out) {
1738                 if (fll.k)
1739                         reg = WM8994_FLL1_ENA | WM8994_FLL1_FRAC;
1740                 else
1741                         reg = WM8994_FLL1_ENA;
1742                 snd_soc_update_bits(codec, WM8994_FLL1_CONTROL_1 + reg_offset,
1743                                     WM8994_FLL1_ENA | WM8994_FLL1_FRAC,
1744                                     reg);
1745         }
1746
1747         wm8994->fll[id].in = freq_in;
1748         wm8994->fll[id].out = freq_out;
1749         wm8994->fll[id].src = src;
1750
1751         /* Enable any gated AIF clocks */
1752         snd_soc_update_bits(codec, WM8994_AIF1_CLOCKING_1,
1753                             WM8994_AIF1CLK_ENA, aif1);
1754         snd_soc_update_bits(codec, WM8994_AIF2_CLOCKING_1,
1755                             WM8994_AIF2CLK_ENA, aif2);
1756
1757         configure_clock(codec);
1758
1759         return 0;
1760 }
1761
1762
1763 static int opclk_divs[] = { 10, 20, 30, 40, 55, 60, 80, 120, 160 };
1764
1765 static int wm8994_set_fll(struct snd_soc_dai *dai, int id, int src,
1766                           unsigned int freq_in, unsigned int freq_out)
1767 {
1768         return _wm8994_set_fll(dai->codec, id, src, freq_in, freq_out);
1769 }
1770
1771 static int wm8994_set_dai_sysclk(struct snd_soc_dai *dai,
1772                 int clk_id, unsigned int freq, int dir)
1773 {
1774         struct snd_soc_codec *codec = dai->codec;
1775         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1776         int i;
1777
1778         switch (dai->id) {
1779         case 1:
1780         case 2:
1781                 break;
1782
1783         default:
1784                 /* AIF3 shares clocking with AIF1/2 */
1785                 return -EINVAL;
1786         }
1787
1788         switch (clk_id) {
1789         case WM8994_SYSCLK_MCLK1:
1790                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK1;
1791                 wm8994->mclk[0] = freq;
1792                 dev_dbg(dai->dev, "AIF%d using MCLK1 at %uHz\n",
1793                         dai->id, freq);
1794                 break;
1795
1796         case WM8994_SYSCLK_MCLK2:
1797                 /* TODO: Set GPIO AF */
1798                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_MCLK2;
1799                 wm8994->mclk[1] = freq;
1800                 dev_dbg(dai->dev, "AIF%d using MCLK2 at %uHz\n",
1801                         dai->id, freq);
1802                 break;
1803
1804         case WM8994_SYSCLK_FLL1:
1805                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL1;
1806                 dev_dbg(dai->dev, "AIF%d using FLL1\n", dai->id);
1807                 break;
1808
1809         case WM8994_SYSCLK_FLL2:
1810                 wm8994->sysclk[dai->id - 1] = WM8994_SYSCLK_FLL2;
1811                 dev_dbg(dai->dev, "AIF%d using FLL2\n", dai->id);
1812                 break;
1813
1814         case WM8994_SYSCLK_OPCLK:
1815                 /* Special case - a division (times 10) is given and
1816                  * no effect on main clocking.
1817                  */
1818                 if (freq) {
1819                         for (i = 0; i < ARRAY_SIZE(opclk_divs); i++)
1820                                 if (opclk_divs[i] == freq)
1821                                         break;
1822                         if (i == ARRAY_SIZE(opclk_divs))
1823                                 return -EINVAL;
1824                         snd_soc_update_bits(codec, WM8994_CLOCKING_2,
1825                                             WM8994_OPCLK_DIV_MASK, i);
1826                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1827                                             WM8994_OPCLK_ENA, WM8994_OPCLK_ENA);
1828                 } else {
1829                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_2,
1830                                             WM8994_OPCLK_ENA, 0);
1831                 }
1832
1833         default:
1834                 return -EINVAL;
1835         }
1836
1837         configure_clock(codec);
1838
1839         return 0;
1840 }
1841
1842 static int wm8994_set_bias_level(struct snd_soc_codec *codec,
1843                                  enum snd_soc_bias_level level)
1844 {
1845         struct wm8994 *control = codec->control_data;
1846         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
1847
1848         switch (level) {
1849         case SND_SOC_BIAS_ON:
1850                 break;
1851
1852         case SND_SOC_BIAS_PREPARE:
1853                 /* VMID=2x40k */
1854                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1855                                     WM8994_VMID_SEL_MASK, 0x2);
1856                 break;
1857
1858         case SND_SOC_BIAS_STANDBY:
1859                 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1860                         pm_runtime_get_sync(codec->dev);
1861
1862                         switch (control->type) {
1863                         case WM8994:
1864                                 if (wm8994->revision < 4) {
1865                                         /* Tweak DC servo and DSP
1866                                          * configuration for improved
1867                                          * performance. */
1868                                         snd_soc_write(codec, 0x102, 0x3);
1869                                         snd_soc_write(codec, 0x56, 0x3);
1870                                         snd_soc_write(codec, 0x817, 0);
1871                                         snd_soc_write(codec, 0x102, 0);
1872                                 }
1873                                 break;
1874
1875                         case WM8958:
1876                                 if (wm8994->revision == 0) {
1877                                         /* Optimise performance for rev A */
1878                                         snd_soc_write(codec, 0x102, 0x3);
1879                                         snd_soc_write(codec, 0xcb, 0x81);
1880                                         snd_soc_write(codec, 0x817, 0);
1881                                         snd_soc_write(codec, 0x102, 0);
1882
1883                                         snd_soc_update_bits(codec,
1884                                                             WM8958_CHARGE_PUMP_2,
1885                                                             WM8958_CP_DISCH,
1886                                                             WM8958_CP_DISCH);
1887                                 }
1888                                 break;
1889                         }
1890
1891                         /* Discharge LINEOUT1 & 2 */
1892                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1893                                             WM8994_LINEOUT1_DISCH |
1894                                             WM8994_LINEOUT2_DISCH,
1895                                             WM8994_LINEOUT1_DISCH |
1896                                             WM8994_LINEOUT2_DISCH);
1897
1898                         /* Startup bias, VMID ramp & buffer */
1899                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1900                                             WM8994_STARTUP_BIAS_ENA |
1901                                             WM8994_VMID_BUF_ENA |
1902                                             WM8994_VMID_RAMP_MASK,
1903                                             WM8994_STARTUP_BIAS_ENA |
1904                                             WM8994_VMID_BUF_ENA |
1905                                             (0x11 << WM8994_VMID_RAMP_SHIFT));
1906
1907                         /* Main bias enable, VMID=2x40k */
1908                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1909                                             WM8994_BIAS_ENA |
1910                                             WM8994_VMID_SEL_MASK,
1911                                             WM8994_BIAS_ENA | 0x2);
1912
1913                         msleep(20);
1914                 }
1915
1916                 /* VMID=2x500k */
1917                 snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1918                                     WM8994_VMID_SEL_MASK, 0x4);
1919
1920                 break;
1921
1922         case SND_SOC_BIAS_OFF:
1923                 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY) {
1924                         /* Switch over to startup biases */
1925                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1926                                             WM8994_BIAS_SRC |
1927                                             WM8994_STARTUP_BIAS_ENA |
1928                                             WM8994_VMID_BUF_ENA |
1929                                             WM8994_VMID_RAMP_MASK,
1930                                             WM8994_BIAS_SRC |
1931                                             WM8994_STARTUP_BIAS_ENA |
1932                                             WM8994_VMID_BUF_ENA |
1933                                             (1 << WM8994_VMID_RAMP_SHIFT));
1934
1935                         /* Disable main biases */
1936                         snd_soc_update_bits(codec, WM8994_POWER_MANAGEMENT_1,
1937                                             WM8994_BIAS_ENA |
1938                                             WM8994_VMID_SEL_MASK, 0);
1939
1940                         /* Discharge line */
1941                         snd_soc_update_bits(codec, WM8994_ANTIPOP_1,
1942                                             WM8994_LINEOUT1_DISCH |
1943                                             WM8994_LINEOUT2_DISCH,
1944                                             WM8994_LINEOUT1_DISCH |
1945                                             WM8994_LINEOUT2_DISCH);
1946
1947                         msleep(5);
1948
1949                         /* Switch off startup biases */
1950                         snd_soc_update_bits(codec, WM8994_ANTIPOP_2,
1951                                             WM8994_BIAS_SRC |
1952                                             WM8994_STARTUP_BIAS_ENA |
1953                                             WM8994_VMID_BUF_ENA |
1954                                             WM8994_VMID_RAMP_MASK, 0);
1955
1956                         pm_runtime_put(codec->dev);
1957                 }
1958                 break;
1959         }
1960         codec->dapm.bias_level = level;
1961         return 0;
1962 }
1963
1964 static int wm8994_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1965 {
1966         struct snd_soc_codec *codec = dai->codec;
1967         struct wm8994 *control = codec->control_data;
1968         int ms_reg;
1969         int aif1_reg;
1970         int ms = 0;
1971         int aif1 = 0;
1972
1973         switch (dai->id) {
1974         case 1:
1975                 ms_reg = WM8994_AIF1_MASTER_SLAVE;
1976                 aif1_reg = WM8994_AIF1_CONTROL_1;
1977                 break;
1978         case 2:
1979                 ms_reg = WM8994_AIF2_MASTER_SLAVE;
1980                 aif1_reg = WM8994_AIF2_CONTROL_1;
1981                 break;
1982         default:
1983                 return -EINVAL;
1984         }
1985
1986         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1987         case SND_SOC_DAIFMT_CBS_CFS:
1988                 break;
1989         case SND_SOC_DAIFMT_CBM_CFM:
1990                 ms = WM8994_AIF1_MSTR;
1991                 break;
1992         default:
1993                 return -EINVAL;
1994         }
1995
1996         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1997         case SND_SOC_DAIFMT_DSP_B:
1998                 aif1 |= WM8994_AIF1_LRCLK_INV;
1999         case SND_SOC_DAIFMT_DSP_A:
2000                 aif1 |= 0x18;
2001                 break;
2002         case SND_SOC_DAIFMT_I2S:
2003                 aif1 |= 0x10;
2004                 break;
2005         case SND_SOC_DAIFMT_RIGHT_J:
2006                 break;
2007         case SND_SOC_DAIFMT_LEFT_J:
2008                 aif1 |= 0x8;
2009                 break;
2010         default:
2011                 return -EINVAL;
2012         }
2013
2014         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2015         case SND_SOC_DAIFMT_DSP_A:
2016         case SND_SOC_DAIFMT_DSP_B:
2017                 /* frame inversion not valid for DSP modes */
2018                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2019                 case SND_SOC_DAIFMT_NB_NF:
2020                         break;
2021                 case SND_SOC_DAIFMT_IB_NF:
2022                         aif1 |= WM8994_AIF1_BCLK_INV;
2023                         break;
2024                 default:
2025                         return -EINVAL;
2026                 }
2027                 break;
2028
2029         case SND_SOC_DAIFMT_I2S:
2030         case SND_SOC_DAIFMT_RIGHT_J:
2031         case SND_SOC_DAIFMT_LEFT_J:
2032                 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2033                 case SND_SOC_DAIFMT_NB_NF:
2034                         break;
2035                 case SND_SOC_DAIFMT_IB_IF:
2036                         aif1 |= WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV;
2037                         break;
2038                 case SND_SOC_DAIFMT_IB_NF:
2039                         aif1 |= WM8994_AIF1_BCLK_INV;
2040                         break;
2041                 case SND_SOC_DAIFMT_NB_IF:
2042                         aif1 |= WM8994_AIF1_LRCLK_INV;
2043                         break;
2044                 default:
2045                         return -EINVAL;
2046                 }
2047                 break;
2048         default:
2049                 return -EINVAL;
2050         }
2051
2052         /* The AIF2 format configuration needs to be mirrored to AIF3
2053          * on WM8958 if it's in use so just do it all the time. */
2054         if (control->type == WM8958 && dai->id == 2)
2055                 snd_soc_update_bits(codec, WM8958_AIF3_CONTROL_1,
2056                                     WM8994_AIF1_LRCLK_INV |
2057                                     WM8958_AIF3_FMT_MASK, aif1);
2058
2059         snd_soc_update_bits(codec, aif1_reg,
2060                             WM8994_AIF1_BCLK_INV | WM8994_AIF1_LRCLK_INV |
2061                             WM8994_AIF1_FMT_MASK,
2062                             aif1);
2063         snd_soc_update_bits(codec, ms_reg, WM8994_AIF1_MSTR,
2064                             ms);
2065
2066         return 0;
2067 }
2068
2069 static struct {
2070         int val, rate;
2071 } srs[] = {
2072         { 0,   8000 },
2073         { 1,  11025 },
2074         { 2,  12000 },
2075         { 3,  16000 },
2076         { 4,  22050 },
2077         { 5,  24000 },
2078         { 6,  32000 },
2079         { 7,  44100 },
2080         { 8,  48000 },
2081         { 9,  88200 },
2082         { 10, 96000 },
2083 };
2084
2085 static int fs_ratios[] = {
2086         64, 128, 192, 256, 348, 512, 768, 1024, 1408, 1536
2087 };
2088
2089 static int bclk_divs[] = {
2090         10, 15, 20, 30, 40, 50, 60, 80, 110, 120, 160, 220, 240, 320, 440, 480,
2091         640, 880, 960, 1280, 1760, 1920
2092 };
2093
2094 static int wm8994_hw_params(struct snd_pcm_substream *substream,
2095                             struct snd_pcm_hw_params *params,
2096                             struct snd_soc_dai *dai)
2097 {
2098         struct snd_soc_codec *codec = dai->codec;
2099         struct wm8994 *control = codec->control_data;
2100         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2101         int aif1_reg;
2102         int bclk_reg;
2103         int lrclk_reg;
2104         int rate_reg;
2105         int aif1 = 0;
2106         int bclk = 0;
2107         int lrclk = 0;
2108         int rate_val = 0;
2109         int id = dai->id - 1;
2110
2111         int i, cur_val, best_val, bclk_rate, best;
2112
2113         switch (dai->id) {
2114         case 1:
2115                 aif1_reg = WM8994_AIF1_CONTROL_1;
2116                 bclk_reg = WM8994_AIF1_BCLK;
2117                 rate_reg = WM8994_AIF1_RATE;
2118                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2119                     wm8994->lrclk_shared[0]) {
2120                         lrclk_reg = WM8994_AIF1DAC_LRCLK;
2121                 } else {
2122                         lrclk_reg = WM8994_AIF1ADC_LRCLK;
2123                         dev_dbg(codec->dev, "AIF1 using split LRCLK\n");
2124                 }
2125                 break;
2126         case 2:
2127                 aif1_reg = WM8994_AIF2_CONTROL_1;
2128                 bclk_reg = WM8994_AIF2_BCLK;
2129                 rate_reg = WM8994_AIF2_RATE;
2130                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
2131                     wm8994->lrclk_shared[1]) {
2132                         lrclk_reg = WM8994_AIF2DAC_LRCLK;
2133                 } else {
2134                         lrclk_reg = WM8994_AIF2ADC_LRCLK;
2135                         dev_dbg(codec->dev, "AIF2 using split LRCLK\n");
2136                 }
2137                 break;
2138         case 3:
2139                 switch (control->type) {
2140                 case WM8958:
2141                         aif1_reg = WM8958_AIF3_CONTROL_1;
2142                         break;
2143                 default:
2144                         return 0;
2145                 }
2146         default:
2147                 return -EINVAL;
2148         }
2149
2150         bclk_rate = params_rate(params) * 2;
2151         switch (params_format(params)) {
2152         case SNDRV_PCM_FORMAT_S16_LE:
2153                 bclk_rate *= 16;
2154                 break;
2155         case SNDRV_PCM_FORMAT_S20_3LE:
2156                 bclk_rate *= 20;
2157                 aif1 |= 0x20;
2158                 break;
2159         case SNDRV_PCM_FORMAT_S24_LE:
2160                 bclk_rate *= 24;
2161                 aif1 |= 0x40;
2162                 break;
2163         case SNDRV_PCM_FORMAT_S32_LE:
2164                 bclk_rate *= 32;
2165                 aif1 |= 0x60;
2166                 break;
2167         default:
2168                 return -EINVAL;
2169         }
2170
2171         /* Try to find an appropriate sample rate; look for an exact match. */
2172         for (i = 0; i < ARRAY_SIZE(srs); i++)
2173                 if (srs[i].rate == params_rate(params))
2174                         break;
2175         if (i == ARRAY_SIZE(srs))
2176                 return -EINVAL;
2177         rate_val |= srs[i].val << WM8994_AIF1_SR_SHIFT;
2178
2179         dev_dbg(dai->dev, "Sample rate is %dHz\n", srs[i].rate);
2180         dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n",
2181                 dai->id, wm8994->aifclk[id], bclk_rate);
2182
2183         if (wm8994->aifclk[id] == 0) {
2184                 dev_err(dai->dev, "AIF%dCLK not configured\n", dai->id);
2185                 return -EINVAL;
2186         }
2187
2188         /* AIFCLK/fs ratio; look for a close match in either direction */
2189         best = 0;
2190         best_val = abs((fs_ratios[0] * params_rate(params))
2191                        - wm8994->aifclk[id]);
2192         for (i = 1; i < ARRAY_SIZE(fs_ratios); i++) {
2193                 cur_val = abs((fs_ratios[i] * params_rate(params))
2194                               - wm8994->aifclk[id]);
2195                 if (cur_val >= best_val)
2196                         continue;
2197                 best = i;
2198                 best_val = cur_val;
2199         }
2200         dev_dbg(dai->dev, "Selected AIF%dCLK/fs = %d\n",
2201                 dai->id, fs_ratios[best]);
2202         rate_val |= best;
2203
2204         /* We may not get quite the right frequency if using
2205          * approximate clocks so look for the closest match that is
2206          * higher than the target (we need to ensure that there enough
2207          * BCLKs to clock out the samples).
2208          */
2209         best = 0;
2210         for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2211                 cur_val = (wm8994->aifclk[id] * 10 / bclk_divs[i]) - bclk_rate;
2212                 if (cur_val < 0) /* BCLK table is sorted */
2213                         break;
2214                 best = i;
2215         }
2216         bclk_rate = wm8994->aifclk[id] * 10 / bclk_divs[best];
2217         dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n",
2218                 bclk_divs[best], bclk_rate);
2219         bclk |= best << WM8994_AIF1_BCLK_DIV_SHIFT;
2220
2221         lrclk = bclk_rate / params_rate(params);
2222         dev_dbg(dai->dev, "Using LRCLK rate %d for actual LRCLK %dHz\n",
2223                 lrclk, bclk_rate / lrclk);
2224
2225         snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2226         snd_soc_update_bits(codec, bclk_reg, WM8994_AIF1_BCLK_DIV_MASK, bclk);
2227         snd_soc_update_bits(codec, lrclk_reg, WM8994_AIF1DAC_RATE_MASK,
2228                             lrclk);
2229         snd_soc_update_bits(codec, rate_reg, WM8994_AIF1_SR_MASK |
2230                             WM8994_AIF1CLK_RATE_MASK, rate_val);
2231
2232         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2233                 switch (dai->id) {
2234                 case 1:
2235                         wm8994->dac_rates[0] = params_rate(params);
2236                         wm8994_set_retune_mobile(codec, 0);
2237                         wm8994_set_retune_mobile(codec, 1);
2238                         break;
2239                 case 2:
2240                         wm8994->dac_rates[1] = params_rate(params);
2241                         wm8994_set_retune_mobile(codec, 2);
2242                         break;
2243                 }
2244         }
2245
2246         return 0;
2247 }
2248
2249 static int wm8994_aif3_hw_params(struct snd_pcm_substream *substream,
2250                                  struct snd_pcm_hw_params *params,
2251                                  struct snd_soc_dai *dai)
2252 {
2253         struct snd_soc_codec *codec = dai->codec;
2254         struct wm8994 *control = codec->control_data;
2255         int aif1_reg;
2256         int aif1 = 0;
2257
2258         switch (dai->id) {
2259         case 3:
2260                 switch (control->type) {
2261                 case WM8958:
2262                         aif1_reg = WM8958_AIF3_CONTROL_1;
2263                         break;
2264                 default:
2265                         return 0;
2266                 }
2267         default:
2268                 return 0;
2269         }
2270
2271         switch (params_format(params)) {
2272         case SNDRV_PCM_FORMAT_S16_LE:
2273                 break;
2274         case SNDRV_PCM_FORMAT_S20_3LE:
2275                 aif1 |= 0x20;
2276                 break;
2277         case SNDRV_PCM_FORMAT_S24_LE:
2278                 aif1 |= 0x40;
2279                 break;
2280         case SNDRV_PCM_FORMAT_S32_LE:
2281                 aif1 |= 0x60;
2282                 break;
2283         default:
2284                 return -EINVAL;
2285         }
2286
2287         return snd_soc_update_bits(codec, aif1_reg, WM8994_AIF1_WL_MASK, aif1);
2288 }
2289
2290 static int wm8994_aif_mute(struct snd_soc_dai *codec_dai, int mute)
2291 {
2292         struct snd_soc_codec *codec = codec_dai->codec;
2293         int mute_reg;
2294         int reg;
2295
2296         switch (codec_dai->id) {
2297         case 1:
2298                 mute_reg = WM8994_AIF1_DAC1_FILTERS_1;
2299                 break;
2300         case 2:
2301                 mute_reg = WM8994_AIF2_DAC_FILTERS_1;
2302                 break;
2303         default:
2304                 return -EINVAL;
2305         }
2306
2307         if (mute)
2308                 reg = WM8994_AIF1DAC1_MUTE;
2309         else
2310                 reg = 0;
2311
2312         snd_soc_update_bits(codec, mute_reg, WM8994_AIF1DAC1_MUTE, reg);
2313
2314         return 0;
2315 }
2316
2317 static int wm8994_set_tristate(struct snd_soc_dai *codec_dai, int tristate)
2318 {
2319         struct snd_soc_codec *codec = codec_dai->codec;
2320         int reg, val, mask;
2321
2322         switch (codec_dai->id) {
2323         case 1:
2324                 reg = WM8994_AIF1_MASTER_SLAVE;
2325                 mask = WM8994_AIF1_TRI;
2326                 break;
2327         case 2:
2328                 reg = WM8994_AIF2_MASTER_SLAVE;
2329                 mask = WM8994_AIF2_TRI;
2330                 break;
2331         case 3:
2332                 reg = WM8994_POWER_MANAGEMENT_6;
2333                 mask = WM8994_AIF3_TRI;
2334                 break;
2335         default:
2336                 return -EINVAL;
2337         }
2338
2339         if (tristate)
2340                 val = mask;
2341         else
2342                 val = 0;
2343
2344         return snd_soc_update_bits(codec, reg, mask, reg);
2345 }
2346
2347 #define WM8994_RATES SNDRV_PCM_RATE_8000_96000
2348
2349 #define WM8994_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2350                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2351
2352 static struct snd_soc_dai_ops wm8994_aif1_dai_ops = {
2353         .set_sysclk     = wm8994_set_dai_sysclk,
2354         .set_fmt        = wm8994_set_dai_fmt,
2355         .hw_params      = wm8994_hw_params,
2356         .digital_mute   = wm8994_aif_mute,
2357         .set_pll        = wm8994_set_fll,
2358         .set_tristate   = wm8994_set_tristate,
2359 };
2360
2361 static struct snd_soc_dai_ops wm8994_aif2_dai_ops = {
2362         .set_sysclk     = wm8994_set_dai_sysclk,
2363         .set_fmt        = wm8994_set_dai_fmt,
2364         .hw_params      = wm8994_hw_params,
2365         .digital_mute   = wm8994_aif_mute,
2366         .set_pll        = wm8994_set_fll,
2367         .set_tristate   = wm8994_set_tristate,
2368 };
2369
2370 static struct snd_soc_dai_ops wm8994_aif3_dai_ops = {
2371         .hw_params      = wm8994_aif3_hw_params,
2372         .set_tristate   = wm8994_set_tristate,
2373 };
2374
2375 static struct snd_soc_dai_driver wm8994_dai[] = {
2376         {
2377                 .name = "wm8994-aif1",
2378                 .id = 1,
2379                 .playback = {
2380                         .stream_name = "AIF1 Playback",
2381                         .channels_min = 2,
2382                         .channels_max = 2,
2383                         .rates = WM8994_RATES,
2384                         .formats = WM8994_FORMATS,
2385                 },
2386                 .capture = {
2387                         .stream_name = "AIF1 Capture",
2388                         .channels_min = 2,
2389                         .channels_max = 2,
2390                         .rates = WM8994_RATES,
2391                         .formats = WM8994_FORMATS,
2392                  },
2393                 .ops = &wm8994_aif1_dai_ops,
2394         },
2395         {
2396                 .name = "wm8994-aif2",
2397                 .id = 2,
2398                 .playback = {
2399                         .stream_name = "AIF2 Playback",
2400                         .channels_min = 2,
2401                         .channels_max = 2,
2402                         .rates = WM8994_RATES,
2403                         .formats = WM8994_FORMATS,
2404                 },
2405                 .capture = {
2406                         .stream_name = "AIF2 Capture",
2407                         .channels_min = 2,
2408                         .channels_max = 2,
2409                         .rates = WM8994_RATES,
2410                         .formats = WM8994_FORMATS,
2411                 },
2412                 .ops = &wm8994_aif2_dai_ops,
2413         },
2414         {
2415                 .name = "wm8994-aif3",
2416                 .id = 3,
2417                 .playback = {
2418                         .stream_name = "AIF3 Playback",
2419                         .channels_min = 2,
2420                         .channels_max = 2,
2421                         .rates = WM8994_RATES,
2422                         .formats = WM8994_FORMATS,
2423                 },
2424                 .capture = {
2425                         .stream_name = "AIF3 Capture",
2426                         .channels_min = 2,
2427                         .channels_max = 2,
2428                         .rates = WM8994_RATES,
2429                         .formats = WM8994_FORMATS,
2430                 },
2431                 .ops = &wm8994_aif3_dai_ops,
2432         }
2433 };
2434
2435 #ifdef CONFIG_PM
2436 static int wm8994_suspend(struct snd_soc_codec *codec, pm_message_t state)
2437 {
2438         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2439         int i, ret;
2440
2441         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2442                 memcpy(&wm8994->fll_suspend[i], &wm8994->fll[i],
2443                        sizeof(struct fll_config));
2444                 ret = _wm8994_set_fll(codec, i + 1, 0, 0, 0);
2445                 if (ret < 0)
2446                         dev_warn(codec->dev, "Failed to stop FLL%d: %d\n",
2447                                  i + 1, ret);
2448         }
2449
2450         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
2451
2452         return 0;
2453 }
2454
2455 static int wm8994_resume(struct snd_soc_codec *codec)
2456 {
2457         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2458         int i, ret;
2459
2460         /* Restore the registers */
2461         ret = snd_soc_cache_sync(codec);
2462         if (ret != 0)
2463                 dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
2464
2465         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2466
2467         for (i = 0; i < ARRAY_SIZE(wm8994->fll); i++) {
2468                 if (!wm8994->fll_suspend[i].out)
2469                         continue;
2470
2471                 ret = _wm8994_set_fll(codec, i + 1,
2472                                      wm8994->fll_suspend[i].src,
2473                                      wm8994->fll_suspend[i].in,
2474                                      wm8994->fll_suspend[i].out);
2475                 if (ret < 0)
2476                         dev_warn(codec->dev, "Failed to restore FLL%d: %d\n",
2477                                  i + 1, ret);
2478         }
2479
2480         return 0;
2481 }
2482 #else
2483 #define wm8994_suspend NULL
2484 #define wm8994_resume NULL
2485 #endif
2486
2487 static void wm8994_handle_retune_mobile_pdata(struct wm8994_priv *wm8994)
2488 {
2489         struct snd_soc_codec *codec = wm8994->codec;
2490         struct wm8994_pdata *pdata = wm8994->pdata;
2491         struct snd_kcontrol_new controls[] = {
2492                 SOC_ENUM_EXT("AIF1.1 EQ Mode",
2493                              wm8994->retune_mobile_enum,
2494                              wm8994_get_retune_mobile_enum,
2495                              wm8994_put_retune_mobile_enum),
2496                 SOC_ENUM_EXT("AIF1.2 EQ Mode",
2497                              wm8994->retune_mobile_enum,
2498                              wm8994_get_retune_mobile_enum,
2499                              wm8994_put_retune_mobile_enum),
2500                 SOC_ENUM_EXT("AIF2 EQ Mode",
2501                              wm8994->retune_mobile_enum,
2502                              wm8994_get_retune_mobile_enum,
2503                              wm8994_put_retune_mobile_enum),
2504         };
2505         int ret, i, j;
2506         const char **t;
2507
2508         /* We need an array of texts for the enum API but the number
2509          * of texts is likely to be less than the number of
2510          * configurations due to the sample rate dependency of the
2511          * configurations. */
2512         wm8994->num_retune_mobile_texts = 0;
2513         wm8994->retune_mobile_texts = NULL;
2514         for (i = 0; i < pdata->num_retune_mobile_cfgs; i++) {
2515                 for (j = 0; j < wm8994->num_retune_mobile_texts; j++) {
2516                         if (strcmp(pdata->retune_mobile_cfgs[i].name,
2517                                    wm8994->retune_mobile_texts[j]) == 0)
2518                                 break;
2519                 }
2520
2521                 if (j != wm8994->num_retune_mobile_texts)
2522                         continue;
2523
2524                 /* Expand the array... */
2525                 t = krealloc(wm8994->retune_mobile_texts,
2526                              sizeof(char *) *
2527                              (wm8994->num_retune_mobile_texts + 1),
2528                              GFP_KERNEL);
2529                 if (t == NULL)
2530                         continue;
2531
2532                 /* ...store the new entry... */
2533                 t[wm8994->num_retune_mobile_texts] =
2534                         pdata->retune_mobile_cfgs[i].name;
2535
2536                 /* ...and remember the new version. */
2537                 wm8994->num_retune_mobile_texts++;
2538                 wm8994->retune_mobile_texts = t;
2539         }
2540
2541         dev_dbg(codec->dev, "Allocated %d unique ReTune Mobile names\n",
2542                 wm8994->num_retune_mobile_texts);
2543
2544         wm8994->retune_mobile_enum.max = wm8994->num_retune_mobile_texts;
2545         wm8994->retune_mobile_enum.texts = wm8994->retune_mobile_texts;
2546
2547         ret = snd_soc_add_controls(wm8994->codec, controls,
2548                                    ARRAY_SIZE(controls));
2549         if (ret != 0)
2550                 dev_err(wm8994->codec->dev,
2551                         "Failed to add ReTune Mobile controls: %d\n", ret);
2552 }
2553
2554 static void wm8994_handle_pdata(struct wm8994_priv *wm8994)
2555 {
2556         struct snd_soc_codec *codec = wm8994->codec;
2557         struct wm8994_pdata *pdata = wm8994->pdata;
2558         int ret, i;
2559
2560         if (!pdata)
2561                 return;
2562
2563         wm_hubs_handle_analogue_pdata(codec, pdata->lineout1_diff,
2564                                       pdata->lineout2_diff,
2565                                       pdata->lineout1fb,
2566                                       pdata->lineout2fb,
2567                                       pdata->jd_scthr,
2568                                       pdata->jd_thr,
2569                                       pdata->micbias1_lvl,
2570                                       pdata->micbias2_lvl);
2571
2572         dev_dbg(codec->dev, "%d DRC configurations\n", pdata->num_drc_cfgs);
2573
2574         if (pdata->num_drc_cfgs) {
2575                 struct snd_kcontrol_new controls[] = {
2576                         SOC_ENUM_EXT("AIF1DRC1 Mode", wm8994->drc_enum,
2577                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2578                         SOC_ENUM_EXT("AIF1DRC2 Mode", wm8994->drc_enum,
2579                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2580                         SOC_ENUM_EXT("AIF2DRC Mode", wm8994->drc_enum,
2581                                      wm8994_get_drc_enum, wm8994_put_drc_enum),
2582                 };
2583
2584                 /* We need an array of texts for the enum API */
2585                 wm8994->drc_texts = kmalloc(sizeof(char *)
2586                                             * pdata->num_drc_cfgs, GFP_KERNEL);
2587                 if (!wm8994->drc_texts) {
2588                         dev_err(wm8994->codec->dev,
2589                                 "Failed to allocate %d DRC config texts\n",
2590                                 pdata->num_drc_cfgs);
2591                         return;
2592                 }
2593
2594                 for (i = 0; i < pdata->num_drc_cfgs; i++)
2595                         wm8994->drc_texts[i] = pdata->drc_cfgs[i].name;
2596
2597                 wm8994->drc_enum.max = pdata->num_drc_cfgs;
2598                 wm8994->drc_enum.texts = wm8994->drc_texts;
2599
2600                 ret = snd_soc_add_controls(wm8994->codec, controls,
2601                                            ARRAY_SIZE(controls));
2602                 if (ret != 0)
2603                         dev_err(wm8994->codec->dev,
2604                                 "Failed to add DRC mode controls: %d\n", ret);
2605
2606                 for (i = 0; i < WM8994_NUM_DRC; i++)
2607                         wm8994_set_drc(codec, i);
2608         }
2609
2610         dev_dbg(codec->dev, "%d ReTune Mobile configurations\n",
2611                 pdata->num_retune_mobile_cfgs);
2612
2613         if (pdata->num_mbc_cfgs) {
2614                 struct snd_kcontrol_new control[] = {
2615                         SOC_ENUM_EXT("MBC Mode", wm8994->mbc_enum,
2616                                      wm8958_get_mbc_enum, wm8958_put_mbc_enum),
2617                 };
2618
2619                 /* We need an array of texts for the enum API */
2620                 wm8994->mbc_texts = kmalloc(sizeof(char *)
2621                                             * pdata->num_mbc_cfgs, GFP_KERNEL);
2622                 if (!wm8994->mbc_texts) {
2623                         dev_err(wm8994->codec->dev,
2624                                 "Failed to allocate %d MBC config texts\n",
2625                                 pdata->num_mbc_cfgs);
2626                         return;
2627                 }
2628
2629                 for (i = 0; i < pdata->num_mbc_cfgs; i++)
2630                         wm8994->mbc_texts[i] = pdata->mbc_cfgs[i].name;
2631
2632                 wm8994->mbc_enum.max = pdata->num_mbc_cfgs;
2633                 wm8994->mbc_enum.texts = wm8994->mbc_texts;
2634
2635                 ret = snd_soc_add_controls(wm8994->codec, control, 1);
2636                 if (ret != 0)
2637                         dev_err(wm8994->codec->dev,
2638                                 "Failed to add MBC mode controls: %d\n", ret);
2639         }
2640
2641         if (pdata->num_retune_mobile_cfgs)
2642                 wm8994_handle_retune_mobile_pdata(wm8994);
2643         else
2644                 snd_soc_add_controls(wm8994->codec, wm8994_eq_controls,
2645                                      ARRAY_SIZE(wm8994_eq_controls));
2646 }
2647
2648 /**
2649  * wm8994_mic_detect - Enable microphone detection via the WM8994 IRQ
2650  *
2651  * @codec:   WM8994 codec
2652  * @jack:    jack to report detection events on
2653  * @micbias: microphone bias to detect on
2654  * @det:     value to report for presence detection
2655  * @shrt:    value to report for short detection
2656  *
2657  * Enable microphone detection via IRQ on the WM8994.  If GPIOs are
2658  * being used to bring out signals to the processor then only platform
2659  * data configuration is needed for WM8994 and processor GPIOs should
2660  * be configured using snd_soc_jack_add_gpios() instead.
2661  *
2662  * Configuration of detection levels is available via the micbias1_lvl
2663  * and micbias2_lvl platform data members.
2664  */
2665 int wm8994_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2666                       int micbias, int det, int shrt)
2667 {
2668         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2669         struct wm8994_micdet *micdet;
2670         struct wm8994 *control = codec->control_data;
2671         int reg;
2672
2673         if (control->type != WM8994)
2674                 return -EINVAL;
2675
2676         switch (micbias) {
2677         case 1:
2678                 micdet = &wm8994->micdet[0];
2679                 break;
2680         case 2:
2681                 micdet = &wm8994->micdet[1];
2682                 break;
2683         default:
2684                 return -EINVAL;
2685         }
2686
2687         dev_dbg(codec->dev, "Configuring microphone detection on %d: %x %x\n",
2688                 micbias, det, shrt);
2689
2690         /* Store the configuration */
2691         micdet->jack = jack;
2692         micdet->det = det;
2693         micdet->shrt = shrt;
2694
2695         /* If either of the jacks is set up then enable detection */
2696         if (wm8994->micdet[0].jack || wm8994->micdet[1].jack)
2697                 reg = WM8994_MICD_ENA;
2698         else
2699                 reg = 0;
2700
2701         snd_soc_update_bits(codec, WM8994_MICBIAS, WM8994_MICD_ENA, reg);
2702
2703         return 0;
2704 }
2705 EXPORT_SYMBOL_GPL(wm8994_mic_detect);
2706
2707 static irqreturn_t wm8994_mic_irq(int irq, void *data)
2708 {
2709         struct wm8994_priv *priv = data;
2710         struct snd_soc_codec *codec = priv->codec;
2711         int reg;
2712         int report;
2713
2714         reg = snd_soc_read(codec, WM8994_INTERRUPT_RAW_STATUS_2);
2715         if (reg < 0) {
2716                 dev_err(codec->dev, "Failed to read microphone status: %d\n",
2717                         reg);
2718                 return IRQ_HANDLED;
2719         }
2720
2721         dev_dbg(codec->dev, "Microphone status: %x\n", reg);
2722
2723         report = 0;
2724         if (reg & WM8994_MIC1_DET_STS)
2725                 report |= priv->micdet[0].det;
2726         if (reg & WM8994_MIC1_SHRT_STS)
2727                 report |= priv->micdet[0].shrt;
2728         snd_soc_jack_report(priv->micdet[0].jack, report,
2729                             priv->micdet[0].det | priv->micdet[0].shrt);
2730
2731         report = 0;
2732         if (reg & WM8994_MIC2_DET_STS)
2733                 report |= priv->micdet[1].det;
2734         if (reg & WM8994_MIC2_SHRT_STS)
2735                 report |= priv->micdet[1].shrt;
2736         snd_soc_jack_report(priv->micdet[1].jack, report,
2737                             priv->micdet[1].det | priv->micdet[1].shrt);
2738
2739         return IRQ_HANDLED;
2740 }
2741
2742 /* Default microphone detection handler for WM8958 - the user can
2743  * override this if they wish.
2744  */
2745 static void wm8958_default_micdet(u16 status, void *data)
2746 {
2747         struct snd_soc_codec *codec = data;
2748         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2749         int report = 0;
2750
2751         /* If nothing present then clear our statuses */
2752         if (!(status & WM8958_MICD_STS)) {
2753                 wm8994->jack_is_video = false;
2754                 wm8994->jack_is_mic = false;
2755                 goto done;
2756         }
2757
2758         /* Assume anything over 475 ohms is a microphone and remember
2759          * that we've seen one (since buttons override it) */
2760         if (status & 0x600)
2761                 wm8994->jack_is_mic = true;
2762         if (wm8994->jack_is_mic)
2763                 report |= SND_JACK_MICROPHONE;
2764
2765         /* Video has an impedence of approximately 75 ohms; assume
2766          * this isn't used as a button and remember it since buttons
2767          * override it. */
2768         if (status & 0x40)
2769                 wm8994->jack_is_video = true;
2770         if (wm8994->jack_is_video)
2771                 report |= SND_JACK_VIDEOOUT;
2772
2773         /* Everything else is buttons; just assign slots */
2774         if (status & 0x4)
2775                 report |= SND_JACK_BTN_0;
2776         if (status & 0x8)
2777                 report |= SND_JACK_BTN_1;
2778         if (status & 0x10)
2779                 report |= SND_JACK_BTN_2;
2780         if (status & 0x20)
2781                 report |= SND_JACK_BTN_3;
2782         if (status & 0x80)
2783                 report |= SND_JACK_BTN_4;
2784         if (status & 0x100)
2785                 report |= SND_JACK_BTN_5;
2786
2787 done:
2788         snd_soc_jack_report(wm8994->micdet[0].jack,
2789                             SND_JACK_BTN_0 | SND_JACK_BTN_1 | SND_JACK_BTN_2 |
2790                             SND_JACK_BTN_3 | SND_JACK_BTN_4 | SND_JACK_BTN_5 |
2791                             SND_JACK_MICROPHONE | SND_JACK_VIDEOOUT,
2792                             report);
2793 }
2794
2795 /**
2796  * wm8958_mic_detect - Enable microphone detection via the WM8958 IRQ
2797  *
2798  * @codec:   WM8958 codec
2799  * @jack:    jack to report detection events on
2800  *
2801  * Enable microphone detection functionality for the WM8958.  By
2802  * default simple detection which supports the detection of up to 6
2803  * buttons plus video and microphone functionality is supported.
2804  *
2805  * The WM8958 has an advanced jack detection facility which is able to
2806  * support complex accessory detection, especially when used in
2807  * conjunction with external circuitry.  In order to provide maximum
2808  * flexiblity a callback is provided which allows a completely custom
2809  * detection algorithm.
2810  */
2811 int wm8958_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack,
2812                       wm8958_micdet_cb cb, void *cb_data)
2813 {
2814         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
2815         struct wm8994 *control = codec->control_data;
2816
2817         if (control->type != WM8958)
2818                 return -EINVAL;
2819
2820         if (jack) {
2821                 if (!cb) {
2822                         dev_dbg(codec->dev, "Using default micdet callback\n");
2823                         cb = wm8958_default_micdet;
2824                         cb_data = codec;
2825                 }
2826
2827                 wm8994->micdet[0].jack = jack;
2828                 wm8994->jack_cb = cb;
2829                 wm8994->jack_cb_data = cb_data;
2830
2831                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2832                                     WM8958_MICD_ENA, WM8958_MICD_ENA);
2833         } else {
2834                 snd_soc_update_bits(codec, WM8958_MIC_DETECT_1,
2835                                     WM8958_MICD_ENA, 0);
2836         }
2837
2838         return 0;
2839 }
2840 EXPORT_SYMBOL_GPL(wm8958_mic_detect);
2841
2842 static irqreturn_t wm8958_mic_irq(int irq, void *data)
2843 {
2844         struct wm8994_priv *wm8994 = data;
2845         struct snd_soc_codec *codec = wm8994->codec;
2846         int reg;
2847
2848         reg = snd_soc_read(codec, WM8958_MIC_DETECT_3);
2849         if (reg < 0) {
2850                 dev_err(codec->dev, "Failed to read mic detect status: %d\n",
2851                         reg);
2852                 return IRQ_NONE;
2853         }
2854
2855         if (!(reg & WM8958_MICD_VALID)) {
2856                 dev_dbg(codec->dev, "Mic detect data not valid\n");
2857                 goto out;
2858         }
2859
2860         if (wm8994->jack_cb)
2861                 wm8994->jack_cb(reg, wm8994->jack_cb_data);
2862         else
2863                 dev_warn(codec->dev, "Accessory detection with no callback\n");
2864
2865 out:
2866         return IRQ_HANDLED;
2867 }
2868
2869 static int wm8994_codec_probe(struct snd_soc_codec *codec)
2870 {
2871         struct wm8994 *control;
2872         struct wm8994_priv *wm8994;
2873         struct snd_soc_dapm_context *dapm = &codec->dapm;
2874         int ret, i;
2875
2876         codec->control_data = dev_get_drvdata(codec->dev->parent);
2877         control = codec->control_data;
2878
2879         wm8994 = kzalloc(sizeof(struct wm8994_priv), GFP_KERNEL);
2880         if (wm8994 == NULL)
2881                 return -ENOMEM;
2882         snd_soc_codec_set_drvdata(codec, wm8994);
2883
2884         wm8994->pdata = dev_get_platdata(codec->dev->parent);
2885         wm8994->codec = codec;
2886
2887         pm_runtime_enable(codec->dev);
2888         pm_runtime_resume(codec->dev);
2889
2890         /* Read our current status back from the chip - we don't want to
2891          * reset as this may interfere with the GPIO or LDO operation. */
2892         for (i = 0; i < WM8994_CACHE_SIZE; i++) {
2893                 if (!wm8994_readable(i) || wm8994_volatile(i))
2894                         continue;
2895
2896                 ret = wm8994_reg_read(codec->control_data, i);
2897                 if (ret <= 0)
2898                         continue;
2899
2900                 ret = snd_soc_cache_write(codec, i, ret);
2901                 if (ret != 0) {
2902                         dev_err(codec->dev,
2903                                 "Failed to initialise cache for 0x%x: %d\n",
2904                                 i, ret);
2905                         goto err;
2906                 }
2907         }
2908
2909         /* Set revision-specific configuration */
2910         wm8994->revision = snd_soc_read(codec, WM8994_CHIP_REVISION);
2911         switch (control->type) {
2912         case WM8994:
2913                 switch (wm8994->revision) {
2914                 case 2:
2915                 case 3:
2916                         wm8994->hubs.dcs_codes = -5;
2917                         wm8994->hubs.hp_startup_mode = 1;
2918                         wm8994->hubs.dcs_readback_mode = 1;
2919                         break;
2920                 default:
2921                         wm8994->hubs.dcs_readback_mode = 1;
2922                         break;
2923                 }
2924
2925         case WM8958:
2926                 wm8994->hubs.dcs_readback_mode = 1;
2927                 break;
2928
2929         default:
2930                 break;
2931         }
2932
2933         switch (control->type) {
2934         case WM8994:
2935                 ret = wm8994_request_irq(codec->control_data,
2936                                          WM8994_IRQ_MIC1_DET,
2937                                          wm8994_mic_irq, "Mic 1 detect",
2938                                          wm8994);
2939                 if (ret != 0)
2940                         dev_warn(codec->dev,
2941                                  "Failed to request Mic1 detect IRQ: %d\n",
2942                                  ret);
2943
2944                 ret = wm8994_request_irq(codec->control_data,
2945                                          WM8994_IRQ_MIC1_SHRT,
2946                                          wm8994_mic_irq, "Mic 1 short",
2947                                          wm8994);
2948                 if (ret != 0)
2949                         dev_warn(codec->dev,
2950                                  "Failed to request Mic1 short IRQ: %d\n",
2951                                  ret);
2952
2953                 ret = wm8994_request_irq(codec->control_data,
2954                                          WM8994_IRQ_MIC2_DET,
2955                                          wm8994_mic_irq, "Mic 2 detect",
2956                                          wm8994);
2957                 if (ret != 0)
2958                         dev_warn(codec->dev,
2959                                  "Failed to request Mic2 detect IRQ: %d\n",
2960                                  ret);
2961
2962                 ret = wm8994_request_irq(codec->control_data,
2963                                          WM8994_IRQ_MIC2_SHRT,
2964                                          wm8994_mic_irq, "Mic 2 short",
2965                                          wm8994);
2966                 if (ret != 0)
2967                         dev_warn(codec->dev,
2968                                  "Failed to request Mic2 short IRQ: %d\n",
2969                                  ret);
2970                 break;
2971
2972         case WM8958:
2973                 ret = wm8994_request_irq(codec->control_data,
2974                                          WM8994_IRQ_MIC1_DET,
2975                                          wm8958_mic_irq, "Mic detect",
2976                                          wm8994);
2977                 if (ret != 0)
2978                         dev_warn(codec->dev,
2979                                  "Failed to request Mic detect IRQ: %d\n",
2980                                  ret);
2981                 break;
2982         }
2983
2984         /* Remember if AIFnLRCLK is configured as a GPIO.  This should be
2985          * configured on init - if a system wants to do this dynamically
2986          * at runtime we can deal with that then.
2987          */
2988         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_1);
2989         if (ret < 0) {
2990                 dev_err(codec->dev, "Failed to read GPIO1 state: %d\n", ret);
2991                 goto err_irq;
2992         }
2993         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
2994                 wm8994->lrclk_shared[0] = 1;
2995                 wm8994_dai[0].symmetric_rates = 1;
2996         } else {
2997                 wm8994->lrclk_shared[0] = 0;
2998         }
2999
3000         ret = wm8994_reg_read(codec->control_data, WM8994_GPIO_6);
3001         if (ret < 0) {
3002                 dev_err(codec->dev, "Failed to read GPIO6 state: %d\n", ret);
3003                 goto err_irq;
3004         }
3005         if ((ret & WM8994_GPN_FN_MASK) != WM8994_GP_FN_PIN_SPECIFIC) {
3006                 wm8994->lrclk_shared[1] = 1;
3007                 wm8994_dai[1].symmetric_rates = 1;
3008         } else {
3009                 wm8994->lrclk_shared[1] = 0;
3010         }
3011
3012         wm8994_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
3013
3014         /* Latch volume updates (right only; we always do left then right). */
3015         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_RIGHT_VOLUME,
3016                             WM8994_AIF1DAC1_VU, WM8994_AIF1DAC1_VU);
3017         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_RIGHT_VOLUME,
3018                             WM8994_AIF1DAC2_VU, WM8994_AIF1DAC2_VU);
3019         snd_soc_update_bits(codec, WM8994_AIF2_DAC_RIGHT_VOLUME,
3020                             WM8994_AIF2DAC_VU, WM8994_AIF2DAC_VU);
3021         snd_soc_update_bits(codec, WM8994_AIF1_ADC1_RIGHT_VOLUME,
3022                             WM8994_AIF1ADC1_VU, WM8994_AIF1ADC1_VU);
3023         snd_soc_update_bits(codec, WM8994_AIF1_ADC2_RIGHT_VOLUME,
3024                             WM8994_AIF1ADC2_VU, WM8994_AIF1ADC2_VU);
3025         snd_soc_update_bits(codec, WM8994_AIF2_ADC_RIGHT_VOLUME,
3026                             WM8994_AIF2ADC_VU, WM8994_AIF1ADC2_VU);
3027         snd_soc_update_bits(codec, WM8994_DAC1_RIGHT_VOLUME,
3028                             WM8994_DAC1_VU, WM8994_DAC1_VU);
3029         snd_soc_update_bits(codec, WM8994_DAC2_RIGHT_VOLUME,
3030                             WM8994_DAC2_VU, WM8994_DAC2_VU);
3031
3032         /* Set the low bit of the 3D stereo depth so TLV matches */
3033         snd_soc_update_bits(codec, WM8994_AIF1_DAC1_FILTERS_2,
3034                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT,
3035                             1 << WM8994_AIF1DAC1_3D_GAIN_SHIFT);
3036         snd_soc_update_bits(codec, WM8994_AIF1_DAC2_FILTERS_2,
3037                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT,
3038                             1 << WM8994_AIF1DAC2_3D_GAIN_SHIFT);
3039         snd_soc_update_bits(codec, WM8994_AIF2_DAC_FILTERS_2,
3040                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT,
3041                             1 << WM8994_AIF2DAC_3D_GAIN_SHIFT);
3042
3043         /* Unconditionally enable AIF1 ADC TDM mode; it only affects
3044          * behaviour on idle TDM clock cycles. */
3045         snd_soc_update_bits(codec, WM8994_AIF1_CONTROL_1,
3046                             WM8994_AIF1ADC_TDM, WM8994_AIF1ADC_TDM);
3047
3048         wm8994_update_class_w(codec);
3049
3050         wm8994_handle_pdata(wm8994);
3051
3052         wm_hubs_add_analogue_controls(codec);
3053         snd_soc_add_controls(codec, wm8994_snd_controls,
3054                              ARRAY_SIZE(wm8994_snd_controls));
3055         snd_soc_dapm_new_controls(dapm, wm8994_dapm_widgets,
3056                                   ARRAY_SIZE(wm8994_dapm_widgets));
3057
3058         switch (control->type) {
3059         case WM8994:
3060                 snd_soc_dapm_new_controls(dapm, wm8994_specific_dapm_widgets,
3061                                           ARRAY_SIZE(wm8994_specific_dapm_widgets));
3062                 break;
3063         case WM8958:
3064                 snd_soc_add_controls(codec, wm8958_snd_controls,
3065                                      ARRAY_SIZE(wm8958_snd_controls));
3066                 snd_soc_dapm_new_controls(dapm, wm8958_dapm_widgets,
3067                                           ARRAY_SIZE(wm8958_dapm_widgets));
3068                 break;
3069         }
3070
3071
3072         wm_hubs_add_analogue_routes(codec, 0, 0);
3073         snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
3074
3075         switch (control->type) {
3076         case WM8994:
3077                 snd_soc_dapm_add_routes(dapm, wm8994_intercon,
3078                                         ARRAY_SIZE(wm8994_intercon));
3079                 break;
3080         case WM8958:
3081                 snd_soc_dapm_add_routes(dapm, wm8958_intercon,
3082                                         ARRAY_SIZE(wm8958_intercon));
3083                 break;
3084         }
3085
3086         return 0;
3087
3088 err_irq:
3089         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT, wm8994);
3090         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET, wm8994);
3091         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT, wm8994);
3092         wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET, wm8994);
3093 err:
3094         kfree(wm8994);
3095         return ret;
3096 }
3097
3098 static int  wm8994_codec_remove(struct snd_soc_codec *codec)
3099 {
3100         struct wm8994_priv *wm8994 = snd_soc_codec_get_drvdata(codec);
3101         struct wm8994 *control = codec->control_data;
3102
3103         wm8994_set_bias_level(codec, SND_SOC_BIAS_OFF);
3104
3105         pm_runtime_disable(codec->dev);
3106
3107         switch (control->type) {
3108         case WM8994:
3109                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_SHRT,
3110                                 wm8994);
3111                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC2_DET,
3112                                 wm8994);
3113                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_SHRT,
3114                                 wm8994);
3115                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3116                                 wm8994);
3117                 break;
3118
3119         case WM8958:
3120                 wm8994_free_irq(codec->control_data, WM8994_IRQ_MIC1_DET,
3121                                 wm8994);
3122                 break;
3123         }
3124         kfree(wm8994->retune_mobile_texts);
3125         kfree(wm8994->drc_texts);
3126         kfree(wm8994);
3127
3128         return 0;
3129 }
3130
3131 static struct snd_soc_codec_driver soc_codec_dev_wm8994 = {
3132         .probe =        wm8994_codec_probe,
3133         .remove =       wm8994_codec_remove,
3134         .suspend =      wm8994_suspend,
3135         .resume =       wm8994_resume,
3136         .read =         wm8994_read,
3137         .write =        wm8994_write,
3138         .readable_register = wm8994_readable,
3139         .volatile_register = wm8994_volatile,
3140         .set_bias_level = wm8994_set_bias_level,
3141
3142         .reg_cache_size = WM8994_CACHE_SIZE,
3143         .reg_cache_default = wm8994_reg_defaults,
3144         .reg_word_size = 2,
3145         .compress_type = SND_SOC_RBTREE_COMPRESSION,
3146 };
3147
3148 static int __devinit wm8994_probe(struct platform_device *pdev)
3149 {
3150         return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8994,
3151                         wm8994_dai, ARRAY_SIZE(wm8994_dai));
3152 }
3153
3154 static int __devexit wm8994_remove(struct platform_device *pdev)
3155 {
3156         snd_soc_unregister_codec(&pdev->dev);
3157         return 0;
3158 }
3159
3160 static struct platform_driver wm8994_codec_driver = {
3161         .driver = {
3162                    .name = "wm8994-codec",
3163                    .owner = THIS_MODULE,
3164                    },
3165         .probe = wm8994_probe,
3166         .remove = __devexit_p(wm8994_remove),
3167 };
3168
3169 static __init int wm8994_init(void)
3170 {
3171         return platform_driver_register(&wm8994_codec_driver);
3172 }
3173 module_init(wm8994_init);
3174
3175 static __exit void wm8994_exit(void)
3176 {
3177         platform_driver_unregister(&wm8994_codec_driver);
3178 }
3179 module_exit(wm8994_exit);
3180
3181
3182 MODULE_DESCRIPTION("ASoC WM8994 driver");
3183 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3184 MODULE_LICENSE("GPL");
3185 MODULE_ALIAS("platform:wm8994-codec");