sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <linux/delay.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/kernel.h>
  40 #include <linux/module.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/moduleparam.h>
  43 #include <linux/init.h>
  44 #include <linux/slab.h>
  45 #include <linux/pci.h>
  46 #include <linux/mutex.h>
  47 #include <linux/reboot.h>
  48 #include <linux/io.h>
  49 #ifdef CONFIG_X86
  50 /* for snoop control */
  51 #include <asm/pgtable.h>
  52 #include <asm/cacheflush.h>
  53 #endif
  54 #include <sound/core.h>
  55 #include <sound/initval.h>
  56 #include "hda_codec.h"
  57
  58
  59 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  60 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  61 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  62 static char *model[SNDRV_CARDS];
  63 static int position_fix[SNDRV_CARDS];
  64 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  65 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  66 static int probe_only[SNDRV_CARDS];
  67 static int single_cmd;
  68 static int enable_msi = -1;
  69 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  70 static char *patch[SNDRV_CARDS];
  71 #endif
  72 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  73 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  74                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  75 #endif
  76
  77 module_param_array(index, int, NULL, 0444);
  78 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  79 module_param_array(id, charp, NULL, 0444);
  80 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  81 module_param_array(enable, bool, NULL, 0444);
  82 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  83 module_param_array(model, charp, NULL, 0444);
  84 MODULE_PARM_DESC(model, "Use the given board model.");
  85 module_param_array(position_fix, int, NULL, 0444);
  86 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
  87                  "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
  88 module_param_array(bdl_pos_adj, int, NULL, 0644);
  89 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  90 module_param_array(probe_mask, int, NULL, 0444);
  91 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  92 module_param_array(probe_only, int, NULL, 0444);
  93 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  94 module_param(single_cmd, bool, 0444);
  95 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  96                  "(for debugging only).");
  97 module_param(enable_msi, int, 0444);
  98 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  99 #ifdef CONFIG_SND_HDA_PATCH_LOADER
 100 module_param_array(patch, charp, NULL, 0444);
 101 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
 102 #endif
 103 #ifdef CONFIG_SND_HDA_INPUT_BEEP
 104 module_param_array(beep_mode, int, NULL, 0444);
 105 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 106                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 107 #endif
 108
 109 #ifdef CONFIG_SND_HDA_POWER_SAVE
 110 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 111 module_param(power_save, int, 0644);
 112 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 113                  "(in second, 0 = disable).");
 114
 115 /* reset the HD-audio controller in power save mode.
 116  * this may give more power-saving, but will take longer time to
 117  * wake up.
 118  */
 119 static int power_save_controller = 1;
 120 module_param(power_save_controller, bool, 0644);
 121 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 122 #endif
 123
 124 static int align_buffer_size = 1;
 125 module_param(align_buffer_size, bool, 0644);
 126 MODULE_PARM_DESC(align_buffer_size,
 127                 "Force buffer and period sizes to be multiple of 128 bytes.");
 128
 129 #ifdef CONFIG_X86
 130 static bool hda_snoop = true;
 131 module_param_named(snoop, hda_snoop, bool, 0444);
 132 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
 133 #define azx_snoop(chip)         (chip)->snoop
 134 #else
 135 #define hda_snoop               true
 136 #define azx_snoop(chip)         true
 137 #endif
 138
 139
 140 MODULE_LICENSE("GPL");
 141 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 142                          "{Intel, ICH6M},"
 143                          "{Intel, ICH7},"
 144                          "{Intel, ESB2},"
 145                          "{Intel, ICH8},"
 146                          "{Intel, ICH9},"
 147                          "{Intel, ICH10},"
 148                          "{Intel, PCH},"
 149                          "{Intel, CPT},"
 150                          "{Intel, PPT},"
 151                          "{Intel, LPT},"
 152                          "{Intel, PBG},"
 153                          "{Intel, SCH},"
 154                          "{ATI, SB450},"
 155                          "{ATI, SB600},"
 156                          "{ATI, RS600},"
 157                          "{ATI, RS690},"
 158                          "{ATI, RS780},"
 159                          "{ATI, R600},"
 160                          "{ATI, RV630},"
 161                          "{ATI, RV610},"
 162                          "{ATI, RV670},"
 163                          "{ATI, RV635},"
 164                          "{ATI, RV620},"
 165                          "{ATI, RV770},"
 166                          "{VIA, VT8251},"
 167                          "{VIA, VT8237A},"
 168                          "{SiS, SIS966},"
 169                          "{ULI, M5461}}");
 170 MODULE_DESCRIPTION("Intel HDA driver");
 171
 172 #ifdef CONFIG_SND_VERBOSE_PRINTK
 173 #define SFX     /* nop */
 174 #else
 175 #define SFX     "hda-intel: "
 176 #endif
 177
 178 /*
 179  * registers
 180  */
 181 #define ICH6_REG_GCAP                   0x00
 182 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 183 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 184 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 185 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 186 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 187 #define ICH6_REG_VMIN                   0x02
 188 #define ICH6_REG_VMAJ                   0x03
 189 #define ICH6_REG_OUTPAY                 0x04
 190 #define ICH6_REG_INPAY                  0x06
 191 #define ICH6_REG_GCTL                   0x08
 192 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 193 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 194 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 195 #define ICH6_REG_WAKEEN                 0x0c
 196 #define ICH6_REG_STATESTS               0x0e
 197 #define ICH6_REG_GSTS                   0x10
 198 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 199 #define ICH6_REG_INTCTL                 0x20
 200 #define ICH6_REG_INTSTS                 0x24
 201 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
 202 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
 203 #define ICH6_REG_SSYNC                  0x38
 204 #define ICH6_REG_CORBLBASE              0x40
 205 #define ICH6_REG_CORBUBASE              0x44
 206 #define ICH6_REG_CORBWP                 0x48
 207 #define ICH6_REG_CORBRP                 0x4a
 208 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 209 #define ICH6_REG_CORBCTL                0x4c
 210 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 211 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 212 #define ICH6_REG_CORBSTS                0x4d
 213 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 214 #define ICH6_REG_CORBSIZE               0x4e
 215
 216 #define ICH6_REG_RIRBLBASE              0x50
 217 #define ICH6_REG_RIRBUBASE              0x54
 218 #define ICH6_REG_RIRBWP                 0x58
 219 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 220 #define ICH6_REG_RINTCNT                0x5a
 221 #define ICH6_REG_RIRBCTL                0x5c
 222 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 223 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 224 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 225 #define ICH6_REG_RIRBSTS                0x5d
 226 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 227 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 228 #define ICH6_REG_RIRBSIZE               0x5e
 229
 230 #define ICH6_REG_IC                     0x60
 231 #define ICH6_REG_IR                     0x64
 232 #define ICH6_REG_IRS                    0x68
 233 #define   ICH6_IRS_VALID        (1<<1)
 234 #define   ICH6_IRS_BUSY         (1<<0)
 235
 236 #define ICH6_REG_DPLBASE                0x70
 237 #define ICH6_REG_DPUBASE                0x74
 238 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 239
 240 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 241 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 242
 243 /* stream register offsets from stream base */
 244 #define ICH6_REG_SD_CTL                 0x00
 245 #define ICH6_REG_SD_STS                 0x03
 246 #define ICH6_REG_SD_LPIB                0x04
 247 #define ICH6_REG_SD_CBL                 0x08
 248 #define ICH6_REG_SD_LVI                 0x0c
 249 #define ICH6_REG_SD_FIFOW               0x0e
 250 #define ICH6_REG_SD_FIFOSIZE            0x10
 251 #define ICH6_REG_SD_FORMAT              0x12
 252 #define ICH6_REG_SD_BDLPL               0x18
 253 #define ICH6_REG_SD_BDLPU               0x1c
 254
 255 /* PCI space */
 256 #define ICH6_PCIREG_TCSEL       0x44
 257
 258 /*
 259  * other constants
 260  */
 261
 262 /* max number of SDs */
 263 /* ICH, ATI and VIA have 4 playback and 4 capture */
 264 #define ICH6_NUM_CAPTURE        4
 265 #define ICH6_NUM_PLAYBACK       4
 266
 267 /* ULI has 6 playback and 5 capture */
 268 #define ULI_NUM_CAPTURE         5
 269 #define ULI_NUM_PLAYBACK        6
 270
 271 /* ATI HDMI has 1 playback and 0 capture */
 272 #define ATIHDMI_NUM_CAPTURE     0
 273 #define ATIHDMI_NUM_PLAYBACK    1
 274
 275 /* TERA has 4 playback and 3 capture */
 276 #define TERA_NUM_CAPTURE        3
 277 #define TERA_NUM_PLAYBACK       4
 278
 279 /* this number is statically defined for simplicity */
 280 #define MAX_AZX_DEV             16
 281
 282 /* max number of fragments - we may use more if allocating more pages for BDL */
 283 #define BDL_SIZE                4096
 284 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 285 #define AZX_MAX_FRAG            32
 286 /* max buffer size - no h/w limit, you can increase as you like */
 287 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 288
 289 /* RIRB int mask: overrun[2], response[0] */
 290 #define RIRB_INT_RESPONSE       0x01
 291 #define RIRB_INT_OVERRUN        0x04
 292 #define RIRB_INT_MASK           0x05
 293
 294 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 295 #define AZX_MAX_CODECS          8
 296 #define AZX_DEFAULT_CODECS      4
 297 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 298
 299 /* SD_CTL bits */
 300 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 301 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 302 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 303 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 304 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 305 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 306 #define SD_CTL_STREAM_TAG_SHIFT 20
 307
 308 /* SD_CTL and SD_STS */
 309 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 310 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 311 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 312 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 313                                  SD_INT_COMPLETE)
 314
 315 /* SD_STS */
 316 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 317
 318 /* INTCTL and INTSTS */
 319 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 320 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 321 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 322
 323 /* below are so far hardcoded - should read registers in future */
 324 #define ICH6_MAX_CORB_ENTRIES   256
 325 #define ICH6_MAX_RIRB_ENTRIES   256
 326
 327 /* position fix mode */
 328 enum {
 329         POS_FIX_AUTO,
 330         POS_FIX_LPIB,
 331         POS_FIX_POSBUF,
 332         POS_FIX_VIACOMBO,
 333 };
 334
 335 /* Defines for ATI HD Audio support in SB450 south bridge */
 336 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 337 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 338
 339 /* Defines for Nvidia HDA support */
 340 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 341 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 342 #define NVIDIA_HDA_ISTRM_COH          0x4d
 343 #define NVIDIA_HDA_OSTRM_COH          0x4c
 344 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 345
 346 /* Defines for Intel SCH HDA snoop control */
 347 #define INTEL_SCH_HDA_DEVC      0x78
 348 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 349
 350 /* Define IN stream 0 FIFO size offset in VIA controller */
 351 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 352 /* Define VIA HD Audio Device ID*/
 353 #define VIA_HDAC_DEVICE_ID              0x3288
 354
 355 /* HD Audio class code */
 356 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 357
 358 /*
 359  */
 360
 361 struct azx_dev {
 362         struct snd_dma_buffer bdl; /* BDL buffer */
 363         u32 *posbuf;            /* position buffer pointer */
 364
 365         unsigned int bufsize;   /* size of the play buffer in bytes */
 366         unsigned int period_bytes; /* size of the period in bytes */
 367         unsigned int frags;     /* number for period in the play buffer */
 368         unsigned int fifo_size; /* FIFO size */
 369         unsigned long start_wallclk;    /* start + minimum wallclk */
 370         unsigned long period_wallclk;   /* wallclk for period */
 371
 372         void __iomem *sd_addr;  /* stream descriptor pointer */
 373
 374         u32 sd_int_sta_mask;    /* stream int status mask */
 375
 376         /* pcm support */
 377         struct snd_pcm_substream *substream;    /* assigned substream,
 378                                                  * set in PCM open
 379                                                  */
 380         unsigned int format_val;        /* format value to be set in the
 381                                          * controller and the codec
 382                                          */
 383         unsigned char stream_tag;       /* assigned stream */
 384         unsigned char index;            /* stream index */
 385         int assigned_key;               /* last device# key assigned to */
 386
 387         unsigned int opened :1;
 388         unsigned int running :1;
 389         unsigned int irq_pending :1;
 390         /*
 391          * For VIA:
 392          *  A flag to ensure DMA position is 0
 393          *  when link position is not greater than FIFO size
 394          */
 395         unsigned int insufficient :1;
 396         unsigned int wc_marked:1;
 397 };
 398
 399 /* CORB/RIRB */
 400 struct azx_rb {
 401         u32 *buf;               /* CORB/RIRB buffer
 402                                  * Each CORB entry is 4byte, RIRB is 8byte
 403                                  */
 404         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 405         /* for RIRB */
 406         unsigned short rp, wp;  /* read/write pointers */
 407         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 408         u32 res[AZX_MAX_CODECS];        /* last read value */
 409 };
 410
 411 struct azx {
 412         struct snd_card *card;
 413         struct pci_dev *pci;
 414         int dev_index;
 415
 416         /* chip type specific */
 417         int driver_type;
 418         unsigned int driver_caps;
 419         int playback_streams;
 420         int playback_index_offset;
 421         int capture_streams;
 422         int capture_index_offset;
 423         int num_streams;
 424
 425         /* pci resources */
 426         unsigned long addr;
 427         void __iomem *remap_addr;
 428         int irq;
 429
 430         /* locks */
 431         spinlock_t reg_lock;
 432         struct mutex open_mutex;
 433
 434         /* streams (x num_streams) */
 435         struct azx_dev *azx_dev;
 436
 437         /* PCM */
 438         struct snd_pcm *pcm[HDA_MAX_PCMS];
 439
 440         /* HD codec */
 441         unsigned short codec_mask;
 442         int  codec_probe_mask; /* copied from probe_mask option */
 443         struct hda_bus *bus;
 444         unsigned int beep_mode;
 445
 446         /* CORB/RIRB */
 447         struct azx_rb corb;
 448         struct azx_rb rirb;
 449
 450         /* CORB/RIRB and position buffers */
 451         struct snd_dma_buffer rb;
 452         struct snd_dma_buffer posbuf;
 453
 454         /* flags */
 455         int position_fix[2]; /* for both playback/capture streams */
 456         int poll_count;
 457         unsigned int running :1;
 458         unsigned int initialized :1;
 459         unsigned int single_cmd :1;
 460         unsigned int polling_mode :1;
 461         unsigned int msi :1;
 462         unsigned int irq_pending_warned :1;
 463         unsigned int probing :1; /* codec probing phase */
 464         unsigned int snoop:1;
 465         unsigned int align_buffer_size:1;
 466
 467         /* for debugging */
 468         unsigned int last_cmd[AZX_MAX_CODECS];
 469
 470         /* for pending irqs */
 471         struct work_struct irq_pending_work;
 472
 473         /* reboot notifier (for mysterious hangup problem at power-down) */
 474         struct notifier_block reboot_notifier;
 475 };
 476
 477 /* driver types */
 478 enum {
 479         AZX_DRIVER_ICH,
 480         AZX_DRIVER_PCH,
 481         AZX_DRIVER_SCH,
 482         AZX_DRIVER_ATI,
 483         AZX_DRIVER_ATIHDMI,
 484         AZX_DRIVER_VIA,
 485         AZX_DRIVER_SIS,
 486         AZX_DRIVER_ULI,
 487         AZX_DRIVER_NVIDIA,
 488         AZX_DRIVER_TERA,
 489         AZX_DRIVER_CTX,
 490         AZX_DRIVER_GENERIC,
 491         AZX_NUM_DRIVERS, /* keep this as last entry */
 492 };
 493
 494 /* driver quirks (capabilities) */
 495 /* bits 0-7 are used for indicating driver type */
 496 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
 497 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
 498 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
 499 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
 500 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
 501 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
 502 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
 503 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
 504 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
 505 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
 506 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
 507 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
 508 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
 509 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
 510
 511 /* quirks for ATI SB / AMD Hudson */
 512 #define AZX_DCAPS_PRESET_ATI_SB \
 513         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
 514          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 515
 516 /* quirks for ATI/AMD HDMI */
 517 #define AZX_DCAPS_PRESET_ATI_HDMI \
 518         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
 519
 520 /* quirks for Nvidia */
 521 #define AZX_DCAPS_PRESET_NVIDIA \
 522         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
 523
 524 static char *driver_short_names[] __devinitdata = {
 525         [AZX_DRIVER_ICH] = "HDA Intel",
 526         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 527         [AZX_DRIVER_SCH] = "HDA Intel MID",
 528         [AZX_DRIVER_ATI] = "HDA ATI SB",
 529         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 530         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 531         [AZX_DRIVER_SIS] = "HDA SIS966",
 532         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 533         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 534         [AZX_DRIVER_TERA] = "HDA Teradici",
 535         [AZX_DRIVER_CTX] = "HDA Creative",
 536         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 537 };
 538
 539 /*
 540  * macros for easy use
 541  */
 542 #define azx_writel(chip,reg,value) \
 543         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 544 #define azx_readl(chip,reg) \
 545         readl((chip)->remap_addr + ICH6_REG_##reg)
 546 #define azx_writew(chip,reg,value) \
 547         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 548 #define azx_readw(chip,reg) \
 549         readw((chip)->remap_addr + ICH6_REG_##reg)
 550 #define azx_writeb(chip,reg,value) \
 551         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 552 #define azx_readb(chip,reg) \
 553         readb((chip)->remap_addr + ICH6_REG_##reg)
 554
 555 #define azx_sd_writel(dev,reg,value) \
 556         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 557 #define azx_sd_readl(dev,reg) \
 558         readl((dev)->sd_addr + ICH6_REG_##reg)
 559 #define azx_sd_writew(dev,reg,value) \
 560         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 561 #define azx_sd_readw(dev,reg) \
 562         readw((dev)->sd_addr + ICH6_REG_##reg)
 563 #define azx_sd_writeb(dev,reg,value) \
 564         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 565 #define azx_sd_readb(dev,reg) \
 566         readb((dev)->sd_addr + ICH6_REG_##reg)
 567
 568 /* for pcm support */
 569 #define get_azx_dev(substream) (substream->runtime->private_data)
 570
 571 #ifdef CONFIG_X86
 572 static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
 573 {
 574         if (azx_snoop(chip))
 575                 return;
 576         if (addr && size) {
 577                 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
 578                 if (on)
 579                         set_memory_wc((unsigned long)addr, pages);
 580                 else
 581                         set_memory_wb((unsigned long)addr, pages);
 582         }
 583 }
 584
 585 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 586                                  bool on)
 587 {
 588         __mark_pages_wc(chip, buf->area, buf->bytes, on);
 589 }
 590 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 591                                    struct snd_pcm_runtime *runtime, bool on)
 592 {
 593         if (azx_dev->wc_marked != on) {
 594                 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
 595                 azx_dev->wc_marked = on;
 596         }
 597 }
 598 #else
 599 /* NOP for other archs */
 600 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
 601                                  bool on)
 602 {
 603 }
 604 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
 605                                    struct snd_pcm_runtime *runtime, bool on)
 606 {
 607 }
 608 #endif
 609
 610 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 611 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 612 /*
 613  * Interface for HD codec
 614  */
 615
 616 /*
 617  * CORB / RIRB interface
 618  */
 619 static int azx_alloc_cmd_io(struct azx *chip)
 620 {
 621         int err;
 622
 623         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 624         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 625                                   snd_dma_pci_data(chip->pci),
 626                                   PAGE_SIZE, &chip->rb);
 627         if (err < 0) {
 628                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 629                 return err;
 630         }
 631         mark_pages_wc(chip, &chip->rb, true);
 632         return 0;
 633 }
 634
 635 static void azx_init_cmd_io(struct azx *chip)
 636 {
 637         spin_lock_irq(&chip->reg_lock);
 638         /* CORB set up */
 639         chip->corb.addr = chip->rb.addr;
 640         chip->corb.buf = (u32 *)chip->rb.area;
 641         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 642         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 643
 644         /* set the corb size to 256 entries (ULI requires explicitly) */
 645         azx_writeb(chip, CORBSIZE, 0x02);
 646         /* set the corb write pointer to 0 */
 647         azx_writew(chip, CORBWP, 0);
 648         /* reset the corb hw read pointer */
 649         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 650         /* enable corb dma */
 651         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 652
 653         /* RIRB set up */
 654         chip->rirb.addr = chip->rb.addr + 2048;
 655         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 656         chip->rirb.wp = chip->rirb.rp = 0;
 657         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 658         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 659         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 660
 661         /* set the rirb size to 256 entries (ULI requires explicitly) */
 662         azx_writeb(chip, RIRBSIZE, 0x02);
 663         /* reset the rirb hw write pointer */
 664         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 665         /* set N=1, get RIRB response interrupt for new entry */
 666         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
 667                 azx_writew(chip, RINTCNT, 0xc0);
 668         else
 669                 azx_writew(chip, RINTCNT, 1);
 670         /* enable rirb dma and response irq */
 671         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 672         spin_unlock_irq(&chip->reg_lock);
 673 }
 674
 675 static void azx_free_cmd_io(struct azx *chip)
 676 {
 677         spin_lock_irq(&chip->reg_lock);
 678         /* disable ringbuffer DMAs */
 679         azx_writeb(chip, RIRBCTL, 0);
 680         azx_writeb(chip, CORBCTL, 0);
 681         spin_unlock_irq(&chip->reg_lock);
 682 }
 683
 684 static unsigned int azx_command_addr(u32 cmd)
 685 {
 686         unsigned int addr = cmd >> 28;
 687
 688         if (addr >= AZX_MAX_CODECS) {
 689                 snd_BUG();
 690                 addr = 0;
 691         }
 692
 693         return addr;
 694 }
 695
 696 static unsigned int azx_response_addr(u32 res)
 697 {
 698         unsigned int addr = res & 0xf;
 699
 700         if (addr >= AZX_MAX_CODECS) {
 701                 snd_BUG();
 702                 addr = 0;
 703         }
 704
 705         return addr;
 706 }
 707
 708 /* send a command */
 709 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 710 {
 711         struct azx *chip = bus->private_data;
 712         unsigned int addr = azx_command_addr(val);
 713         unsigned int wp;
 714
 715         spin_lock_irq(&chip->reg_lock);
 716
 717         /* add command to corb */
 718         wp = azx_readb(chip, CORBWP);
 719         wp++;
 720         wp %= ICH6_MAX_CORB_ENTRIES;
 721
 722         chip->rirb.cmds[addr]++;
 723         chip->corb.buf[wp] = cpu_to_le32(val);
 724         azx_writel(chip, CORBWP, wp);
 725
 726         spin_unlock_irq(&chip->reg_lock);
 727
 728         return 0;
 729 }
 730
 731 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 732
 733 /* retrieve RIRB entry - called from interrupt handler */
 734 static void azx_update_rirb(struct azx *chip)
 735 {
 736         unsigned int rp, wp;
 737         unsigned int addr;
 738         u32 res, res_ex;
 739
 740         wp = azx_readb(chip, RIRBWP);
 741         if (wp == chip->rirb.wp)
 742                 return;
 743         chip->rirb.wp = wp;
 744
 745         while (chip->rirb.rp != wp) {
 746                 chip->rirb.rp++;
 747                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 748
 749                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 750                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 751                 res = le32_to_cpu(chip->rirb.buf[rp]);
 752                 addr = azx_response_addr(res_ex);
 753                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 754                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 755                 else if (chip->rirb.cmds[addr]) {
 756                         chip->rirb.res[addr] = res;
 757                         smp_wmb();
 758                         chip->rirb.cmds[addr]--;
 759                 } else
 760                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 761                                    "last cmd=%#08x\n",
 762                                    res, res_ex,
 763                                    chip->last_cmd[addr]);
 764         }
 765 }
 766
 767 /* receive a response */
 768 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 769                                           unsigned int addr)
 770 {
 771         struct azx *chip = bus->private_data;
 772         unsigned long timeout;
 773         unsigned long loopcounter;
 774         int do_poll = 0;
 775
 776  again:
 777         timeout = jiffies + msecs_to_jiffies(1000);
 778
 779         for (loopcounter = 0;; loopcounter++) {
 780                 if (chip->polling_mode || do_poll) {
 781                         spin_lock_irq(&chip->reg_lock);
 782                         azx_update_rirb(chip);
 783                         spin_unlock_irq(&chip->reg_lock);
 784                 }
 785                 if (!chip->rirb.cmds[addr]) {
 786                         smp_rmb();
 787                         bus->rirb_error = 0;
 788
 789                         if (!do_poll)
 790                                 chip->poll_count = 0;
 791                         return chip->rirb.res[addr]; /* the last value */
 792                 }
 793                 if (time_after(jiffies, timeout))
 794                         break;
 795                 if (bus->needs_damn_long_delay || loopcounter > 3000)
 796                         msleep(2); /* temporary workaround */
 797                 else {
 798                         udelay(10);
 799                         cond_resched();
 800                 }
 801         }
 802
 803         if (!chip->polling_mode && chip->poll_count < 2) {
 804                 snd_printdd(SFX "azx_get_response timeout, "
 805                            "polling the codec once: last cmd=0x%08x\n",
 806                            chip->last_cmd[addr]);
 807                 do_poll = 1;
 808                 chip->poll_count++;
 809                 goto again;
 810         }
 811
 812
 813         if (!chip->polling_mode) {
 814                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 815                            "switching to polling mode: last cmd=0x%08x\n",
 816                            chip->last_cmd[addr]);
 817                 chip->polling_mode = 1;
 818                 goto again;
 819         }
 820
 821         if (chip->msi) {
 822                 snd_printk(KERN_WARNING SFX "No response from codec, "
 823                            "disabling MSI: last cmd=0x%08x\n",
 824                            chip->last_cmd[addr]);
 825                 free_irq(chip->irq, chip);
 826                 chip->irq = -1;
 827                 pci_disable_msi(chip->pci);
 828                 chip->msi = 0;
 829                 if (azx_acquire_irq(chip, 1) < 0) {
 830                         bus->rirb_error = 1;
 831                         return -1;
 832                 }
 833                 goto again;
 834         }
 835
 836         if (chip->probing) {
 837                 /* If this critical timeout happens during the codec probing
 838                  * phase, this is likely an access to a non-existing codec
 839                  * slot.  Better to return an error and reset the system.
 840                  */
 841                 return -1;
 842         }
 843
 844         /* a fatal communication error; need either to reset or to fallback
 845          * to the single_cmd mode
 846          */
 847         bus->rirb_error = 1;
 848         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 849                 bus->response_reset = 1;
 850                 return -1; /* give a chance to retry */
 851         }
 852
 853         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 854                    "switching to single_cmd mode: last cmd=0x%08x\n",
 855                    chip->last_cmd[addr]);
 856         chip->single_cmd = 1;
 857         bus->response_reset = 0;
 858         /* release CORB/RIRB */
 859         azx_free_cmd_io(chip);
 860         /* disable unsolicited responses */
 861         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 862         return -1;
 863 }
 864
 865 /*
 866  * Use the single immediate command instead of CORB/RIRB for simplicity
 867  *
 868  * Note: according to Intel, this is not preferred use.  The command was
 869  *       intended for the BIOS only, and may get confused with unsolicited
 870  *       responses.  So, we shouldn't use it for normal operation from the
 871  *       driver.
 872  *       I left the codes, however, for debugging/testing purposes.
 873  */
 874
 875 /* receive a response */
 876 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 877 {
 878         int timeout = 50;
 879
 880         while (timeout--) {
 881                 /* check IRV busy bit */
 882                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 883                         /* reuse rirb.res as the response return value */
 884                         chip->rirb.res[addr] = azx_readl(chip, IR);
 885                         return 0;
 886                 }
 887                 udelay(1);
 888         }
 889         if (printk_ratelimit())
 890                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 891                            azx_readw(chip, IRS));
 892         chip->rirb.res[addr] = -1;
 893         return -EIO;
 894 }
 895
 896 /* send a command */
 897 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 898 {
 899         struct azx *chip = bus->private_data;
 900         unsigned int addr = azx_command_addr(val);
 901         int timeout = 50;
 902
 903         bus->rirb_error = 0;
 904         while (timeout--) {
 905                 /* check ICB busy bit */
 906                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 907                         /* Clear IRV valid bit */
 908                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 909                                    ICH6_IRS_VALID);
 910                         azx_writel(chip, IC, val);
 911                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 912                                    ICH6_IRS_BUSY);
 913                         return azx_single_wait_for_response(chip, addr);
 914                 }
 915                 udelay(1);
 916         }
 917         if (printk_ratelimit())
 918                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 919                            azx_readw(chip, IRS), val);
 920         return -EIO;
 921 }
 922
 923 /* receive a response */
 924 static unsigned int azx_single_get_response(struct hda_bus *bus,
 925                                             unsigned int addr)
 926 {
 927         struct azx *chip = bus->private_data;
 928         return chip->rirb.res[addr];
 929 }
 930
 931 /*
 932  * The below are the main callbacks from hda_codec.
 933  *
 934  * They are just the skeleton to call sub-callbacks according to the
 935  * current setting of chip->single_cmd.
 936  */
 937
 938 /* send a command */
 939 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 940 {
 941         struct azx *chip = bus->private_data;
 942
 943         chip->last_cmd[azx_command_addr(val)] = val;
 944         if (chip->single_cmd)
 945                 return azx_single_send_cmd(bus, val);
 946         else
 947                 return azx_corb_send_cmd(bus, val);
 948 }
 949
 950 /* get a response */
 951 static unsigned int azx_get_response(struct hda_bus *bus,
 952                                      unsigned int addr)
 953 {
 954         struct azx *chip = bus->private_data;
 955         if (chip->single_cmd)
 956                 return azx_single_get_response(bus, addr);
 957         else
 958                 return azx_rirb_get_response(bus, addr);
 959 }
 960
 961 #ifdef CONFIG_SND_HDA_POWER_SAVE
 962 static void azx_power_notify(struct hda_bus *bus);
 963 #endif
 964
 965 /* reset codec link */
 966 static int azx_reset(struct azx *chip, int full_reset)
 967 {
 968         int count;
 969
 970         if (!full_reset)
 971                 goto __skip;
 972
 973         /* clear STATESTS */
 974         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 975
 976         /* reset controller */
 977         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 978
 979         count = 50;
 980         while (azx_readb(chip, GCTL) && --count)
 981                 msleep(1);
 982
 983         /* delay for >= 100us for codec PLL to settle per spec
 984          * Rev 0.9 section 5.5.1
 985          */
 986         msleep(1);
 987
 988         /* Bring controller out of reset */
 989         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 990
 991         count = 50;
 992         while (!azx_readb(chip, GCTL) && --count)
 993                 msleep(1);
 994
 995         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 996         msleep(1);
 997
 998       __skip:
 999         /* check to see if controller is ready */
1000         if (!azx_readb(chip, GCTL)) {
1001                 snd_printd(SFX "azx_reset: controller not ready!\n");
1002                 return -EBUSY;
1003         }
1004
1005         /* Accept unsolicited responses */
1006         if (!chip->single_cmd)
1007                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1008                            ICH6_GCTL_UNSOL);
1009
1010         /* detect codecs */
1011         if (!chip->codec_mask) {
1012                 chip->codec_mask = azx_readw(chip, STATESTS);
1013                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1014         }
1015
1016         return 0;
1017 }
1018
1019
1020 /*
1021  * Lowlevel interface
1022  */
1023
1024 /* enable interrupts */
1025 static void azx_int_enable(struct azx *chip)
1026 {
1027         /* enable controller CIE and GIE */
1028         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1029                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1030 }
1031
1032 /* disable interrupts */
1033 static void azx_int_disable(struct azx *chip)
1034 {
1035         int i;
1036
1037         /* disable interrupts in stream descriptor */
1038         for (i = 0; i < chip->num_streams; i++) {
1039                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1040                 azx_sd_writeb(azx_dev, SD_CTL,
1041                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1042         }
1043
1044         /* disable SIE for all streams */
1045         azx_writeb(chip, INTCTL, 0);
1046
1047         /* disable controller CIE and GIE */
1048         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1049                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1050 }
1051
1052 /* clear interrupts */
1053 static void azx_int_clear(struct azx *chip)
1054 {
1055         int i;
1056
1057         /* clear stream status */
1058         for (i = 0; i < chip->num_streams; i++) {
1059                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1060                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1061         }
1062
1063         /* clear STATESTS */
1064         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1065
1066         /* clear rirb status */
1067         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1068
1069         /* clear int status */
1070         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1071 }
1072
1073 /* start a stream */
1074 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1075 {
1076         /*
1077          * Before stream start, initialize parameter
1078          */
1079         azx_dev->insufficient = 1;
1080
1081         /* enable SIE */
1082         azx_writel(chip, INTCTL,
1083                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1084         /* set DMA start and interrupt mask */
1085         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1086                       SD_CTL_DMA_START | SD_INT_MASK);
1087 }
1088
1089 /* stop DMA */
1090 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1091 {
1092         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1093                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1094         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1095 }
1096
1097 /* stop a stream */
1098 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1099 {
1100         azx_stream_clear(chip, azx_dev);
1101         /* disable SIE */
1102         azx_writel(chip, INTCTL,
1103                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1104 }
1105
1106
1107 /*
1108  * reset and start the controller registers
1109  */
1110 static void azx_init_chip(struct azx *chip, int full_reset)
1111 {
1112         if (chip->initialized)
1113                 return;
1114
1115         /* reset controller */
1116         azx_reset(chip, full_reset);
1117
1118         /* initialize interrupts */
1119         azx_int_clear(chip);
1120         azx_int_enable(chip);
1121
1122         /* initialize the codec command I/O */
1123         if (!chip->single_cmd)
1124                 azx_init_cmd_io(chip);
1125
1126         /* program the position buffer */
1127         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1128         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1129
1130         chip->initialized = 1;
1131 }
1132
1133 /*
1134  * initialize the PCI registers
1135  */
1136 /* update bits in a PCI register byte */
1137 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1138                             unsigned char mask, unsigned char val)
1139 {
1140         unsigned char data;
1141
1142         pci_read_config_byte(pci, reg, &data);
1143         data &= ~mask;
1144         data |= (val & mask);
1145         pci_write_config_byte(pci, reg, data);
1146 }
1147
1148 static void azx_init_pci(struct azx *chip)
1149 {
1150         /* force to non-snoop mode for a new VIA controller when BIOS is set */
1151         if (chip->snoop && chip->driver_type == AZX_DRIVER_VIA) {
1152                 u8 snoop;
1153                 pci_read_config_byte(chip->pci, 0x42, &snoop);
1154                 if (!(snoop & 0x80) && chip->pci->revision == 0x30) {
1155                         chip->snoop = 0;
1156                         snd_printdd(SFX "Force to non-snoop mode\n");
1157                 }
1158         }
1159
1160         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1161          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1162          * Ensuring these bits are 0 clears playback static on some HD Audio
1163          * codecs.
1164          * The PCI register TCSEL is defined in the Intel manuals.
1165          */
1166         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1167                 snd_printdd(SFX "Clearing TCSEL\n");
1168                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1169         }
1170
1171         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1172          * we need to enable snoop.
1173          */
1174         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1175                 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1176                 update_pci_byte(chip->pci,
1177                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1178                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1179         }
1180
1181         /* For NVIDIA HDA, enable snoop */
1182         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1183                 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1184                 update_pci_byte(chip->pci,
1185                                 NVIDIA_HDA_TRANSREG_ADDR,
1186                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1187                 update_pci_byte(chip->pci,
1188                                 NVIDIA_HDA_ISTRM_COH,
1189                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1190                 update_pci_byte(chip->pci,
1191                                 NVIDIA_HDA_OSTRM_COH,
1192                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1193         }
1194
1195         /* Enable SCH/PCH snoop if needed */
1196         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1197                 unsigned short snoop;
1198                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1199                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1200                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1201                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1202                         if (!azx_snoop(chip))
1203                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1204                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1205                         pci_read_config_word(chip->pci,
1206                                 INTEL_SCH_HDA_DEVC, &snoop);
1207                 }
1208                 snd_printdd(SFX "SCH snoop: %s\n",
1209                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1210                                 ? "Disabled" : "Enabled");
1211         }
1212 }
1213
1214
1215 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1216
1217 /*
1218  * interrupt handler
1219  */
1220 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1221 {
1222         struct azx *chip = dev_id;
1223         struct azx_dev *azx_dev;
1224         u32 status;
1225         u8 sd_status;
1226         int i, ok;
1227
1228         spin_lock(&chip->reg_lock);
1229
1230         status = azx_readl(chip, INTSTS);
1231         if (status == 0) {
1232                 spin_unlock(&chip->reg_lock);
1233                 return IRQ_NONE;
1234         }
1235
1236         for (i = 0; i < chip->num_streams; i++) {
1237                 azx_dev = &chip->azx_dev[i];
1238                 if (status & azx_dev->sd_int_sta_mask) {
1239                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1240                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1241                         if (!azx_dev->substream || !azx_dev->running ||
1242                             !(sd_status & SD_INT_COMPLETE))
1243                                 continue;
1244                         /* check whether this IRQ is really acceptable */
1245                         ok = azx_position_ok(chip, azx_dev);
1246                         if (ok == 1) {
1247                                 azx_dev->irq_pending = 0;
1248                                 spin_unlock(&chip->reg_lock);
1249                                 snd_pcm_period_elapsed(azx_dev->substream);
1250                                 spin_lock(&chip->reg_lock);
1251                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1252                                 /* bogus IRQ, process it later */
1253                                 azx_dev->irq_pending = 1;
1254                                 queue_work(chip->bus->workq,
1255                                            &chip->irq_pending_work);
1256                         }
1257                 }
1258         }
1259
1260         /* clear rirb int */
1261         status = azx_readb(chip, RIRBSTS);
1262         if (status & RIRB_INT_MASK) {
1263                 if (status & RIRB_INT_RESPONSE) {
1264                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1265                                 udelay(80);
1266                         azx_update_rirb(chip);
1267                 }
1268                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1269         }
1270
1271 #if 0
1272         /* clear state status int */
1273         if (azx_readb(chip, STATESTS) & 0x04)
1274                 azx_writeb(chip, STATESTS, 0x04);
1275 #endif
1276         spin_unlock(&chip->reg_lock);
1277
1278         return IRQ_HANDLED;
1279 }
1280
1281
1282 /*
1283  * set up a BDL entry
1284  */
1285 static int setup_bdle(struct snd_pcm_substream *substream,
1286                       struct azx_dev *azx_dev, u32 **bdlp,
1287                       int ofs, int size, int with_ioc)
1288 {
1289         u32 *bdl = *bdlp;
1290
1291         while (size > 0) {
1292                 dma_addr_t addr;
1293                 int chunk;
1294
1295                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1296                         return -EINVAL;
1297
1298                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1299                 /* program the address field of the BDL entry */
1300                 bdl[0] = cpu_to_le32((u32)addr);
1301                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1302                 /* program the size field of the BDL entry */
1303                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1304                 bdl[2] = cpu_to_le32(chunk);
1305                 /* program the IOC to enable interrupt
1306                  * only when the whole fragment is processed
1307                  */
1308                 size -= chunk;
1309                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1310                 bdl += 4;
1311                 azx_dev->frags++;
1312                 ofs += chunk;
1313         }
1314         *bdlp = bdl;
1315         return ofs;
1316 }
1317
1318 /*
1319  * set up BDL entries
1320  */
1321 static int azx_setup_periods(struct azx *chip,
1322                              struct snd_pcm_substream *substream,
1323                              struct azx_dev *azx_dev)
1324 {
1325         u32 *bdl;
1326         int i, ofs, periods, period_bytes;
1327         int pos_adj;
1328
1329         /* reset BDL address */
1330         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1331         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1332
1333         period_bytes = azx_dev->period_bytes;
1334         periods = azx_dev->bufsize / period_bytes;
1335
1336         /* program the initial BDL entries */
1337         bdl = (u32 *)azx_dev->bdl.area;
1338         ofs = 0;
1339         azx_dev->frags = 0;
1340         pos_adj = bdl_pos_adj[chip->dev_index];
1341         if (pos_adj > 0) {
1342                 struct snd_pcm_runtime *runtime = substream->runtime;
1343                 int pos_align = pos_adj;
1344                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1345                 if (!pos_adj)
1346                         pos_adj = pos_align;
1347                 else
1348                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1349                                 pos_align;
1350                 pos_adj = frames_to_bytes(runtime, pos_adj);
1351                 if (pos_adj >= period_bytes) {
1352                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1353                                    bdl_pos_adj[chip->dev_index]);
1354                         pos_adj = 0;
1355                 } else {
1356                         ofs = setup_bdle(substream, azx_dev,
1357                                          &bdl, ofs, pos_adj,
1358                                          !substream->runtime->no_period_wakeup);
1359                         if (ofs < 0)
1360                                 goto error;
1361                 }
1362         } else
1363                 pos_adj = 0;
1364         for (i = 0; i < periods; i++) {
1365                 if (i == periods - 1 && pos_adj)
1366                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1367                                          period_bytes - pos_adj, 0);
1368                 else
1369                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1370                                          period_bytes,
1371                                          !substream->runtime->no_period_wakeup);
1372                 if (ofs < 0)
1373                         goto error;
1374         }
1375         return 0;
1376
1377  error:
1378         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1379                    azx_dev->bufsize, period_bytes);
1380         return -EINVAL;
1381 }
1382
1383 /* reset stream */
1384 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1385 {
1386         unsigned char val;
1387         int timeout;
1388
1389         azx_stream_clear(chip, azx_dev);
1390
1391         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1392                       SD_CTL_STREAM_RESET);
1393         udelay(3);
1394         timeout = 300;
1395         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1396                --timeout)
1397                 ;
1398         val &= ~SD_CTL_STREAM_RESET;
1399         azx_sd_writeb(azx_dev, SD_CTL, val);
1400         udelay(3);
1401
1402         timeout = 300;
1403         /* waiting for hardware to report that the stream is out of reset */
1404         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1405                --timeout)
1406                 ;
1407
1408         /* reset first position - may not be synced with hw at this time */
1409         *azx_dev->posbuf = 0;
1410 }
1411
1412 /*
1413  * set up the SD for streaming
1414  */
1415 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1416 {
1417         unsigned int val;
1418         /* make sure the run bit is zero for SD */
1419         azx_stream_clear(chip, azx_dev);
1420         /* program the stream_tag */
1421         val = azx_sd_readl(azx_dev, SD_CTL);
1422         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1423                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1424         if (!azx_snoop(chip))
1425                 val |= SD_CTL_TRAFFIC_PRIO;
1426         azx_sd_writel(azx_dev, SD_CTL, val);
1427
1428         /* program the length of samples in cyclic buffer */
1429         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1430
1431         /* program the stream format */
1432         /* this value needs to be the same as the one programmed */
1433         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1434
1435         /* program the stream LVI (last valid index) of the BDL */
1436         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1437
1438         /* program the BDL address */
1439         /* lower BDL address */
1440         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1441         /* upper BDL address */
1442         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1443
1444         /* enable the position buffer */
1445         if (chip->position_fix[0] != POS_FIX_LPIB ||
1446             chip->position_fix[1] != POS_FIX_LPIB) {
1447                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1448                         azx_writel(chip, DPLBASE,
1449                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1450         }
1451
1452         /* set the interrupt enable bits in the descriptor control register */
1453         azx_sd_writel(azx_dev, SD_CTL,
1454                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1455
1456         return 0;
1457 }
1458
1459 /*
1460  * Probe the given codec address
1461  */
1462 static int probe_codec(struct azx *chip, int addr)
1463 {
1464         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1465                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1466         unsigned int res;
1467
1468         mutex_lock(&chip->bus->cmd_mutex);
1469         chip->probing = 1;
1470         azx_send_cmd(chip->bus, cmd);
1471         res = azx_get_response(chip->bus, addr);
1472         chip->probing = 0;
1473         mutex_unlock(&chip->bus->cmd_mutex);
1474         if (res == -1)
1475                 return -EIO;
1476         snd_printdd(SFX "codec #%d probed OK\n", addr);
1477         return 0;
1478 }
1479
1480 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1481                                  struct hda_pcm *cpcm);
1482 static void azx_stop_chip(struct azx *chip);
1483
1484 static void azx_bus_reset(struct hda_bus *bus)
1485 {
1486         struct azx *chip = bus->private_data;
1487
1488         bus->in_reset = 1;
1489         azx_stop_chip(chip);
1490         azx_init_chip(chip, 1);
1491 #ifdef CONFIG_PM
1492         if (chip->initialized) {
1493                 int i;
1494
1495                 for (i = 0; i < HDA_MAX_PCMS; i++)
1496                         snd_pcm_suspend_all(chip->pcm[i]);
1497                 snd_hda_suspend(chip->bus);
1498                 snd_hda_resume(chip->bus);
1499         }
1500 #endif
1501         bus->in_reset = 0;
1502 }
1503
1504 /*
1505  * Codec initialization
1506  */
1507
1508 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1509 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1510         [AZX_DRIVER_NVIDIA] = 8,
1511         [AZX_DRIVER_TERA] = 1,
1512 };
1513
1514 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1515 {
1516         struct hda_bus_template bus_temp;
1517         int c, codecs, err;
1518         int max_slots;
1519
1520         memset(&bus_temp, 0, sizeof(bus_temp));
1521         bus_temp.private_data = chip;
1522         bus_temp.modelname = model;
1523         bus_temp.pci = chip->pci;
1524         bus_temp.ops.command = azx_send_cmd;
1525         bus_temp.ops.get_response = azx_get_response;
1526         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1527         bus_temp.ops.bus_reset = azx_bus_reset;
1528 #ifdef CONFIG_SND_HDA_POWER_SAVE
1529         bus_temp.power_save = &power_save;
1530         bus_temp.ops.pm_notify = azx_power_notify;
1531 #endif
1532
1533         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1534         if (err < 0)
1535                 return err;
1536
1537         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1538                 snd_printd(SFX "Enable delay in RIRB handling\n");
1539                 chip->bus->needs_damn_long_delay = 1;
1540         }
1541
1542         codecs = 0;
1543         max_slots = azx_max_codecs[chip->driver_type];
1544         if (!max_slots)
1545                 max_slots = AZX_DEFAULT_CODECS;
1546
1547         /* First try to probe all given codec slots */
1548         for (c = 0; c < max_slots; c++) {
1549                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1550                         if (probe_codec(chip, c) < 0) {
1551                                 /* Some BIOSen give you wrong codec addresses
1552                                  * that don't exist
1553                                  */
1554                                 snd_printk(KERN_WARNING SFX
1555                                            "Codec #%d probe error; "
1556                                            "disabling it...\n", c);
1557                                 chip->codec_mask &= ~(1 << c);
1558                                 /* More badly, accessing to a non-existing
1559                                  * codec often screws up the controller chip,
1560                                  * and disturbs the further communications.
1561                                  * Thus if an error occurs during probing,
1562                                  * better to reset the controller chip to
1563                                  * get back to the sanity state.
1564                                  */
1565                                 azx_stop_chip(chip);
1566                                 azx_init_chip(chip, 1);
1567                         }
1568                 }
1569         }
1570
1571         /* AMD chipsets often cause the communication stalls upon certain
1572          * sequence like the pin-detection.  It seems that forcing the synced
1573          * access works around the stall.  Grrr...
1574          */
1575         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1576                 snd_printd(SFX "Enable sync_write for stable communication\n");
1577                 chip->bus->sync_write = 1;
1578                 chip->bus->allow_bus_reset = 1;
1579         }
1580
1581         /* Then create codec instances */
1582         for (c = 0; c < max_slots; c++) {
1583                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1584                         struct hda_codec *codec;
1585                         err = snd_hda_codec_new(chip->bus, c, &codec);
1586                         if (err < 0)
1587                                 continue;
1588                         codec->beep_mode = chip->beep_mode;
1589                         codecs++;
1590                 }
1591         }
1592         if (!codecs) {
1593                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1594                 return -ENXIO;
1595         }
1596         return 0;
1597 }
1598
1599 /* configure each codec instance */
1600 static int __devinit azx_codec_configure(struct azx *chip)
1601 {
1602         struct hda_codec *codec;
1603         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1604                 snd_hda_codec_configure(codec);
1605         }
1606         return 0;
1607 }
1608
1609
1610 /*
1611  * PCM support
1612  */
1613
1614 /* assign a stream for the PCM */
1615 static inline struct azx_dev *
1616 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1617 {
1618         int dev, i, nums;
1619         struct azx_dev *res = NULL;
1620         /* make a non-zero unique key for the substream */
1621         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1622                 (substream->stream + 1);
1623
1624         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1625                 dev = chip->playback_index_offset;
1626                 nums = chip->playback_streams;
1627         } else {
1628                 dev = chip->capture_index_offset;
1629                 nums = chip->capture_streams;
1630         }
1631         for (i = 0; i < nums; i++, dev++)
1632                 if (!chip->azx_dev[dev].opened) {
1633                         res = &chip->azx_dev[dev];
1634                         if (res->assigned_key == key)
1635                                 break;
1636                 }
1637         if (res) {
1638                 res->opened = 1;
1639                 res->assigned_key = key;
1640         }
1641         return res;
1642 }
1643
1644 /* release the assigned stream */
1645 static inline void azx_release_device(struct azx_dev *azx_dev)
1646 {
1647         azx_dev->opened = 0;
1648 }
1649
1650 static struct snd_pcm_hardware azx_pcm_hw = {
1651         .info =                 (SNDRV_PCM_INFO_MMAP |
1652                                  SNDRV_PCM_INFO_INTERLEAVED |
1653                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1654                                  SNDRV_PCM_INFO_MMAP_VALID |
1655                                  /* No full-resume yet implemented */
1656                                  /* SNDRV_PCM_INFO_RESUME |*/
1657                                  SNDRV_PCM_INFO_PAUSE |
1658                                  SNDRV_PCM_INFO_SYNC_START |
1659                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1660         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1661         .rates =                SNDRV_PCM_RATE_48000,
1662         .rate_min =             48000,
1663         .rate_max =             48000,
1664         .channels_min =         2,
1665         .channels_max =         2,
1666         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1667         .period_bytes_min =     128,
1668         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1669         .periods_min =          2,
1670         .periods_max =          AZX_MAX_FRAG,
1671         .fifo_size =            0,
1672 };
1673
1674 struct azx_pcm {
1675         struct azx *chip;
1676         struct hda_codec *codec;
1677         struct hda_pcm_stream *hinfo[2];
1678 };
1679
1680 static int azx_pcm_open(struct snd_pcm_substream *substream)
1681 {
1682         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1683         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1684         struct azx *chip = apcm->chip;
1685         struct azx_dev *azx_dev;
1686         struct snd_pcm_runtime *runtime = substream->runtime;
1687         unsigned long flags;
1688         int err;
1689         int buff_step;
1690
1691         mutex_lock(&chip->open_mutex);
1692         azx_dev = azx_assign_device(chip, substream);
1693         if (azx_dev == NULL) {
1694                 mutex_unlock(&chip->open_mutex);
1695                 return -EBUSY;
1696         }
1697         runtime->hw = azx_pcm_hw;
1698         runtime->hw.channels_min = hinfo->channels_min;
1699         runtime->hw.channels_max = hinfo->channels_max;
1700         runtime->hw.formats = hinfo->formats;
1701         runtime->hw.rates = hinfo->rates;
1702         snd_pcm_limit_hw_rates(runtime);
1703         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1704         if (chip->align_buffer_size)
1705                 /* constrain buffer sizes to be multiple of 128
1706                    bytes. This is more efficient in terms of memory
1707                    access but isn't required by the HDA spec and
1708                    prevents users from specifying exact period/buffer
1709                    sizes. For example for 44.1kHz, a period size set
1710                    to 20ms will be rounded to 19.59ms. */
1711                 buff_step = 128;
1712         else
1713                 /* Don't enforce steps on buffer sizes, still need to
1714                    be multiple of 4 bytes (HDA spec). Tested on Intel
1715                    HDA controllers, may not work on all devices where
1716                    option needs to be disabled */
1717                 buff_step = 4;
1718
1719         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1720                                    buff_step);
1721         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1722                                    buff_step);
1723         snd_hda_power_up(apcm->codec);
1724         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1725         if (err < 0) {
1726                 azx_release_device(azx_dev);
1727                 snd_hda_power_down(apcm->codec);
1728                 mutex_unlock(&chip->open_mutex);
1729                 return err;
1730         }
1731         snd_pcm_limit_hw_rates(runtime);
1732         /* sanity check */
1733         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1734             snd_BUG_ON(!runtime->hw.channels_max) ||
1735             snd_BUG_ON(!runtime->hw.formats) ||
1736             snd_BUG_ON(!runtime->hw.rates)) {
1737                 azx_release_device(azx_dev);
1738                 hinfo->ops.close(hinfo, apcm->codec, substream);
1739                 snd_hda_power_down(apcm->codec);
1740                 mutex_unlock(&chip->open_mutex);
1741                 return -EINVAL;
1742         }
1743         spin_lock_irqsave(&chip->reg_lock, flags);
1744         azx_dev->substream = substream;
1745         azx_dev->running = 0;
1746         spin_unlock_irqrestore(&chip->reg_lock, flags);
1747
1748         runtime->private_data = azx_dev;
1749         snd_pcm_set_sync(substream);
1750         mutex_unlock(&chip->open_mutex);
1751         return 0;
1752 }
1753
1754 static int azx_pcm_close(struct snd_pcm_substream *substream)
1755 {
1756         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1757         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1758         struct azx *chip = apcm->chip;
1759         struct azx_dev *azx_dev = get_azx_dev(substream);
1760         unsigned long flags;
1761
1762         mutex_lock(&chip->open_mutex);
1763         spin_lock_irqsave(&chip->reg_lock, flags);
1764         azx_dev->substream = NULL;
1765         azx_dev->running = 0;
1766         spin_unlock_irqrestore(&chip->reg_lock, flags);
1767         azx_release_device(azx_dev);
1768         hinfo->ops.close(hinfo, apcm->codec, substream);
1769         snd_hda_power_down(apcm->codec);
1770         mutex_unlock(&chip->open_mutex);
1771         return 0;
1772 }
1773
1774 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1775                              struct snd_pcm_hw_params *hw_params)
1776 {
1777         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1778         struct azx *chip = apcm->chip;
1779         struct snd_pcm_runtime *runtime = substream->runtime;
1780         struct azx_dev *azx_dev = get_azx_dev(substream);
1781         int ret;
1782
1783         mark_runtime_wc(chip, azx_dev, runtime, false);
1784         azx_dev->bufsize = 0;
1785         azx_dev->period_bytes = 0;
1786         azx_dev->format_val = 0;
1787         ret = snd_pcm_lib_malloc_pages(substream,
1788                                         params_buffer_bytes(hw_params));
1789         if (ret < 0)
1790                 return ret;
1791         mark_runtime_wc(chip, azx_dev, runtime, true);
1792         return ret;
1793 }
1794
1795 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1796 {
1797         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1798         struct azx_dev *azx_dev = get_azx_dev(substream);
1799         struct azx *chip = apcm->chip;
1800         struct snd_pcm_runtime *runtime = substream->runtime;
1801         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1802
1803         /* reset BDL address */
1804         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1805         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1806         azx_sd_writel(azx_dev, SD_CTL, 0);
1807         azx_dev->bufsize = 0;
1808         azx_dev->period_bytes = 0;
1809         azx_dev->format_val = 0;
1810
1811         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1812
1813         mark_runtime_wc(chip, azx_dev, runtime, false);
1814         return snd_pcm_lib_free_pages(substream);
1815 }
1816
1817 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1818 {
1819         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1820         struct azx *chip = apcm->chip;
1821         struct azx_dev *azx_dev = get_azx_dev(substream);
1822         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1823         struct snd_pcm_runtime *runtime = substream->runtime;
1824         unsigned int bufsize, period_bytes, format_val, stream_tag;
1825         int err;
1826         struct hda_spdif_out *spdif =
1827                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1828         unsigned short ctls = spdif ? spdif->ctls : 0;
1829
1830         azx_stream_reset(chip, azx_dev);
1831         format_val = snd_hda_calc_stream_format(runtime->rate,
1832                                                 runtime->channels,
1833                                                 runtime->format,
1834                                                 hinfo->maxbps,
1835                                                 ctls);
1836         if (!format_val) {
1837                 snd_printk(KERN_ERR SFX
1838                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1839                            runtime->rate, runtime->channels, runtime->format);
1840                 return -EINVAL;
1841         }
1842
1843         bufsize = snd_pcm_lib_buffer_bytes(substream);
1844         period_bytes = snd_pcm_lib_period_bytes(substream);
1845
1846         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1847                     bufsize, format_val);
1848
1849         if (bufsize != azx_dev->bufsize ||
1850             period_bytes != azx_dev->period_bytes ||
1851             format_val != azx_dev->format_val) {
1852                 azx_dev->bufsize = bufsize;
1853                 azx_dev->period_bytes = period_bytes;
1854                 azx_dev->format_val = format_val;
1855                 err = azx_setup_periods(chip, substream, azx_dev);
1856                 if (err < 0)
1857                         return err;
1858         }
1859
1860         /* wallclk has 24Mhz clock source */
1861         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1862                                                 runtime->rate) * 1000);
1863         azx_setup_controller(chip, azx_dev);
1864         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1865                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1866         else
1867                 azx_dev->fifo_size = 0;
1868
1869         stream_tag = azx_dev->stream_tag;
1870         /* CA-IBG chips need the playback stream starting from 1 */
1871         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1872             stream_tag > chip->capture_streams)
1873                 stream_tag -= chip->capture_streams;
1874         return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1875                                      azx_dev->format_val, substream);
1876 }
1877
1878 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1879 {
1880         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1881         struct azx *chip = apcm->chip;
1882         struct azx_dev *azx_dev;
1883         struct snd_pcm_substream *s;
1884         int rstart = 0, start, nsync = 0, sbits = 0;
1885         int nwait, timeout;
1886
1887         switch (cmd) {
1888         case SNDRV_PCM_TRIGGER_START:
1889                 rstart = 1;
1890         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1891         case SNDRV_PCM_TRIGGER_RESUME:
1892                 start = 1;
1893                 break;
1894         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1895         case SNDRV_PCM_TRIGGER_SUSPEND:
1896         case SNDRV_PCM_TRIGGER_STOP:
1897                 start = 0;
1898                 break;
1899         default:
1900                 return -EINVAL;
1901         }
1902
1903         snd_pcm_group_for_each_entry(s, substream) {
1904                 if (s->pcm->card != substream->pcm->card)
1905                         continue;
1906                 azx_dev = get_azx_dev(s);
1907                 sbits |= 1 << azx_dev->index;
1908                 nsync++;
1909                 snd_pcm_trigger_done(s, substream);
1910         }
1911
1912         spin_lock(&chip->reg_lock);
1913         if (nsync > 1) {
1914                 /* first, set SYNC bits of corresponding streams */
1915                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1916                         azx_writel(chip, OLD_SSYNC,
1917                                    azx_readl(chip, OLD_SSYNC) | sbits);
1918                 else
1919                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1920         }
1921         snd_pcm_group_for_each_entry(s, substream) {
1922                 if (s->pcm->card != substream->pcm->card)
1923                         continue;
1924                 azx_dev = get_azx_dev(s);
1925                 if (start) {
1926                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1927                         if (!rstart)
1928                                 azx_dev->start_wallclk -=
1929                                                 azx_dev->period_wallclk;
1930                         azx_stream_start(chip, azx_dev);
1931                 } else {
1932                         azx_stream_stop(chip, azx_dev);
1933                 }
1934                 azx_dev->running = start;
1935         }
1936         spin_unlock(&chip->reg_lock);
1937         if (start) {
1938                 if (nsync == 1)
1939                         return 0;
1940                 /* wait until all FIFOs get ready */
1941                 for (timeout = 5000; timeout; timeout--) {
1942                         nwait = 0;
1943                         snd_pcm_group_for_each_entry(s, substream) {
1944                                 if (s->pcm->card != substream->pcm->card)
1945                                         continue;
1946                                 azx_dev = get_azx_dev(s);
1947                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1948                                       SD_STS_FIFO_READY))
1949                                         nwait++;
1950                         }
1951                         if (!nwait)
1952                                 break;
1953                         cpu_relax();
1954                 }
1955         } else {
1956                 /* wait until all RUN bits are cleared */
1957                 for (timeout = 5000; timeout; timeout--) {
1958                         nwait = 0;
1959                         snd_pcm_group_for_each_entry(s, substream) {
1960                                 if (s->pcm->card != substream->pcm->card)
1961                                         continue;
1962                                 azx_dev = get_azx_dev(s);
1963                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1964                                     SD_CTL_DMA_START)
1965                                         nwait++;
1966                         }
1967                         if (!nwait)
1968                                 break;
1969                         cpu_relax();
1970                 }
1971         }
1972         if (nsync > 1) {
1973                 spin_lock(&chip->reg_lock);
1974                 /* reset SYNC bits */
1975                 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1976                         azx_writel(chip, OLD_SSYNC,
1977                                    azx_readl(chip, OLD_SSYNC) & ~sbits);
1978                 else
1979                         azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1980                 spin_unlock(&chip->reg_lock);
1981         }
1982         return 0;
1983 }
1984
1985 /* get the current DMA position with correction on VIA chips */
1986 static unsigned int azx_via_get_position(struct azx *chip,
1987                                          struct azx_dev *azx_dev)
1988 {
1989         unsigned int link_pos, mini_pos, bound_pos;
1990         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1991         unsigned int fifo_size;
1992
1993         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1994         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1995                 /* Playback, no problem using link position */
1996                 return link_pos;
1997         }
1998
1999         /* Capture */
2000         /* For new chipset,
2001          * use mod to get the DMA position just like old chipset
2002          */
2003         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2004         mod_dma_pos %= azx_dev->period_bytes;
2005
2006         /* azx_dev->fifo_size can't get FIFO size of in stream.
2007          * Get from base address + offset.
2008          */
2009         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2010
2011         if (azx_dev->insufficient) {
2012                 /* Link position never gather than FIFO size */
2013                 if (link_pos <= fifo_size)
2014                         return 0;
2015
2016                 azx_dev->insufficient = 0;
2017         }
2018
2019         if (link_pos <= fifo_size)
2020                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2021         else
2022                 mini_pos = link_pos - fifo_size;
2023
2024         /* Find nearest previous boudary */
2025         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2026         mod_link_pos = link_pos % azx_dev->period_bytes;
2027         if (mod_link_pos >= fifo_size)
2028                 bound_pos = link_pos - mod_link_pos;
2029         else if (mod_dma_pos >= mod_mini_pos)
2030                 bound_pos = mini_pos - mod_mini_pos;
2031         else {
2032                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2033                 if (bound_pos >= azx_dev->bufsize)
2034                         bound_pos = 0;
2035         }
2036
2037         /* Calculate real DMA position we want */
2038         return bound_pos + mod_dma_pos;
2039 }
2040
2041 static unsigned int azx_get_position(struct azx *chip,
2042                                      struct azx_dev *azx_dev,
2043                                      bool with_check)
2044 {
2045         unsigned int pos;
2046         int stream = azx_dev->substream->stream;
2047
2048         switch (chip->position_fix[stream]) {
2049         case POS_FIX_LPIB:
2050                 /* read LPIB */
2051                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2052                 break;
2053         case POS_FIX_VIACOMBO:
2054                 pos = azx_via_get_position(chip, azx_dev);
2055                 break;
2056         default:
2057                 /* use the position buffer */
2058                 pos = le32_to_cpu(*azx_dev->posbuf);
2059                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2060                         if (!pos || pos == (u32)-1) {
2061                                 printk(KERN_WARNING
2062                                        "hda-intel: Invalid position buffer, "
2063                                        "using LPIB read method instead.\n");
2064                                 chip->position_fix[stream] = POS_FIX_LPIB;
2065                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2066                         } else
2067                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2068                 }
2069                 break;
2070         }
2071
2072         if (pos >= azx_dev->bufsize)
2073                 pos = 0;
2074         return pos;
2075 }
2076
2077 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2078 {
2079         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2080         struct azx *chip = apcm->chip;
2081         struct azx_dev *azx_dev = get_azx_dev(substream);
2082         return bytes_to_frames(substream->runtime,
2083                                azx_get_position(chip, azx_dev, false));
2084 }
2085
2086 /*
2087  * Check whether the current DMA position is acceptable for updating
2088  * periods.  Returns non-zero if it's OK.
2089  *
2090  * Many HD-audio controllers appear pretty inaccurate about
2091  * the update-IRQ timing.  The IRQ is issued before actually the
2092  * data is processed.  So, we need to process it afterwords in a
2093  * workqueue.
2094  */
2095 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2096 {
2097         u32 wallclk;
2098         unsigned int pos;
2099         int stream;
2100
2101         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2102         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2103                 return -1;      /* bogus (too early) interrupt */
2104
2105         stream = azx_dev->substream->stream;
2106         pos = azx_get_position(chip, azx_dev, true);
2107
2108         if (WARN_ONCE(!azx_dev->period_bytes,
2109                       "hda-intel: zero azx_dev->period_bytes"))
2110                 return -1; /* this shouldn't happen! */
2111         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2112             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2113                 /* NG - it's below the first next period boundary */
2114                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2115         azx_dev->start_wallclk += wallclk;
2116         return 1; /* OK, it's fine */
2117 }
2118
2119 /*
2120  * The work for pending PCM period updates.
2121  */
2122 static void azx_irq_pending_work(struct work_struct *work)
2123 {
2124         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2125         int i, pending, ok;
2126
2127         if (!chip->irq_pending_warned) {
2128                 printk(KERN_WARNING
2129                        "hda-intel: IRQ timing workaround is activated "
2130                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2131                        chip->card->number);
2132                 chip->irq_pending_warned = 1;
2133         }
2134
2135         for (;;) {
2136                 pending = 0;
2137                 spin_lock_irq(&chip->reg_lock);
2138                 for (i = 0; i < chip->num_streams; i++) {
2139                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2140                         if (!azx_dev->irq_pending ||
2141                             !azx_dev->substream ||
2142                             !azx_dev->running)
2143                                 continue;
2144                         ok = azx_position_ok(chip, azx_dev);
2145                         if (ok > 0) {
2146                                 azx_dev->irq_pending = 0;
2147                                 spin_unlock(&chip->reg_lock);
2148                                 snd_pcm_period_elapsed(azx_dev->substream);
2149                                 spin_lock(&chip->reg_lock);
2150                         } else if (ok < 0) {
2151                                 pending = 0;    /* too early */
2152                         } else
2153                                 pending++;
2154                 }
2155                 spin_unlock_irq(&chip->reg_lock);
2156                 if (!pending)
2157                         return;
2158                 msleep(1);
2159         }
2160 }
2161
2162 /* clear irq_pending flags and assure no on-going workq */
2163 static void azx_clear_irq_pending(struct azx *chip)
2164 {
2165         int i;
2166
2167         spin_lock_irq(&chip->reg_lock);
2168         for (i = 0; i < chip->num_streams; i++)
2169                 chip->azx_dev[i].irq_pending = 0;
2170         spin_unlock_irq(&chip->reg_lock);
2171 }
2172
2173 #ifdef CONFIG_X86
2174 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2175                         struct vm_area_struct *area)
2176 {
2177         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2178         struct azx *chip = apcm->chip;
2179         if (!azx_snoop(chip))
2180                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2181         return snd_pcm_lib_default_mmap(substream, area);
2182 }
2183 #else
2184 #define azx_pcm_mmap    NULL
2185 #endif
2186
2187 static struct snd_pcm_ops azx_pcm_ops = {
2188         .open = azx_pcm_open,
2189         .close = azx_pcm_close,
2190         .ioctl = snd_pcm_lib_ioctl,
2191         .hw_params = azx_pcm_hw_params,
2192         .hw_free = azx_pcm_hw_free,
2193         .prepare = azx_pcm_prepare,
2194         .trigger = azx_pcm_trigger,
2195         .pointer = azx_pcm_pointer,
2196         .mmap = azx_pcm_mmap,
2197         .page = snd_pcm_sgbuf_ops_page,
2198 };
2199
2200 static void azx_pcm_free(struct snd_pcm *pcm)
2201 {
2202         struct azx_pcm *apcm = pcm->private_data;
2203         if (apcm) {
2204                 apcm->chip->pcm[pcm->device] = NULL;
2205                 kfree(apcm);
2206         }
2207 }
2208
2209 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2210
2211 static int
2212 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2213                       struct hda_pcm *cpcm)
2214 {
2215         struct azx *chip = bus->private_data;
2216         struct snd_pcm *pcm;
2217         struct azx_pcm *apcm;
2218         int pcm_dev = cpcm->device;
2219         unsigned int size;
2220         int s, err;
2221
2222         if (pcm_dev >= HDA_MAX_PCMS) {
2223                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2224                            pcm_dev);
2225                 return -EINVAL;
2226         }
2227         if (chip->pcm[pcm_dev]) {
2228                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2229                 return -EBUSY;
2230         }
2231         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2232                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2233                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2234                           &pcm);
2235         if (err < 0)
2236                 return err;
2237         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2238         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2239         if (apcm == NULL)
2240                 return -ENOMEM;
2241         apcm->chip = chip;
2242         apcm->codec = codec;
2243         pcm->private_data = apcm;
2244         pcm->private_free = azx_pcm_free;
2245         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2246                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2247         chip->pcm[pcm_dev] = pcm;
2248         cpcm->pcm = pcm;
2249         for (s = 0; s < 2; s++) {
2250                 apcm->hinfo[s] = &cpcm->stream[s];
2251                 if (cpcm->stream[s].substreams)
2252                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2253         }
2254         /* buffer pre-allocation */
2255         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2256         if (size > MAX_PREALLOC_SIZE)
2257                 size = MAX_PREALLOC_SIZE;
2258         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2259                                               snd_dma_pci_data(chip->pci),
2260                                               size, MAX_PREALLOC_SIZE);
2261         return 0;
2262 }
2263
2264 /*
2265  * mixer creation - all stuff is implemented in hda module
2266  */
2267 static int __devinit azx_mixer_create(struct azx *chip)
2268 {
2269         return snd_hda_build_controls(chip->bus);
2270 }
2271
2272
2273 /*
2274  * initialize SD streams
2275  */
2276 static int __devinit azx_init_stream(struct azx *chip)
2277 {
2278         int i;
2279
2280         /* initialize each stream (aka device)
2281          * assign the starting bdl address to each stream (device)
2282          * and initialize
2283          */
2284         for (i = 0; i < chip->num_streams; i++) {
2285                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2286                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2287                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2288                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2289                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2290                 azx_dev->sd_int_sta_mask = 1 << i;
2291                 /* stream tag: must be non-zero and unique */
2292                 azx_dev->index = i;
2293                 azx_dev->stream_tag = i + 1;
2294         }
2295
2296         return 0;
2297 }
2298
2299 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2300 {
2301         if (request_irq(chip->pci->irq, azx_interrupt,
2302                         chip->msi ? 0 : IRQF_SHARED,
2303                         KBUILD_MODNAME, chip)) {
2304                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2305                        "disabling device\n", chip->pci->irq);
2306                 if (do_disconnect)
2307                         snd_card_disconnect(chip->card);
2308                 return -1;
2309         }
2310         chip->irq = chip->pci->irq;
2311         pci_intx(chip->pci, !chip->msi);
2312         return 0;
2313 }
2314
2315
2316 static void azx_stop_chip(struct azx *chip)
2317 {
2318         if (!chip->initialized)
2319                 return;
2320
2321         /* disable interrupts */
2322         azx_int_disable(chip);
2323         azx_int_clear(chip);
2324
2325         /* disable CORB/RIRB */
2326         azx_free_cmd_io(chip);
2327
2328         /* disable position buffer */
2329         azx_writel(chip, DPLBASE, 0);
2330         azx_writel(chip, DPUBASE, 0);
2331
2332         chip->initialized = 0;
2333 }
2334
2335 #ifdef CONFIG_SND_HDA_POWER_SAVE
2336 /* power-up/down the controller */
2337 static void azx_power_notify(struct hda_bus *bus)
2338 {
2339         struct azx *chip = bus->private_data;
2340         struct hda_codec *c;
2341         int power_on = 0;
2342
2343         list_for_each_entry(c, &bus->codec_list, list) {
2344                 if (c->power_on) {
2345                         power_on = 1;
2346                         break;
2347                 }
2348         }
2349         if (power_on)
2350                 azx_init_chip(chip, 1);
2351         else if (chip->running && power_save_controller &&
2352                  !bus->power_keep_link_on)
2353                 azx_stop_chip(chip);
2354 }
2355 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2356
2357 #ifdef CONFIG_PM
2358 /*
2359  * power management
2360  */
2361
2362 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2363 {
2364         struct hda_codec *codec;
2365
2366         list_for_each_entry(codec, &bus->codec_list, list) {
2367                 if (snd_hda_codec_needs_resume(codec))
2368                         return 1;
2369         }
2370         return 0;
2371 }
2372
2373 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2374 {
2375         struct snd_card *card = pci_get_drvdata(pci);
2376         struct azx *chip = card->private_data;
2377         int i;
2378
2379         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2380         azx_clear_irq_pending(chip);
2381         for (i = 0; i < HDA_MAX_PCMS; i++)
2382                 snd_pcm_suspend_all(chip->pcm[i]);
2383         if (chip->initialized)
2384                 snd_hda_suspend(chip->bus);
2385         azx_stop_chip(chip);
2386         if (chip->irq >= 0) {
2387                 free_irq(chip->irq, chip);
2388                 chip->irq = -1;
2389         }
2390         if (chip->msi)
2391                 pci_disable_msi(chip->pci);
2392         pci_disable_device(pci);
2393         pci_save_state(pci);
2394         pci_set_power_state(pci, pci_choose_state(pci, state));
2395         return 0;
2396 }
2397
2398 static int azx_resume(struct pci_dev *pci)
2399 {
2400         struct snd_card *card = pci_get_drvdata(pci);
2401         struct azx *chip = card->private_data;
2402
2403         pci_set_power_state(pci, PCI_D0);
2404         pci_restore_state(pci);
2405         if (pci_enable_device(pci) < 0) {
2406                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2407                        "disabling device\n");
2408                 snd_card_disconnect(card);
2409                 return -EIO;
2410         }
2411         pci_set_master(pci);
2412         if (chip->msi)
2413                 if (pci_enable_msi(pci) < 0)
2414                         chip->msi = 0;
2415         if (azx_acquire_irq(chip, 1) < 0)
2416                 return -EIO;
2417         azx_init_pci(chip);
2418
2419         if (snd_hda_codecs_inuse(chip->bus))
2420                 azx_init_chip(chip, 1);
2421
2422         snd_hda_resume(chip->bus);
2423         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2424         return 0;
2425 }
2426 #endif /* CONFIG_PM */
2427
2428
2429 /*
2430  * reboot notifier for hang-up problem at power-down
2431  */
2432 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2433 {
2434         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2435         snd_hda_bus_reboot_notify(chip->bus);
2436         azx_stop_chip(chip);
2437         return NOTIFY_OK;
2438 }
2439
2440 static void azx_notifier_register(struct azx *chip)
2441 {
2442         chip->reboot_notifier.notifier_call = azx_halt;
2443         register_reboot_notifier(&chip->reboot_notifier);
2444 }
2445
2446 static void azx_notifier_unregister(struct azx *chip)
2447 {
2448         if (chip->reboot_notifier.notifier_call)
2449                 unregister_reboot_notifier(&chip->reboot_notifier);
2450 }
2451
2452 /*
2453  * destructor
2454  */
2455 static int azx_free(struct azx *chip)
2456 {
2457         int i;
2458
2459         azx_notifier_unregister(chip);
2460
2461         if (chip->initialized) {
2462                 azx_clear_irq_pending(chip);
2463                 for (i = 0; i < chip->num_streams; i++)
2464                         azx_stream_stop(chip, &chip->azx_dev[i]);
2465                 azx_stop_chip(chip);
2466         }
2467
2468         if (chip->irq >= 0)
2469                 free_irq(chip->irq, (void*)chip);
2470         if (chip->msi)
2471                 pci_disable_msi(chip->pci);
2472         if (chip->remap_addr)
2473                 iounmap(chip->remap_addr);
2474
2475         if (chip->azx_dev) {
2476                 for (i = 0; i < chip->num_streams; i++)
2477                         if (chip->azx_dev[i].bdl.area) {
2478                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2479                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2480                         }
2481         }
2482         if (chip->rb.area) {
2483                 mark_pages_wc(chip, &chip->rb, false);
2484                 snd_dma_free_pages(&chip->rb);
2485         }
2486         if (chip->posbuf.area) {
2487                 mark_pages_wc(chip, &chip->posbuf, false);
2488                 snd_dma_free_pages(&chip->posbuf);
2489         }
2490         pci_release_regions(chip->pci);
2491         pci_disable_device(chip->pci);
2492         kfree(chip->azx_dev);
2493         kfree(chip);
2494
2495         return 0;
2496 }
2497
2498 static int azx_dev_free(struct snd_device *device)
2499 {
2500         return azx_free(device->device_data);
2501 }
2502
2503 /*
2504  * white/black-listing for position_fix
2505  */
2506 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2507         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2508         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2509         SND_PCI_QUIRK(0x1028, 0x02c6, "Dell Inspiron 1010", POS_FIX_LPIB),
2510         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2511         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2512         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2513         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2514         SND_PCI_QUIRK(0x1043, 0x83ce, "ASUS 1101HA", POS_FIX_LPIB),
2515         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2516         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2517         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2518         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2519         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2520         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2521         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2522         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2523         {}
2524 };
2525
2526 static int __devinit check_position_fix(struct azx *chip, int fix)
2527 {
2528         const struct snd_pci_quirk *q;
2529
2530         switch (fix) {
2531         case POS_FIX_LPIB:
2532         case POS_FIX_POSBUF:
2533         case POS_FIX_VIACOMBO:
2534                 return fix;
2535         }
2536
2537         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2538         if (q) {
2539                 printk(KERN_INFO
2540                        "hda_intel: position_fix set to %d "
2541                        "for device %04x:%04x\n",
2542                        q->value, q->subvendor, q->subdevice);
2543                 return q->value;
2544         }
2545
2546         /* Check VIA/ATI HD Audio Controller exist */
2547         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2548                 snd_printd(SFX "Using VIACOMBO position fix\n");
2549                 return POS_FIX_VIACOMBO;
2550         }
2551         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2552                 snd_printd(SFX "Using LPIB position fix\n");
2553                 return POS_FIX_LPIB;
2554         }
2555         return POS_FIX_AUTO;
2556 }
2557
2558 /*
2559  * black-lists for probe_mask
2560  */
2561 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2562         /* Thinkpad often breaks the controller communication when accessing
2563          * to the non-working (or non-existing) modem codec slot.
2564          */
2565         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2566         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2567         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2568         /* broken BIOS */
2569         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2570         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2571         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2572         /* forced codec slots */
2573         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2574         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2575         {}
2576 };
2577
2578 #define AZX_FORCE_CODEC_MASK    0x100
2579
2580 static void __devinit check_probe_mask(struct azx *chip, int dev)
2581 {
2582         const struct snd_pci_quirk *q;
2583
2584         chip->codec_probe_mask = probe_mask[dev];
2585         if (chip->codec_probe_mask == -1) {
2586                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2587                 if (q) {
2588                         printk(KERN_INFO
2589                                "hda_intel: probe_mask set to 0x%x "
2590                                "for device %04x:%04x\n",
2591                                q->value, q->subvendor, q->subdevice);
2592                         chip->codec_probe_mask = q->value;
2593                 }
2594         }
2595
2596         /* check forced option */
2597         if (chip->codec_probe_mask != -1 &&
2598             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2599                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2600                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2601                        chip->codec_mask);
2602         }
2603 }
2604
2605 /*
2606  * white/black-list for enable_msi
2607  */
2608 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2609         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2610         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2611         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2612         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2613         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2614         {}
2615 };
2616
2617 static void __devinit check_msi(struct azx *chip)
2618 {
2619         const struct snd_pci_quirk *q;
2620
2621         if (enable_msi >= 0) {
2622                 chip->msi = !!enable_msi;
2623                 return;
2624         }
2625         chip->msi = 1;  /* enable MSI as default */
2626         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2627         if (q) {
2628                 printk(KERN_INFO
2629                        "hda_intel: msi for device %04x:%04x set to %d\n",
2630                        q->subvendor, q->subdevice, q->value);
2631                 chip->msi = q->value;
2632                 return;
2633         }
2634
2635         /* NVidia chipsets seem to cause troubles with MSI */
2636         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2637                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2638                 chip->msi = 0;
2639         }
2640 }
2641
2642
2643 /*
2644  * constructor
2645  */
2646 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2647                                 int dev, unsigned int driver_caps,
2648                                 struct azx **rchip)
2649 {
2650         struct azx *chip;
2651         int i, err;
2652         unsigned short gcap;
2653         static struct snd_device_ops ops = {
2654                 .dev_free = azx_dev_free,
2655         };
2656
2657         *rchip = NULL;
2658
2659         err = pci_enable_device(pci);
2660         if (err < 0)
2661                 return err;
2662
2663         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2664         if (!chip) {
2665                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2666                 pci_disable_device(pci);
2667                 return -ENOMEM;
2668         }
2669
2670         spin_lock_init(&chip->reg_lock);
2671         mutex_init(&chip->open_mutex);
2672         chip->card = card;
2673         chip->pci = pci;
2674         chip->irq = -1;
2675         chip->driver_caps = driver_caps;
2676         chip->driver_type = driver_caps & 0xff;
2677         check_msi(chip);
2678         chip->dev_index = dev;
2679         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2680
2681         chip->position_fix[0] = chip->position_fix[1] =
2682                 check_position_fix(chip, position_fix[dev]);
2683         check_probe_mask(chip, dev);
2684
2685         chip->single_cmd = single_cmd;
2686         chip->snoop = hda_snoop;
2687
2688         if (bdl_pos_adj[dev] < 0) {
2689                 switch (chip->driver_type) {
2690                 case AZX_DRIVER_ICH:
2691                 case AZX_DRIVER_PCH:
2692                         bdl_pos_adj[dev] = 1;
2693                         break;
2694                 default:
2695                         bdl_pos_adj[dev] = 32;
2696                         break;
2697                 }
2698         }
2699
2700 #if BITS_PER_LONG != 64
2701         /* Fix up base address on ULI M5461 */
2702         if (chip->driver_type == AZX_DRIVER_ULI) {
2703                 u16 tmp3;
2704                 pci_read_config_word(pci, 0x40, &tmp3);
2705                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2706                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2707         }
2708 #endif
2709
2710         err = pci_request_regions(pci, "ICH HD audio");
2711         if (err < 0) {
2712                 kfree(chip);
2713                 pci_disable_device(pci);
2714                 return err;
2715         }
2716
2717         chip->addr = pci_resource_start(pci, 0);
2718         chip->remap_addr = pci_ioremap_bar(pci, 0);
2719         if (chip->remap_addr == NULL) {
2720                 snd_printk(KERN_ERR SFX "ioremap error\n");
2721                 err = -ENXIO;
2722                 goto errout;
2723         }
2724
2725         if (chip->msi)
2726                 if (pci_enable_msi(pci) < 0)
2727                         chip->msi = 0;
2728
2729         if (azx_acquire_irq(chip, 0) < 0) {
2730                 err = -EBUSY;
2731                 goto errout;
2732         }
2733
2734         pci_set_master(pci);
2735         synchronize_irq(chip->irq);
2736
2737         gcap = azx_readw(chip, GCAP);
2738         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2739
2740         /* disable SB600 64bit support for safety */
2741         if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2742                 struct pci_dev *p_smbus;
2743                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2744                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2745                                          NULL);
2746                 if (p_smbus) {
2747                         if (p_smbus->revision < 0x30)
2748                                 gcap &= ~ICH6_GCAP_64OK;
2749                         pci_dev_put(p_smbus);
2750                 }
2751         }
2752
2753         /* disable 64bit DMA address on some devices */
2754         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2755                 snd_printd(SFX "Disabling 64bit DMA\n");
2756                 gcap &= ~ICH6_GCAP_64OK;
2757         }
2758
2759         /* disable buffer size rounding to 128-byte multiples if supported */
2760         chip->align_buffer_size = align_buffer_size;
2761         if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2762                 chip->align_buffer_size = 0;
2763
2764         /* allow 64bit DMA address if supported by H/W */
2765         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2766                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2767         else {
2768                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2769                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2770         }
2771
2772         /* read number of streams from GCAP register instead of using
2773          * hardcoded value
2774          */
2775         chip->capture_streams = (gcap >> 8) & 0x0f;
2776         chip->playback_streams = (gcap >> 12) & 0x0f;
2777         if (!chip->playback_streams && !chip->capture_streams) {
2778                 /* gcap didn't give any info, switching to old method */
2779
2780                 switch (chip->driver_type) {
2781                 case AZX_DRIVER_ULI:
2782                         chip->playback_streams = ULI_NUM_PLAYBACK;
2783                         chip->capture_streams = ULI_NUM_CAPTURE;
2784                         break;
2785                 case AZX_DRIVER_ATIHDMI:
2786                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2787                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2788                         break;
2789                 case AZX_DRIVER_GENERIC:
2790                 default:
2791                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2792                         chip->capture_streams = ICH6_NUM_CAPTURE;
2793                         break;
2794                 }
2795         }
2796         chip->capture_index_offset = 0;
2797         chip->playback_index_offset = chip->capture_streams;
2798         chip->num_streams = chip->playback_streams + chip->capture_streams;
2799         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2800                                 GFP_KERNEL);
2801         if (!chip->azx_dev) {
2802                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2803                 goto errout;
2804         }
2805
2806         for (i = 0; i < chip->num_streams; i++) {
2807                 /* allocate memory for the BDL for each stream */
2808                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2809                                           snd_dma_pci_data(chip->pci),
2810                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2811                 if (err < 0) {
2812                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2813                         goto errout;
2814                 }
2815                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2816         }
2817         /* allocate memory for the position buffer */
2818         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2819                                   snd_dma_pci_data(chip->pci),
2820                                   chip->num_streams * 8, &chip->posbuf);
2821         if (err < 0) {
2822                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2823                 goto errout;
2824         }
2825         mark_pages_wc(chip, &chip->posbuf, true);
2826         /* allocate CORB/RIRB */
2827         err = azx_alloc_cmd_io(chip);
2828         if (err < 0)
2829                 goto errout;
2830
2831         /* initialize streams */
2832         azx_init_stream(chip);
2833
2834         /* initialize chip */
2835         azx_init_pci(chip);
2836         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2837
2838         /* codec detection */
2839         if (!chip->codec_mask) {
2840                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2841                 err = -ENODEV;
2842                 goto errout;
2843         }
2844
2845         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2846         if (err <0) {
2847                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2848                 goto errout;
2849         }
2850
2851         strcpy(card->driver, "HDA-Intel");
2852         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2853                 sizeof(card->shortname));
2854         snprintf(card->longname, sizeof(card->longname),
2855                  "%s at 0x%lx irq %i",
2856                  card->shortname, chip->addr, chip->irq);
2857
2858         *rchip = chip;
2859         return 0;
2860
2861  errout:
2862         azx_free(chip);
2863         return err;
2864 }
2865
2866 static void power_down_all_codecs(struct azx *chip)
2867 {
2868 #ifdef CONFIG_SND_HDA_POWER_SAVE
2869         /* The codecs were powered up in snd_hda_codec_new().
2870          * Now all initialization done, so turn them down if possible
2871          */
2872         struct hda_codec *codec;
2873         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2874                 snd_hda_power_down(codec);
2875         }
2876 #endif
2877 }
2878
2879 static int __devinit azx_probe(struct pci_dev *pci,
2880                                const struct pci_device_id *pci_id)
2881 {
2882         static int dev;
2883         struct snd_card *card;
2884         struct azx *chip;
2885         int err;
2886
2887         if (dev >= SNDRV_CARDS)
2888                 return -ENODEV;
2889         if (!enable[dev]) {
2890                 dev++;
2891                 return -ENOENT;
2892         }
2893
2894         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2895         if (err < 0) {
2896                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2897                 return err;
2898         }
2899
2900         /* set this here since it's referred in snd_hda_load_patch() */
2901         snd_card_set_dev(card, &pci->dev);
2902
2903         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2904         if (err < 0)
2905                 goto out_free;
2906         card->private_data = chip;
2907
2908 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2909         chip->beep_mode = beep_mode[dev];
2910 #endif
2911
2912         /* create codec instances */
2913         err = azx_codec_create(chip, model[dev]);
2914         if (err < 0)
2915                 goto out_free;
2916 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2917         if (patch[dev] && *patch[dev]) {
2918                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2919                            patch[dev]);
2920                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2921                 if (err < 0)
2922                         goto out_free;
2923         }
2924 #endif
2925         if ((probe_only[dev] & 1) == 0) {
2926                 err = azx_codec_configure(chip);
2927                 if (err < 0)
2928                         goto out_free;
2929         }
2930
2931         /* create PCM streams */
2932         err = snd_hda_build_pcms(chip->bus);
2933         if (err < 0)
2934                 goto out_free;
2935
2936         /* create mixer controls */
2937         err = azx_mixer_create(chip);
2938         if (err < 0)
2939                 goto out_free;
2940
2941         err = snd_card_register(card);
2942         if (err < 0)
2943                 goto out_free;
2944
2945         pci_set_drvdata(pci, card);
2946         chip->running = 1;
2947         power_down_all_codecs(chip);
2948         azx_notifier_register(chip);
2949
2950         dev++;
2951         return err;
2952 out_free:
2953         snd_card_free(card);
2954         return err;
2955 }
2956
2957 static void __devexit azx_remove(struct pci_dev *pci)
2958 {
2959         snd_card_free(pci_get_drvdata(pci));
2960         pci_set_drvdata(pci, NULL);
2961 }
2962
2963 /* PCI IDs */
2964 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2965         /* CPT */
2966         { PCI_DEVICE(0x8086, 0x1c20),
2967           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2968           AZX_DCAPS_BUFSIZE },
2969         /* PBG */
2970         { PCI_DEVICE(0x8086, 0x1d20),
2971           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2972           AZX_DCAPS_BUFSIZE},
2973         /* Panther Point */
2974         { PCI_DEVICE(0x8086, 0x1e20),
2975           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2976           AZX_DCAPS_BUFSIZE},
2977         /* Lynx Point */
2978         { PCI_DEVICE(0x8086, 0x8c20),
2979           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2980           AZX_DCAPS_BUFSIZE},
2981         /* SCH */
2982         { PCI_DEVICE(0x8086, 0x811b),
2983           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2984           AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB }, /* Poulsbo */
2985         /* ICH */
2986         { PCI_DEVICE(0x8086, 0x2668),
2987           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2988           AZX_DCAPS_BUFSIZE },  /* ICH6 */
2989         { PCI_DEVICE(0x8086, 0x27d8),
2990           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2991           AZX_DCAPS_BUFSIZE },  /* ICH7 */
2992         { PCI_DEVICE(0x8086, 0x269a),
2993           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2994           AZX_DCAPS_BUFSIZE },  /* ESB2 */
2995         { PCI_DEVICE(0x8086, 0x284b),
2996           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2997           AZX_DCAPS_BUFSIZE },  /* ICH8 */
2998         { PCI_DEVICE(0x8086, 0x293e),
2999           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3000           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3001         { PCI_DEVICE(0x8086, 0x293f),
3002           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3003           AZX_DCAPS_BUFSIZE },  /* ICH9 */
3004         { PCI_DEVICE(0x8086, 0x3a3e),
3005           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3006           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3007         { PCI_DEVICE(0x8086, 0x3a6e),
3008           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3009           AZX_DCAPS_BUFSIZE },  /* ICH10 */
3010         /* Generic Intel */
3011         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3012           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3013           .class_mask = 0xffffff,
3014           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3015         /* ATI SB 450/600/700/800/900 */
3016         { PCI_DEVICE(0x1002, 0x437b),
3017           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3018         { PCI_DEVICE(0x1002, 0x4383),
3019           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3020         /* AMD Hudson */
3021         { PCI_DEVICE(0x1022, 0x780d),
3022           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3023         /* ATI HDMI */
3024         { PCI_DEVICE(0x1002, 0x793b),
3025           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3026         { PCI_DEVICE(0x1002, 0x7919),
3027           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3028         { PCI_DEVICE(0x1002, 0x960f),
3029           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3030         { PCI_DEVICE(0x1002, 0x970f),
3031           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3032         { PCI_DEVICE(0x1002, 0xaa00),
3033           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3034         { PCI_DEVICE(0x1002, 0xaa08),
3035           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3036         { PCI_DEVICE(0x1002, 0xaa10),
3037           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3038         { PCI_DEVICE(0x1002, 0xaa18),
3039           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3040         { PCI_DEVICE(0x1002, 0xaa20),
3041           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3042         { PCI_DEVICE(0x1002, 0xaa28),
3043           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3044         { PCI_DEVICE(0x1002, 0xaa30),
3045           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3046         { PCI_DEVICE(0x1002, 0xaa38),
3047           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3048         { PCI_DEVICE(0x1002, 0xaa40),
3049           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3050         { PCI_DEVICE(0x1002, 0xaa48),
3051           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3052         /* VIA VT8251/VT8237A */
3053         { PCI_DEVICE(0x1106, 0x3288),
3054           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3055         /* SIS966 */
3056         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3057         /* ULI M5461 */
3058         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3059         /* NVIDIA MCP */
3060         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3061           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3062           .class_mask = 0xffffff,
3063           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3064         /* Teradici */
3065         { PCI_DEVICE(0x6549, 0x1200),
3066           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3067         /* Creative X-Fi (CA0110-IBG) */
3068 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3069         /* the following entry conflicts with snd-ctxfi driver,
3070          * as ctxfi driver mutates from HD-audio to native mode with
3071          * a special command sequence.
3072          */
3073         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3074           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3075           .class_mask = 0xffffff,
3076           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3077           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3078 #else
3079         /* this entry seems still valid -- i.e. without emu20kx chip */
3080         { PCI_DEVICE(0x1102, 0x0009),
3081           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3082           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3083 #endif
3084         /* Vortex86MX */
3085         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3086         /* VMware HDAudio */
3087         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3088         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
3089         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3090           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3091           .class_mask = 0xffffff,
3092           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3093         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3094           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3095           .class_mask = 0xffffff,
3096           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3097         { 0, }
3098 };
3099 MODULE_DEVICE_TABLE(pci, azx_ids);
3100
3101 /* pci_driver definition */
3102 static struct pci_driver driver = {
3103         .name = KBUILD_MODNAME,
3104         .id_table = azx_ids,
3105         .probe = azx_probe,
3106         .remove = __devexit_p(azx_remove),
3107 #ifdef CONFIG_PM
3108         .suspend = azx_suspend,
3109         .resume = azx_resume,
3110 #endif
3111 };
3112
3113 static int __init alsa_card_azx_init(void)
3114 {
3115         return pci_register_driver(&driver);
3116 }
3117
3118 static void __exit alsa_card_azx_exit(void)
3119 {
3120         pci_unregister_driver(&driver);
3121 }
3122
3123 module_init(alsa_card_azx_init)
3124 module_exit(alsa_card_azx_exit)