sound/pci/cs46xx/cs46xx_lib.c

   1 /*
   2  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
   3  *                   Abramo Bagnara <abramo@alsa-project.org>
   4  *                   Cirrus Logic, Inc.
   5  *  Routines for control of Cirrus Logic CS461x chips
   6  *
   7  *  KNOWN BUGS:
   8  *    - Sometimes the SPDIF input DSP tasks get's unsynchronized
   9  *      and the SPDIF get somewhat "distorcionated", or/and left right channel
  10  *      are swapped. To get around this problem when it happens, mute and unmute
  11  *      the SPDIF input mixer control.
  12  *    - On the Hercules Game Theater XP the amplifier are sometimes turned
  13  *      off on inadecuate moments which causes distorcions on sound.
  14  *
  15  *  TODO:
  16  *    - Secondary CODEC on some soundcards
  17  *    - SPDIF input support for other sample rates then 48khz
  18  *    - Posibility to mix the SPDIF output with analog sources.
  19  *    - PCM channels for Center and LFE on secondary codec
  20  *
  21  *  NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  22  *        is default configuration), no SPDIF, no secondary codec, no
  23  *        multi channel PCM.  But known to work.
  24  *
  25  *  FINALLY: A credit to the developers Tom and Jordan
  26  *           at Cirrus for have helping me out with the DSP, however we
  27  *           still don't have sufficient documentation and technical
  28  *           references to be able to implement all fancy feutures
  29  *           supported by the cs46xx DSP's.
  30  *           Benny <benny@hostmobility.com>
  31  *
  32  *   This program is free software; you can redistribute it and/or modify
  33  *   it under the terms of the GNU General Public License as published by
  34  *   the Free Software Foundation; either version 2 of the License, or
  35  *   (at your option) any later version.
  36  *
  37  *   This program is distributed in the hope that it will be useful,
  38  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  39  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  40  *   GNU General Public License for more details.
  41  *
  42  *   You should have received a copy of the GNU General Public License
  43  *   along with this program; if not, write to the Free Software
  44  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  45  *
  46  */
  47
  48 #include <linux/delay.h>
  49 #include <linux/pci.h>
  50 #include <linux/pm.h>
  51 #include <linux/init.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/slab.h>
  54 #include <linux/gameport.h>
  55 #include <linux/mutex.h>
  56 #include <linux/export.h>
  57
  58
  59 #include <sound/core.h>
  60 #include <sound/control.h>
  61 #include <sound/info.h>
  62 #include <sound/pcm.h>
  63 #include <sound/pcm_params.h>
  64 #include "cs46xx.h"
  65
  66 #include <asm/io.h>
  67
  68 #include "cs46xx_lib.h"
  69 #include "dsp_spos.h"
  70
  71 static void amp_voyetra(struct snd_cs46xx *chip, int change);
  72
  73 #ifdef CONFIG_SND_CS46XX_NEW_DSP
  74 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
  75 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
  76 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
  77 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
  78 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
  79 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
  80 #endif
  81
  82 static struct snd_pcm_ops snd_cs46xx_playback_ops;
  83 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
  84 static struct snd_pcm_ops snd_cs46xx_capture_ops;
  85 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
  86
  87 static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
  88                                             unsigned short reg,
  89                                             int codec_index)
  90 {
  91         int count;
  92         unsigned short result,tmp;
  93         u32 offset = 0;
  94
  95         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
  96                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
  97                 return -EINVAL;
  98
  99         chip->active_ctrl(chip, 1);
 100
 101         if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
 102                 offset = CS46XX_SECONDARY_CODEC_OFFSET;
 103
 104         /*
 105          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 106          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 107          *  3. Write ACCTL = Control Register = 460h for initiating the write7---55
 108          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 109          *  5. if DCV not cleared, break and return error
 110          *  6. Read ACSTS = Status Register = 464h, check VSTS bit
 111          */
 112
 113         snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 114
 115         tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 116         if ((tmp & ACCTL_VFRM) == 0) {
 117                 snd_printk(KERN_WARNING  "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
 118                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
 119                 msleep(50);
 120                 tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
 121                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
 122
 123         }
 124
 125         /*
 126          *  Setup the AC97 control registers on the CS461x to send the
 127          *  appropriate command to the AC97 to perform the read.
 128          *  ACCAD = Command Address Register = 46Ch
 129          *  ACCDA = Command Data Register = 470h
 130          *  ACCTL = Control Register = 460h
 131          *  set DCV - will clear when process completed
 132          *  set CRW - Read command
 133          *  set VFRM - valid frame enabled
 134          *  set ESYN - ASYNC generation enabled
 135          *  set RSTN - ARST# inactive, AC97 codec not reset
 136          */
 137
 138         snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
 139         snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
 140         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 141                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
 142                                    ACCTL_VFRM | ACCTL_ESYN |
 143                                    ACCTL_RSTN);
 144                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
 145                                    ACCTL_VFRM | ACCTL_ESYN |
 146                                    ACCTL_RSTN);
 147         } else {
 148                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 149                                    ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
 150                                    ACCTL_RSTN);
 151         }
 152
 153         /*
 154          *  Wait for the read to occur.
 155          */
 156         for (count = 0; count < 1000; count++) {
 157                 /*
 158                  *  First, we want to wait for a short time.
 159                  */
 160                 udelay(10);
 161                 /*
 162                  *  Now, check to see if the read has completed.
 163                  *  ACCTL = 460h, DCV should be reset by now and 460h = 17h
 164                  */
 165                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
 166                         goto ok1;
 167         }
 168
 169         snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
 170         result = 0xffff;
 171         goto end;
 172
 173  ok1:
 174         /*
 175          *  Wait for the valid status bit to go active.
 176          */
 177         for (count = 0; count < 100; count++) {
 178                 /*
 179                  *  Read the AC97 status register.
 180                  *  ACSTS = Status Register = 464h
 181                  *  VSTS - Valid Status
 182                  */
 183                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
 184                         goto ok2;
 185                 udelay(10);
 186         }
 187
 188         snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
 189         result = 0xffff;
 190         goto end;
 191
 192  ok2:
 193         /*
 194          *  Read the data returned from the AC97 register.
 195          *  ACSDA = Status Data Register = 474h
 196          */
 197 #if 0
 198         printk(KERN_DEBUG "e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
 199                         snd_cs46xx_peekBA0(chip, BA0_ACSDA),
 200                         snd_cs46xx_peekBA0(chip, BA0_ACCAD));
 201 #endif
 202
 203         //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
 204         result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
 205  end:
 206         chip->active_ctrl(chip, -1);
 207         return result;
 208 }
 209
 210 static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
 211                                             unsigned short reg)
 212 {
 213         struct snd_cs46xx *chip = ac97->private_data;
 214         unsigned short val;
 215         int codec_index = ac97->num;
 216
 217         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 218                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 219                 return 0xffff;
 220
 221         val = snd_cs46xx_codec_read(chip, reg, codec_index);
 222
 223         return val;
 224 }
 225
 226
 227 static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
 228                                    unsigned short reg,
 229                                    unsigned short val,
 230                                    int codec_index)
 231 {
 232         int count;
 233
 234         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 235                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 236                 return;
 237
 238         chip->active_ctrl(chip, 1);
 239
 240         /*
 241          *  1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 242          *  2. Write ACCDA = Command Data Register = 470h    for data to write to AC97
 243          *  3. Write ACCTL = Control Register = 460h for initiating the write
 244          *  4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 245          *  5. if DCV not cleared, break and return error
 246          */
 247
 248         /*
 249          *  Setup the AC97 control registers on the CS461x to send the
 250          *  appropriate command to the AC97 to perform the read.
 251          *  ACCAD = Command Address Register = 46Ch
 252          *  ACCDA = Command Data Register = 470h
 253          *  ACCTL = Control Register = 460h
 254          *  set DCV - will clear when process completed
 255          *  reset CRW - Write command
 256          *  set VFRM - valid frame enabled
 257          *  set ESYN - ASYNC generation enabled
 258          *  set RSTN - ARST# inactive, AC97 codec not reset
 259          */
 260         snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
 261         snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
 262         snd_cs46xx_peekBA0(chip, BA0_ACCTL);
 263
 264         if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
 265                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
 266                                    ACCTL_ESYN | ACCTL_RSTN);
 267                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
 268                                    ACCTL_ESYN | ACCTL_RSTN);
 269         } else {
 270                 snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
 271                                    ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
 272         }
 273
 274         for (count = 0; count < 4000; count++) {
 275                 /*
 276                  *  First, we want to wait for a short time.
 277                  */
 278                 udelay(10);
 279                 /*
 280                  *  Now, check to see if the write has completed.
 281                  *  ACCTL = 460h, DCV should be reset by now and 460h = 07h
 282                  */
 283                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
 284                         goto end;
 285                 }
 286         }
 287         snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
 288  end:
 289         chip->active_ctrl(chip, -1);
 290 }
 291
 292 static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
 293                                    unsigned short reg,
 294                                    unsigned short val)
 295 {
 296         struct snd_cs46xx *chip = ac97->private_data;
 297         int codec_index = ac97->num;
 298
 299         if (snd_BUG_ON(codec_index != CS46XX_PRIMARY_CODEC_INDEX &&
 300                        codec_index != CS46XX_SECONDARY_CODEC_INDEX))
 301                 return;
 302
 303         snd_cs46xx_codec_write(chip, reg, val, codec_index);
 304 }
 305
 306
 307 /*
 308  *  Chip initialization
 309  */
 310
 311 int snd_cs46xx_download(struct snd_cs46xx *chip,
 312                         u32 *src,
 313                         unsigned long offset,
 314                         unsigned long len)
 315 {
 316         void __iomem *dst;
 317         unsigned int bank = offset >> 16;
 318         offset = offset & 0xffff;
 319
 320         if (snd_BUG_ON((offset & 3) || (len & 3)))
 321                 return -EINVAL;
 322         dst = chip->region.idx[bank+1].remap_addr + offset;
 323         len /= sizeof(u32);
 324
 325         /* writel already converts 32-bit value to right endianess */
 326         while (len-- > 0) {
 327                 writel(*src++, dst);
 328                 dst += sizeof(u32);
 329         }
 330         return 0;
 331 }
 332
 333 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 334
 335 #include "imgs/cwc4630.h"
 336 #include "imgs/cwcasync.h"
 337 #include "imgs/cwcsnoop.h"
 338 #include "imgs/cwcbinhack.h"
 339 #include "imgs/cwcdma.h"
 340
 341 int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
 342                          unsigned long offset,
 343                          unsigned long len)
 344 {
 345         void __iomem *dst;
 346         unsigned int bank = offset >> 16;
 347         offset = offset & 0xffff;
 348
 349         if (snd_BUG_ON((offset & 3) || (len & 3)))
 350                 return -EINVAL;
 351         dst = chip->region.idx[bank+1].remap_addr + offset;
 352         len /= sizeof(u32);
 353
 354         /* writel already converts 32-bit value to right endianess */
 355         while (len-- > 0) {
 356                 writel(0, dst);
 357                 dst += sizeof(u32);
 358         }
 359         return 0;
 360 }
 361
 362 #else /* old DSP image */
 363
 364 #include "cs46xx_image.h"
 365
 366 int snd_cs46xx_download_image(struct snd_cs46xx *chip)
 367 {
 368         int idx, err;
 369         unsigned long offset = 0;
 370
 371         for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
 372                 if ((err = snd_cs46xx_download(chip,
 373                                                &BA1Struct.map[offset],
 374                                                BA1Struct.memory[idx].offset,
 375                                                BA1Struct.memory[idx].size)) < 0)
 376                         return err;
 377                 offset += BA1Struct.memory[idx].size >> 2;
 378         }
 379         return 0;
 380 }
 381 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
 382
 383 /*
 384  *  Chip reset
 385  */
 386
 387 static void snd_cs46xx_reset(struct snd_cs46xx *chip)
 388 {
 389         int idx;
 390
 391         /*
 392          *  Write the reset bit of the SP control register.
 393          */
 394         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
 395
 396         /*
 397          *  Write the control register.
 398          */
 399         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
 400
 401         /*
 402          *  Clear the trap registers.
 403          */
 404         for (idx = 0; idx < 8; idx++) {
 405                 snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
 406                 snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
 407         }
 408         snd_cs46xx_poke(chip, BA1_DREG, 0);
 409
 410         /*
 411          *  Set the frame timer to reflect the number of cycles per frame.
 412          */
 413         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 414 }
 415
 416 static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
 417 {
 418         u32 i, status = 0;
 419         /*
 420          * Make sure the previous FIFO write operation has completed.
 421          */
 422         for(i = 0; i < 50; i++){
 423                 status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
 424
 425                 if( !(status & SERBST_WBSY) )
 426                         break;
 427
 428                 mdelay(retry_timeout);
 429         }
 430
 431         if(status & SERBST_WBSY) {
 432                 snd_printk(KERN_ERR "cs46xx: failure waiting for "
 433                            "FIFO command to complete\n");
 434                 return -EINVAL;
 435         }
 436
 437         return 0;
 438 }
 439
 440 static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
 441 {
 442         int idx, powerdown = 0;
 443         unsigned int tmp;
 444
 445         /*
 446          *  See if the devices are powered down.  If so, we must power them up first
 447          *  or they will not respond.
 448          */
 449         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
 450         if (!(tmp & CLKCR1_SWCE)) {
 451                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
 452                 powerdown = 1;
 453         }
 454
 455         /*
 456          *  We want to clear out the serial port FIFOs so we don't end up playing
 457          *  whatever random garbage happens to be in them.  We fill the sample FIFOS
 458          *  with zero (silence).
 459          */
 460         snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
 461
 462         /*
 463          *  Fill all 256 sample FIFO locations.
 464          */
 465         for (idx = 0; idx < 0xFF; idx++) {
 466                 /*
 467                  *  Make sure the previous FIFO write operation has completed.
 468                  */
 469                 if (cs46xx_wait_for_fifo(chip,1)) {
 470                         snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
 471
 472                         if (powerdown)
 473                                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 474
 475                         break;
 476                 }
 477                 /*
 478                  *  Write the serial port FIFO index.
 479                  */
 480                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
 481                 /*
 482                  *  Tell the serial port to load the new value into the FIFO location.
 483                  */
 484                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
 485         }
 486         /*
 487          *  Now, if we powered up the devices, then power them back down again.
 488          *  This is kinda ugly, but should never happen.
 489          */
 490         if (powerdown)
 491                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
 492 }
 493
 494 static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
 495 {
 496         int cnt;
 497
 498         /*
 499          *  Set the frame timer to reflect the number of cycles per frame.
 500          */
 501         snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
 502         /*
 503          *  Turn on the run, run at frame, and DMA enable bits in the local copy of
 504          *  the SP control register.
 505          */
 506         snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
 507         /*
 508          *  Wait until the run at frame bit resets itself in the SP control
 509          *  register.
 510          */
 511         for (cnt = 0; cnt < 25; cnt++) {
 512                 udelay(50);
 513                 if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
 514                         break;
 515         }
 516
 517         if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
 518                 snd_printk(KERN_ERR "SPCR_RUNFR never reset\n");
 519 }
 520
 521 static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
 522 {
 523         /*
 524          *  Turn off the run, run at frame, and DMA enable bits in the local copy of
 525          *  the SP control register.
 526          */
 527         snd_cs46xx_poke(chip, BA1_SPCR, 0);
 528 }
 529
 530 /*
 531  *  Sample rate routines
 532  */
 533
 534 #define GOF_PER_SEC 200
 535
 536 static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 537 {
 538         unsigned long flags;
 539         unsigned int tmp1, tmp2;
 540         unsigned int phiIncr;
 541         unsigned int correctionPerGOF, correctionPerSec;
 542
 543         /*
 544          *  Compute the values used to drive the actual sample rate conversion.
 545          *  The following formulas are being computed, using inline assembly
 546          *  since we need to use 64 bit arithmetic to compute the values:
 547          *
 548          *  phiIncr = floor((Fs,in * 2^26) / Fs,out)
 549          *  correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 550          *                                   GOF_PER_SEC)
 551          *  ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
 552          *                       GOF_PER_SEC * correctionPerGOF
 553          *
 554          *  i.e.
 555          *
 556          *  phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
 557          *  correctionPerGOF:correctionPerSec =
 558          *      dividend:remainder(ulOther / GOF_PER_SEC)
 559          */
 560         tmp1 = rate << 16;
 561         phiIncr = tmp1 / 48000;
 562         tmp1 -= phiIncr * 48000;
 563         tmp1 <<= 10;
 564         phiIncr <<= 10;
 565         tmp2 = tmp1 / 48000;
 566         phiIncr += tmp2;
 567         tmp1 -= tmp2 * 48000;
 568         correctionPerGOF = tmp1 / GOF_PER_SEC;
 569         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 570         correctionPerSec = tmp1;
 571
 572         /*
 573          *  Fill in the SampleRateConverter control block.
 574          */
 575         spin_lock_irqsave(&chip->reg_lock, flags);
 576         snd_cs46xx_poke(chip, BA1_PSRC,
 577           ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 578         snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
 579         spin_unlock_irqrestore(&chip->reg_lock, flags);
 580 }
 581
 582 static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
 583 {
 584         unsigned long flags;
 585         unsigned int phiIncr, coeffIncr, tmp1, tmp2;
 586         unsigned int correctionPerGOF, correctionPerSec, initialDelay;
 587         unsigned int frameGroupLength, cnt;
 588
 589         /*
 590          *  We can only decimate by up to a factor of 1/9th the hardware rate.
 591          *  Correct the value if an attempt is made to stray outside that limit.
 592          */
 593         if ((rate * 9) < 48000)
 594                 rate = 48000 / 9;
 595
 596         /*
 597          *  We can not capture at at rate greater than the Input Rate (48000).
 598          *  Return an error if an attempt is made to stray outside that limit.
 599          */
 600         if (rate > 48000)
 601                 rate = 48000;
 602
 603         /*
 604          *  Compute the values used to drive the actual sample rate conversion.
 605          *  The following formulas are being computed, using inline assembly
 606          *  since we need to use 64 bit arithmetic to compute the values:
 607          *
 608          *     coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
 609          *     phiIncr = floor((Fs,in * 2^26) / Fs,out)
 610          *     correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
 611          *                                GOF_PER_SEC)
 612          *     correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
 613          *                          GOF_PER_SEC * correctionPerGOF
 614          *     initialDelay = ceil((24 * Fs,in) / Fs,out)
 615          *
 616          * i.e.
 617          *
 618          *     coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
 619          *     phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
 620          *     correctionPerGOF:correctionPerSec =
 621          *          dividend:remainder(ulOther / GOF_PER_SEC)
 622          *     initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
 623          */
 624
 625         tmp1 = rate << 16;
 626         coeffIncr = tmp1 / 48000;
 627         tmp1 -= coeffIncr * 48000;
 628         tmp1 <<= 7;
 629         coeffIncr <<= 7;
 630         coeffIncr += tmp1 / 48000;
 631         coeffIncr ^= 0xFFFFFFFF;
 632         coeffIncr++;
 633         tmp1 = 48000 << 16;
 634         phiIncr = tmp1 / rate;
 635         tmp1 -= phiIncr * rate;
 636         tmp1 <<= 10;
 637         phiIncr <<= 10;
 638         tmp2 = tmp1 / rate;
 639         phiIncr += tmp2;
 640         tmp1 -= tmp2 * rate;
 641         correctionPerGOF = tmp1 / GOF_PER_SEC;
 642         tmp1 -= correctionPerGOF * GOF_PER_SEC;
 643         correctionPerSec = tmp1;
 644         initialDelay = ((48000 * 24) + rate - 1) / rate;
 645
 646         /*
 647          *  Fill in the VariDecimate control block.
 648          */
 649         spin_lock_irqsave(&chip->reg_lock, flags);
 650         snd_cs46xx_poke(chip, BA1_CSRC,
 651                 ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
 652         snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
 653         snd_cs46xx_poke(chip, BA1_CD,
 654                 (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
 655         snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
 656         spin_unlock_irqrestore(&chip->reg_lock, flags);
 657
 658         /*
 659          *  Figure out the frame group length for the write back task.  Basically,
 660          *  this is just the factors of 24000 (2^6*3*5^3) that are not present in
 661          *  the output sample rate.
 662          */
 663         frameGroupLength = 1;
 664         for (cnt = 2; cnt <= 64; cnt *= 2) {
 665                 if (((rate / cnt) * cnt) != rate)
 666                         frameGroupLength *= 2;
 667         }
 668         if (((rate / 3) * 3) != rate) {
 669                 frameGroupLength *= 3;
 670         }
 671         for (cnt = 5; cnt <= 125; cnt *= 5) {
 672                 if (((rate / cnt) * cnt) != rate)
 673                         frameGroupLength *= 5;
 674         }
 675
 676         /*
 677          * Fill in the WriteBack control block.
 678          */
 679         spin_lock_irqsave(&chip->reg_lock, flags);
 680         snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
 681         snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
 682         snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
 683         snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
 684         snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
 685         spin_unlock_irqrestore(&chip->reg_lock, flags);
 686 }
 687
 688 /*
 689  *  PCM part
 690  */
 691
 692 static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
 693                                      struct snd_pcm_indirect *rec, size_t bytes)
 694 {
 695         struct snd_pcm_runtime *runtime = substream->runtime;
 696         struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 697         memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
 698 }
 699
 700 static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
 701 {
 702         struct snd_pcm_runtime *runtime = substream->runtime;
 703         struct snd_cs46xx_pcm * cpcm = runtime->private_data;
 704         snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
 705         return 0;
 706 }
 707
 708 static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
 709                                      struct snd_pcm_indirect *rec, size_t bytes)
 710 {
 711         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 712         struct snd_pcm_runtime *runtime = substream->runtime;
 713         memcpy(runtime->dma_area + rec->sw_data,
 714                chip->capt.hw_buf.area + rec->hw_data, bytes);
 715 }
 716
 717 static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
 718 {
 719         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 720         snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
 721         return 0;
 722 }
 723
 724 static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
 725 {
 726         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 727         size_t ptr;
 728         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 729
 730         if (snd_BUG_ON(!cpcm->pcm_channel))
 731                 return -ENXIO;
 732
 733 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 734         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 735 #else
 736         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 737 #endif
 738         ptr -= cpcm->hw_buf.addr;
 739         return ptr >> cpcm->shift;
 740 }
 741
 742 static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
 743 {
 744         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 745         size_t ptr;
 746         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 747
 748 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 749         if (snd_BUG_ON(!cpcm->pcm_channel))
 750                 return -ENXIO;
 751         ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
 752 #else
 753         ptr = snd_cs46xx_peek(chip, BA1_PBA);
 754 #endif
 755         ptr -= cpcm->hw_buf.addr;
 756         return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
 757 }
 758
 759 static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
 760 {
 761         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 762         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 763         return ptr >> chip->capt.shift;
 764 }
 765
 766 static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
 767 {
 768         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 769         size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
 770         return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
 771 }
 772
 773 static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
 774                                        int cmd)
 775 {
 776         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 777         /*struct snd_pcm_runtime *runtime = substream->runtime;*/
 778         int result = 0;
 779
 780 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 781         struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
 782         if (! cpcm->pcm_channel) {
 783                 return -ENXIO;
 784         }
 785 #endif
 786         switch (cmd) {
 787         case SNDRV_PCM_TRIGGER_START:
 788         case SNDRV_PCM_TRIGGER_RESUME:
 789 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 790                 /* magic value to unmute PCM stream  playback volume */
 791                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 792                                        SCBVolumeCtrl) << 2, 0x80008000);
 793
 794                 if (cpcm->pcm_channel->unlinked)
 795                         cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
 796
 797                 if (substream->runtime->periods != CS46XX_FRAGS)
 798                         snd_cs46xx_playback_transfer(substream);
 799 #else
 800                 spin_lock(&chip->reg_lock);
 801                 if (substream->runtime->periods != CS46XX_FRAGS)
 802                         snd_cs46xx_playback_transfer(substream);
 803                 { unsigned int tmp;
 804                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 805                 tmp &= 0x0000ffff;
 806                 snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
 807                 }
 808                 spin_unlock(&chip->reg_lock);
 809 #endif
 810                 break;
 811         case SNDRV_PCM_TRIGGER_STOP:
 812         case SNDRV_PCM_TRIGGER_SUSPEND:
 813 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 814                 /* magic mute channel */
 815                 snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
 816                                        SCBVolumeCtrl) << 2, 0xffffffff);
 817
 818                 if (!cpcm->pcm_channel->unlinked)
 819                         cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
 820 #else
 821                 spin_lock(&chip->reg_lock);
 822                 { unsigned int tmp;
 823                 tmp = snd_cs46xx_peek(chip, BA1_PCTL);
 824                 tmp &= 0x0000ffff;
 825                 snd_cs46xx_poke(chip, BA1_PCTL, tmp);
 826                 }
 827                 spin_unlock(&chip->reg_lock);
 828 #endif
 829                 break;
 830         default:
 831                 result = -EINVAL;
 832                 break;
 833         }
 834
 835         return result;
 836 }
 837
 838 static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
 839                                       int cmd)
 840 {
 841         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 842         unsigned int tmp;
 843         int result = 0;
 844
 845         spin_lock(&chip->reg_lock);
 846         switch (cmd) {
 847         case SNDRV_PCM_TRIGGER_START:
 848         case SNDRV_PCM_TRIGGER_RESUME:
 849                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 850                 tmp &= 0xffff0000;
 851                 snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
 852                 break;
 853         case SNDRV_PCM_TRIGGER_STOP:
 854         case SNDRV_PCM_TRIGGER_SUSPEND:
 855                 tmp = snd_cs46xx_peek(chip, BA1_CCTL);
 856                 tmp &= 0xffff0000;
 857                 snd_cs46xx_poke(chip, BA1_CCTL, tmp);
 858                 break;
 859         default:
 860                 result = -EINVAL;
 861                 break;
 862         }
 863         spin_unlock(&chip->reg_lock);
 864
 865         return result;
 866 }
 867
 868 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 869 static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
 870                                        int sample_rate)
 871 {
 872
 873         /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
 874         if ( cpcm->pcm_channel == NULL) {
 875                 cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
 876                                                                    cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
 877                 if (cpcm->pcm_channel == NULL) {
 878                         snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
 879                         return -ENOMEM;
 880                 }
 881                 cpcm->pcm_channel->sample_rate = sample_rate;
 882         } else
 883         /* if sample rate is changed */
 884         if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
 885                 int unlinked = cpcm->pcm_channel->unlinked;
 886                 cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
 887
 888                 if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
 889                                                                          cpcm->hw_buf.addr,
 890                                                                          cpcm->pcm_channel_id)) == NULL) {
 891                         snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
 892                         return -ENOMEM;
 893                 }
 894
 895                 if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
 896                 cpcm->pcm_channel->sample_rate = sample_rate;
 897         }
 898
 899         return 0;
 900 }
 901 #endif
 902
 903
 904 static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
 905                                          struct snd_pcm_hw_params *hw_params)
 906 {
 907         struct snd_pcm_runtime *runtime = substream->runtime;
 908         struct snd_cs46xx_pcm *cpcm;
 909         int err;
 910 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 911         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
 912         int sample_rate = params_rate(hw_params);
 913         int period_size = params_period_bytes(hw_params);
 914 #endif
 915         cpcm = runtime->private_data;
 916
 917 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 918         if (snd_BUG_ON(!sample_rate))
 919                 return -ENXIO;
 920
 921         mutex_lock(&chip->spos_mutex);
 922
 923         if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
 924                 mutex_unlock(&chip->spos_mutex);
 925                 return -ENXIO;
 926         }
 927
 928         snd_BUG_ON(!cpcm->pcm_channel);
 929         if (!cpcm->pcm_channel) {
 930                 mutex_unlock(&chip->spos_mutex);
 931                 return -ENXIO;
 932         }
 933
 934
 935         if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
 936                  mutex_unlock(&chip->spos_mutex);
 937                  return -EINVAL;
 938          }
 939
 940         snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
 941                      period_size, params_periods(hw_params),
 942                      params_buffer_bytes(hw_params));
 943 #endif
 944
 945         if (params_periods(hw_params) == CS46XX_FRAGS) {
 946                 if (runtime->dma_area != cpcm->hw_buf.area)
 947                         snd_pcm_lib_free_pages(substream);
 948                 runtime->dma_area = cpcm->hw_buf.area;
 949                 runtime->dma_addr = cpcm->hw_buf.addr;
 950                 runtime->dma_bytes = cpcm->hw_buf.bytes;
 951
 952
 953 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 954                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
 955                         substream->ops = &snd_cs46xx_playback_ops;
 956                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
 957                         substream->ops = &snd_cs46xx_playback_rear_ops;
 958                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
 959                         substream->ops = &snd_cs46xx_playback_clfe_ops;
 960                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
 961                         substream->ops = &snd_cs46xx_playback_iec958_ops;
 962                 } else {
 963                         snd_BUG();
 964                 }
 965 #else
 966                 substream->ops = &snd_cs46xx_playback_ops;
 967 #endif
 968
 969         } else {
 970                 if (runtime->dma_area == cpcm->hw_buf.area) {
 971                         runtime->dma_area = NULL;
 972                         runtime->dma_addr = 0;
 973                         runtime->dma_bytes = 0;
 974                 }
 975                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
 976 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 977                         mutex_unlock(&chip->spos_mutex);
 978 #endif
 979                         return err;
 980                 }
 981
 982 #ifdef CONFIG_SND_CS46XX_NEW_DSP
 983                 if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
 984                         substream->ops = &snd_cs46xx_playback_indirect_ops;
 985                 } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
 986                         substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
 987                 } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
 988                         substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
 989                 } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
 990                         substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
 991                 } else {
 992                         snd_BUG();
 993                 }
 994 #else
 995                 substream->ops = &snd_cs46xx_playback_indirect_ops;
 996 #endif
 997
 998         }
 999
1000 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1001         mutex_unlock(&chip->spos_mutex);
1002 #endif
1003
1004         return 0;
1005 }
1006
1007 static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
1008 {
1009         /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
1010         struct snd_pcm_runtime *runtime = substream->runtime;
1011         struct snd_cs46xx_pcm *cpcm;
1012
1013         cpcm = runtime->private_data;
1014
1015         /* if play_back open fails, then this function
1016            is called and cpcm can actually be NULL here */
1017         if (!cpcm) return -ENXIO;
1018
1019         if (runtime->dma_area != cpcm->hw_buf.area)
1020                 snd_pcm_lib_free_pages(substream);
1021
1022         runtime->dma_area = NULL;
1023         runtime->dma_addr = 0;
1024         runtime->dma_bytes = 0;
1025
1026         return 0;
1027 }
1028
1029 static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
1030 {
1031         unsigned int tmp;
1032         unsigned int pfie;
1033         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1034         struct snd_pcm_runtime *runtime = substream->runtime;
1035         struct snd_cs46xx_pcm *cpcm;
1036
1037         cpcm = runtime->private_data;
1038
1039 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1040         if (snd_BUG_ON(!cpcm->pcm_channel))
1041                 return -ENXIO;
1042
1043         pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
1044         pfie &= ~0x0000f03f;
1045 #else
1046         /* old dsp */
1047         pfie = snd_cs46xx_peek(chip, BA1_PFIE);
1048         pfie &= ~0x0000f03f;
1049 #endif
1050
1051         cpcm->shift = 2;
1052         /* if to convert from stereo to mono */
1053         if (runtime->channels == 1) {
1054                 cpcm->shift--;
1055                 pfie |= 0x00002000;
1056         }
1057         /* if to convert from 8 bit to 16 bit */
1058         if (snd_pcm_format_width(runtime->format) == 8) {
1059                 cpcm->shift--;
1060                 pfie |= 0x00001000;
1061         }
1062         /* if to convert to unsigned */
1063         if (snd_pcm_format_unsigned(runtime->format))
1064                 pfie |= 0x00008000;
1065
1066         /* Never convert byte order when sample stream is 8 bit */
1067         if (snd_pcm_format_width(runtime->format) != 8) {
1068                 /* convert from big endian to little endian */
1069                 if (snd_pcm_format_big_endian(runtime->format))
1070                         pfie |= 0x00004000;
1071         }
1072
1073         memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
1074         cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1075         cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
1076
1077 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1078
1079         tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
1080         tmp &= ~0x000003ff;
1081         tmp |= (4 << cpcm->shift) - 1;
1082         /* playback transaction count register */
1083         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
1084
1085         /* playback format && interrupt enable */
1086         snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
1087 #else
1088         snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
1089         tmp = snd_cs46xx_peek(chip, BA1_PDTC);
1090         tmp &= ~0x000003ff;
1091         tmp |= (4 << cpcm->shift) - 1;
1092         snd_cs46xx_poke(chip, BA1_PDTC, tmp);
1093         snd_cs46xx_poke(chip, BA1_PFIE, pfie);
1094         snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
1095 #endif
1096
1097         return 0;
1098 }
1099
1100 static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
1101                                         struct snd_pcm_hw_params *hw_params)
1102 {
1103         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1104         struct snd_pcm_runtime *runtime = substream->runtime;
1105         int err;
1106
1107 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1108         cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
1109 #endif
1110         if (runtime->periods == CS46XX_FRAGS) {
1111                 if (runtime->dma_area != chip->capt.hw_buf.area)
1112                         snd_pcm_lib_free_pages(substream);
1113                 runtime->dma_area = chip->capt.hw_buf.area;
1114                 runtime->dma_addr = chip->capt.hw_buf.addr;
1115                 runtime->dma_bytes = chip->capt.hw_buf.bytes;
1116                 substream->ops = &snd_cs46xx_capture_ops;
1117         } else {
1118                 if (runtime->dma_area == chip->capt.hw_buf.area) {
1119                         runtime->dma_area = NULL;
1120                         runtime->dma_addr = 0;
1121                         runtime->dma_bytes = 0;
1122                 }
1123                 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1124                         return err;
1125                 substream->ops = &snd_cs46xx_capture_indirect_ops;
1126         }
1127
1128         return 0;
1129 }
1130
1131 static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
1132 {
1133         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1134         struct snd_pcm_runtime *runtime = substream->runtime;
1135
1136         if (runtime->dma_area != chip->capt.hw_buf.area)
1137                 snd_pcm_lib_free_pages(substream);
1138         runtime->dma_area = NULL;
1139         runtime->dma_addr = 0;
1140         runtime->dma_bytes = 0;
1141
1142         return 0;
1143 }
1144
1145 static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
1146 {
1147         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1148         struct snd_pcm_runtime *runtime = substream->runtime;
1149
1150         snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
1151         chip->capt.shift = 2;
1152         memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
1153         chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
1154         chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
1155         snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
1156
1157         return 0;
1158 }
1159
1160 static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
1161 {
1162         struct snd_cs46xx *chip = dev_id;
1163         u32 status1;
1164 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1165         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1166         u32 status2;
1167         int i;
1168         struct snd_cs46xx_pcm *cpcm = NULL;
1169 #endif
1170
1171         /*
1172          *  Read the Interrupt Status Register to clear the interrupt
1173          */
1174         status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
1175         if ((status1 & 0x7fffffff) == 0) {
1176                 snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1177                 return IRQ_NONE;
1178         }
1179
1180 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1181         status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
1182
1183         for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
1184                 if (i <= 15) {
1185                         if ( status1 & (1 << i) ) {
1186                                 if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
1187                                         if (chip->capt.substream)
1188                                                 snd_pcm_period_elapsed(chip->capt.substream);
1189                                 } else {
1190                                         if (ins->pcm_channels[i].active &&
1191                                             ins->pcm_channels[i].private_data &&
1192                                             !ins->pcm_channels[i].unlinked) {
1193                                                 cpcm = ins->pcm_channels[i].private_data;
1194                                                 snd_pcm_period_elapsed(cpcm->substream);
1195                                         }
1196                                 }
1197                         }
1198                 } else {
1199                         if ( status2 & (1 << (i - 16))) {
1200                                 if (ins->pcm_channels[i].active &&
1201                                     ins->pcm_channels[i].private_data &&
1202                                     !ins->pcm_channels[i].unlinked) {
1203                                         cpcm = ins->pcm_channels[i].private_data;
1204                                         snd_pcm_period_elapsed(cpcm->substream);
1205                                 }
1206                         }
1207                 }
1208         }
1209
1210 #else
1211         /* old dsp */
1212         if ((status1 & HISR_VC0) && chip->playback_pcm) {
1213                 if (chip->playback_pcm->substream)
1214                         snd_pcm_period_elapsed(chip->playback_pcm->substream);
1215         }
1216         if ((status1 & HISR_VC1) && chip->pcm) {
1217                 if (chip->capt.substream)
1218                         snd_pcm_period_elapsed(chip->capt.substream);
1219         }
1220 #endif
1221
1222         if ((status1 & HISR_MIDI) && chip->rmidi) {
1223                 unsigned char c;
1224
1225                 spin_lock(&chip->reg_lock);
1226                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
1227                         c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
1228                         if ((chip->midcr & MIDCR_RIE) == 0)
1229                                 continue;
1230                         snd_rawmidi_receive(chip->midi_input, &c, 1);
1231                 }
1232                 while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
1233                         if ((chip->midcr & MIDCR_TIE) == 0)
1234                                 break;
1235                         if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
1236                                 chip->midcr &= ~MIDCR_TIE;
1237                                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
1238                                 break;
1239                         }
1240                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
1241                 }
1242                 spin_unlock(&chip->reg_lock);
1243         }
1244         /*
1245          *  EOI to the PCI part....reenables interrupts
1246          */
1247         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
1248
1249         return IRQ_HANDLED;
1250 }
1251
1252 static struct snd_pcm_hardware snd_cs46xx_playback =
1253 {
1254         .info =                 (SNDRV_PCM_INFO_MMAP |
1255                                  SNDRV_PCM_INFO_INTERLEAVED |
1256                                  SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1257                                  /*SNDRV_PCM_INFO_RESUME*/),
1258         .formats =              (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
1259                                  SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
1260                                  SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
1261         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1262         .rate_min =             5500,
1263         .rate_max =             48000,
1264         .channels_min =         1,
1265         .channels_max =         2,
1266         .buffer_bytes_max =     (256 * 1024),
1267         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1268         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1269         .periods_min =          CS46XX_FRAGS,
1270         .periods_max =          1024,
1271         .fifo_size =            0,
1272 };
1273
1274 static struct snd_pcm_hardware snd_cs46xx_capture =
1275 {
1276         .info =                 (SNDRV_PCM_INFO_MMAP |
1277                                  SNDRV_PCM_INFO_INTERLEAVED |
1278                                  SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
1279                                  /*SNDRV_PCM_INFO_RESUME*/),
1280         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1281         .rates =                SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1282         .rate_min =             5500,
1283         .rate_max =             48000,
1284         .channels_min =         2,
1285         .channels_max =         2,
1286         .buffer_bytes_max =     (256 * 1024),
1287         .period_bytes_min =     CS46XX_MIN_PERIOD_SIZE,
1288         .period_bytes_max =     CS46XX_MAX_PERIOD_SIZE,
1289         .periods_min =          CS46XX_FRAGS,
1290         .periods_max =          1024,
1291         .fifo_size =            0,
1292 };
1293
1294 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1295
1296 static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
1297
1298 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
1299         .count = ARRAY_SIZE(period_sizes),
1300         .list = period_sizes,
1301         .mask = 0
1302 };
1303
1304 #endif
1305
1306 static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
1307 {
1308         kfree(runtime->private_data);
1309 }
1310
1311 static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
1312 {
1313         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1314         struct snd_cs46xx_pcm * cpcm;
1315         struct snd_pcm_runtime *runtime = substream->runtime;
1316
1317         cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
1318         if (cpcm == NULL)
1319                 return -ENOMEM;
1320         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1321                                 PAGE_SIZE, &cpcm->hw_buf) < 0) {
1322                 kfree(cpcm);
1323                 return -ENOMEM;
1324         }
1325
1326         runtime->hw = snd_cs46xx_playback;
1327         runtime->private_data = cpcm;
1328         runtime->private_free = snd_cs46xx_pcm_free_substream;
1329
1330         cpcm->substream = substream;
1331 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1332         mutex_lock(&chip->spos_mutex);
1333         cpcm->pcm_channel = NULL;
1334         cpcm->pcm_channel_id = pcm_channel_id;
1335
1336
1337         snd_pcm_hw_constraint_list(runtime, 0,
1338                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1339                                    &hw_constraints_period_sizes);
1340
1341         mutex_unlock(&chip->spos_mutex);
1342 #else
1343         chip->playback_pcm = cpcm; /* HACK */
1344 #endif
1345
1346         if (chip->accept_valid)
1347                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1348         chip->active_ctrl(chip, 1);
1349
1350         return 0;
1351 }
1352
1353 static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
1354 {
1355         snd_printdd("open front channel\n");
1356         return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
1357 }
1358
1359 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1360 static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
1361 {
1362         snd_printdd("open rear channel\n");
1363
1364         return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
1365 }
1366
1367 static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
1368 {
1369         snd_printdd("open center - LFE channel\n");
1370
1371         return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
1372 }
1373
1374 static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
1375 {
1376         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1377
1378         snd_printdd("open raw iec958 channel\n");
1379
1380         mutex_lock(&chip->spos_mutex);
1381         cs46xx_iec958_pre_open (chip);
1382         mutex_unlock(&chip->spos_mutex);
1383
1384         return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
1385 }
1386
1387 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
1388
1389 static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
1390 {
1391         int err;
1392         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1393
1394         snd_printdd("close raw iec958 channel\n");
1395
1396         err = snd_cs46xx_playback_close(substream);
1397
1398         mutex_lock(&chip->spos_mutex);
1399         cs46xx_iec958_post_close (chip);
1400         mutex_unlock(&chip->spos_mutex);
1401
1402         return err;
1403 }
1404 #endif
1405
1406 static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
1407 {
1408         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1409
1410         if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1411                                 PAGE_SIZE, &chip->capt.hw_buf) < 0)
1412                 return -ENOMEM;
1413         chip->capt.substream = substream;
1414         substream->runtime->hw = snd_cs46xx_capture;
1415
1416         if (chip->accept_valid)
1417                 substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
1418
1419         chip->active_ctrl(chip, 1);
1420
1421 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1422         snd_pcm_hw_constraint_list(substream->runtime, 0,
1423                                    SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1424                                    &hw_constraints_period_sizes);
1425 #endif
1426         return 0;
1427 }
1428
1429 static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
1430 {
1431         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1432         struct snd_pcm_runtime *runtime = substream->runtime;
1433         struct snd_cs46xx_pcm * cpcm;
1434
1435         cpcm = runtime->private_data;
1436
1437         /* when playback_open fails, then cpcm can be NULL */
1438         if (!cpcm) return -ENXIO;
1439
1440 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1441         mutex_lock(&chip->spos_mutex);
1442         if (cpcm->pcm_channel) {
1443                 cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
1444                 cpcm->pcm_channel = NULL;
1445         }
1446         mutex_unlock(&chip->spos_mutex);
1447 #else
1448         chip->playback_pcm = NULL;
1449 #endif
1450
1451         cpcm->substream = NULL;
1452         snd_dma_free_pages(&cpcm->hw_buf);
1453         chip->active_ctrl(chip, -1);
1454
1455         return 0;
1456 }
1457
1458 static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
1459 {
1460         struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
1461
1462         chip->capt.substream = NULL;
1463         snd_dma_free_pages(&chip->capt.hw_buf);
1464         chip->active_ctrl(chip, -1);
1465
1466         return 0;
1467 }
1468
1469 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1470 static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
1471         .open =                 snd_cs46xx_playback_open_rear,
1472         .close =                snd_cs46xx_playback_close,
1473         .ioctl =                snd_pcm_lib_ioctl,
1474         .hw_params =            snd_cs46xx_playback_hw_params,
1475         .hw_free =              snd_cs46xx_playback_hw_free,
1476         .prepare =              snd_cs46xx_playback_prepare,
1477         .trigger =              snd_cs46xx_playback_trigger,
1478         .pointer =              snd_cs46xx_playback_direct_pointer,
1479 };
1480
1481 static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
1482         .open =                 snd_cs46xx_playback_open_rear,
1483         .close =                snd_cs46xx_playback_close,
1484         .ioctl =                snd_pcm_lib_ioctl,
1485         .hw_params =            snd_cs46xx_playback_hw_params,
1486         .hw_free =              snd_cs46xx_playback_hw_free,
1487         .prepare =              snd_cs46xx_playback_prepare,
1488         .trigger =              snd_cs46xx_playback_trigger,
1489         .pointer =              snd_cs46xx_playback_indirect_pointer,
1490         .ack =                  snd_cs46xx_playback_transfer,
1491 };
1492
1493 static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
1494         .open =                 snd_cs46xx_playback_open_clfe,
1495         .close =                snd_cs46xx_playback_close,
1496         .ioctl =                snd_pcm_lib_ioctl,
1497         .hw_params =            snd_cs46xx_playback_hw_params,
1498         .hw_free =              snd_cs46xx_playback_hw_free,
1499         .prepare =              snd_cs46xx_playback_prepare,
1500         .trigger =              snd_cs46xx_playback_trigger,
1501         .pointer =              snd_cs46xx_playback_direct_pointer,
1502 };
1503
1504 static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
1505         .open =                 snd_cs46xx_playback_open_clfe,
1506         .close =                snd_cs46xx_playback_close,
1507         .ioctl =                snd_pcm_lib_ioctl,
1508         .hw_params =            snd_cs46xx_playback_hw_params,
1509         .hw_free =              snd_cs46xx_playback_hw_free,
1510         .prepare =              snd_cs46xx_playback_prepare,
1511         .trigger =              snd_cs46xx_playback_trigger,
1512         .pointer =              snd_cs46xx_playback_indirect_pointer,
1513         .ack =                  snd_cs46xx_playback_transfer,
1514 };
1515
1516 static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
1517         .open =                 snd_cs46xx_playback_open_iec958,
1518         .close =                snd_cs46xx_playback_close_iec958,
1519         .ioctl =                snd_pcm_lib_ioctl,
1520         .hw_params =            snd_cs46xx_playback_hw_params,
1521         .hw_free =              snd_cs46xx_playback_hw_free,
1522         .prepare =              snd_cs46xx_playback_prepare,
1523         .trigger =              snd_cs46xx_playback_trigger,
1524         .pointer =              snd_cs46xx_playback_direct_pointer,
1525 };
1526
1527 static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
1528         .open =                 snd_cs46xx_playback_open_iec958,
1529         .close =                snd_cs46xx_playback_close_iec958,
1530         .ioctl =                snd_pcm_lib_ioctl,
1531         .hw_params =            snd_cs46xx_playback_hw_params,
1532         .hw_free =              snd_cs46xx_playback_hw_free,
1533         .prepare =              snd_cs46xx_playback_prepare,
1534         .trigger =              snd_cs46xx_playback_trigger,
1535         .pointer =              snd_cs46xx_playback_indirect_pointer,
1536         .ack =                  snd_cs46xx_playback_transfer,
1537 };
1538
1539 #endif
1540
1541 static struct snd_pcm_ops snd_cs46xx_playback_ops = {
1542         .open =                 snd_cs46xx_playback_open,
1543         .close =                snd_cs46xx_playback_close,
1544         .ioctl =                snd_pcm_lib_ioctl,
1545         .hw_params =            snd_cs46xx_playback_hw_params,
1546         .hw_free =              snd_cs46xx_playback_hw_free,
1547         .prepare =              snd_cs46xx_playback_prepare,
1548         .trigger =              snd_cs46xx_playback_trigger,
1549         .pointer =              snd_cs46xx_playback_direct_pointer,
1550 };
1551
1552 static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
1553         .open =                 snd_cs46xx_playback_open,
1554         .close =                snd_cs46xx_playback_close,
1555         .ioctl =                snd_pcm_lib_ioctl,
1556         .hw_params =            snd_cs46xx_playback_hw_params,
1557         .hw_free =              snd_cs46xx_playback_hw_free,
1558         .prepare =              snd_cs46xx_playback_prepare,
1559         .trigger =              snd_cs46xx_playback_trigger,
1560         .pointer =              snd_cs46xx_playback_indirect_pointer,
1561         .ack =                  snd_cs46xx_playback_transfer,
1562 };
1563
1564 static struct snd_pcm_ops snd_cs46xx_capture_ops = {
1565         .open =                 snd_cs46xx_capture_open,
1566         .close =                snd_cs46xx_capture_close,
1567         .ioctl =                snd_pcm_lib_ioctl,
1568         .hw_params =            snd_cs46xx_capture_hw_params,
1569         .hw_free =              snd_cs46xx_capture_hw_free,
1570         .prepare =              snd_cs46xx_capture_prepare,
1571         .trigger =              snd_cs46xx_capture_trigger,
1572         .pointer =              snd_cs46xx_capture_direct_pointer,
1573 };
1574
1575 static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
1576         .open =                 snd_cs46xx_capture_open,
1577         .close =                snd_cs46xx_capture_close,
1578         .ioctl =                snd_pcm_lib_ioctl,
1579         .hw_params =            snd_cs46xx_capture_hw_params,
1580         .hw_free =              snd_cs46xx_capture_hw_free,
1581         .prepare =              snd_cs46xx_capture_prepare,
1582         .trigger =              snd_cs46xx_capture_trigger,
1583         .pointer =              snd_cs46xx_capture_indirect_pointer,
1584         .ack =                  snd_cs46xx_capture_transfer,
1585 };
1586
1587 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1588 #define MAX_PLAYBACK_CHANNELS   (DSP_MAX_PCM_CHANNELS - 1)
1589 #else
1590 #define MAX_PLAYBACK_CHANNELS   1
1591 #endif
1592
1593 int __devinit snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1594 {
1595         struct snd_pcm *pcm;
1596         int err;
1597
1598         if (rpcm)
1599                 *rpcm = NULL;
1600         if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
1601                 return err;
1602
1603         pcm->private_data = chip;
1604
1605         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
1606         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
1607
1608         /* global setup */
1609         pcm->info_flags = 0;
1610         strcpy(pcm->name, "CS46xx");
1611         chip->pcm = pcm;
1612
1613         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1614                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1615
1616         if (rpcm)
1617                 *rpcm = pcm;
1618
1619         return 0;
1620 }
1621
1622
1623 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1624 int __devinit snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1625 {
1626         struct snd_pcm *pcm;
1627         int err;
1628
1629         if (rpcm)
1630                 *rpcm = NULL;
1631
1632         if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1633                 return err;
1634
1635         pcm->private_data = chip;
1636
1637         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
1638
1639         /* global setup */
1640         pcm->info_flags = 0;
1641         strcpy(pcm->name, "CS46xx - Rear");
1642         chip->pcm_rear = pcm;
1643
1644         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1645                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1646
1647         if (rpcm)
1648                 *rpcm = pcm;
1649
1650         return 0;
1651 }
1652
1653 int __devinit snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1654 {
1655         struct snd_pcm *pcm;
1656         int err;
1657
1658         if (rpcm)
1659                 *rpcm = NULL;
1660
1661         if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
1662                 return err;
1663
1664         pcm->private_data = chip;
1665
1666         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
1667
1668         /* global setup */
1669         pcm->info_flags = 0;
1670         strcpy(pcm->name, "CS46xx - Center LFE");
1671         chip->pcm_center_lfe = pcm;
1672
1673         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1674                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1675
1676         if (rpcm)
1677                 *rpcm = pcm;
1678
1679         return 0;
1680 }
1681
1682 int __devinit snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
1683 {
1684         struct snd_pcm *pcm;
1685         int err;
1686
1687         if (rpcm)
1688                 *rpcm = NULL;
1689
1690         if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
1691                 return err;
1692
1693         pcm->private_data = chip;
1694
1695         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
1696
1697         /* global setup */
1698         pcm->info_flags = 0;
1699         strcpy(pcm->name, "CS46xx - IEC958");
1700         chip->pcm_rear = pcm;
1701
1702         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1703                                               snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
1704
1705         if (rpcm)
1706                 *rpcm = pcm;
1707
1708         return 0;
1709 }
1710 #endif
1711
1712 /*
1713  *  Mixer routines
1714  */
1715 static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
1716 {
1717         struct snd_cs46xx *chip = bus->private_data;
1718
1719         chip->ac97_bus = NULL;
1720 }
1721
1722 static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
1723 {
1724         struct snd_cs46xx *chip = ac97->private_data;
1725
1726         if (snd_BUG_ON(ac97 != chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] &&
1727                        ac97 != chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]))
1728                 return;
1729
1730         if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
1731                 chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
1732                 chip->eapd_switch = NULL;
1733         }
1734         else
1735                 chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
1736 }
1737
1738 static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
1739                                struct snd_ctl_elem_info *uinfo)
1740 {
1741         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1742         uinfo->count = 2;
1743         uinfo->value.integer.min = 0;
1744         uinfo->value.integer.max = 0x7fff;
1745         return 0;
1746 }
1747
1748 static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1749 {
1750         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1751         int reg = kcontrol->private_value;
1752         unsigned int val = snd_cs46xx_peek(chip, reg);
1753         ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
1754         ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
1755         return 0;
1756 }
1757
1758 static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1759 {
1760         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1761         int reg = kcontrol->private_value;
1762         unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
1763                             (0xffff - ucontrol->value.integer.value[1]));
1764         unsigned int old = snd_cs46xx_peek(chip, reg);
1765         int change = (old != val);
1766
1767         if (change) {
1768                 snd_cs46xx_poke(chip, reg, val);
1769         }
1770
1771         return change;
1772 }
1773
1774 #ifdef CONFIG_SND_CS46XX_NEW_DSP
1775
1776 static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1777 {
1778         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1779
1780         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
1781         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
1782
1783         return 0;
1784 }
1785
1786 static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1787 {
1788         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1789         int change = 0;
1790
1791         if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
1792             chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
1793                 cs46xx_dsp_set_dac_volume(chip,
1794                                           ucontrol->value.integer.value[0],
1795                                           ucontrol->value.integer.value[1]);
1796                 change = 1;
1797         }
1798
1799         return change;
1800 }
1801
1802 #if 0
1803 static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1804 {
1805         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1806
1807         ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
1808         ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
1809         return 0;
1810 }
1811
1812 static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1813 {
1814         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1815         int change = 0;
1816
1817         if (chip->dsp_spos_instance->spdif_input_volume_left  != ucontrol->value.integer.value[0] ||
1818             chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
1819                 cs46xx_dsp_set_iec958_volume (chip,
1820                                               ucontrol->value.integer.value[0],
1821                                               ucontrol->value.integer.value[1]);
1822                 change = 1;
1823         }
1824
1825         return change;
1826 }
1827 #endif
1828
1829 #define snd_mixer_boolean_info          snd_ctl_boolean_mono_info
1830
1831 static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
1832                                  struct snd_ctl_elem_value *ucontrol)
1833 {
1834         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1835         int reg = kcontrol->private_value;
1836
1837         if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
1838                 ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1839         else
1840                 ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
1841
1842         return 0;
1843 }
1844
1845 static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
1846                                   struct snd_ctl_elem_value *ucontrol)
1847 {
1848         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1849         int change, res;
1850
1851         switch (kcontrol->private_value) {
1852         case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
1853                 mutex_lock(&chip->spos_mutex);
1854                 change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
1855                 if (ucontrol->value.integer.value[0] && !change)
1856                         cs46xx_dsp_enable_spdif_out(chip);
1857                 else if (change && !ucontrol->value.integer.value[0])
1858                         cs46xx_dsp_disable_spdif_out(chip);
1859
1860                 res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
1861                 mutex_unlock(&chip->spos_mutex);
1862                 break;
1863         case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
1864                 change = chip->dsp_spos_instance->spdif_status_in;
1865                 if (ucontrol->value.integer.value[0] && !change) {
1866                         cs46xx_dsp_enable_spdif_in(chip);
1867                         /* restore volume */
1868                 }
1869                 else if (change && !ucontrol->value.integer.value[0])
1870                         cs46xx_dsp_disable_spdif_in(chip);
1871
1872                 res = (change != chip->dsp_spos_instance->spdif_status_in);
1873                 break;
1874         default:
1875                 res = -EINVAL;
1876                 snd_BUG(); /* should never happen ... */
1877         }
1878
1879         return res;
1880 }
1881
1882 static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
1883                                       struct snd_ctl_elem_value *ucontrol)
1884 {
1885         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1886         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1887
1888         if (ins->adc_input != NULL)
1889                 ucontrol->value.integer.value[0] = 1;
1890         else
1891                 ucontrol->value.integer.value[0] = 0;
1892
1893         return 0;
1894 }
1895
1896 static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
1897                                       struct snd_ctl_elem_value *ucontrol)
1898 {
1899         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1900         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1901         int change = 0;
1902
1903         if (ucontrol->value.integer.value[0] && !ins->adc_input) {
1904                 cs46xx_dsp_enable_adc_capture(chip);
1905                 change = 1;
1906         } else  if (!ucontrol->value.integer.value[0] && ins->adc_input) {
1907                 cs46xx_dsp_disable_adc_capture(chip);
1908                 change = 1;
1909         }
1910         return change;
1911 }
1912
1913 static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
1914                                       struct snd_ctl_elem_value *ucontrol)
1915 {
1916         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1917         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1918
1919         if (ins->pcm_input != NULL)
1920                 ucontrol->value.integer.value[0] = 1;
1921         else
1922                 ucontrol->value.integer.value[0] = 0;
1923
1924         return 0;
1925 }
1926
1927
1928 static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
1929                                       struct snd_ctl_elem_value *ucontrol)
1930 {
1931         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1932         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
1933         int change = 0;
1934
1935         if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
1936                 cs46xx_dsp_enable_pcm_capture(chip);
1937                 change = 1;
1938         } else  if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
1939                 cs46xx_dsp_disable_pcm_capture(chip);
1940                 change = 1;
1941         }
1942
1943         return change;
1944 }
1945
1946 static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
1947                                      struct snd_ctl_elem_value *ucontrol)
1948 {
1949         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1950
1951         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1952
1953         if (val1 & EGPIODR_GPOE0)
1954                 ucontrol->value.integer.value[0] = 1;
1955         else
1956                 ucontrol->value.integer.value[0] = 0;
1957
1958         return 0;
1959 }
1960
1961 /*
1962  *      Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
1963  */
1964 static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
1965                                        struct snd_ctl_elem_value *ucontrol)
1966 {
1967         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
1968         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
1969         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
1970
1971         if (ucontrol->value.integer.value[0]) {
1972                 /* optical is default */
1973                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
1974                                    EGPIODR_GPOE0 | val1);  /* enable EGPIO0 output */
1975                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
1976                                    EGPIOPTR_GPPT0 | val2); /* open-drain on output */
1977         } else {
1978                 /* coaxial */
1979                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE0); /* disable */
1980                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
1981         }
1982
1983         /* checking diff from the EGPIO direction register
1984            should be enough */
1985         return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
1986 }
1987
1988
1989 static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1990 {
1991         uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1992         uinfo->count = 1;
1993         return 0;
1994 }
1995
1996 static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
1997                                         struct snd_ctl_elem_value *ucontrol)
1998 {
1999         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2000         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2001
2002         mutex_lock(&chip->spos_mutex);
2003         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
2004         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
2005         ucontrol->value.iec958.status[2] = 0;
2006         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
2007         mutex_unlock(&chip->spos_mutex);
2008
2009         return 0;
2010 }
2011
2012 static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
2013                                         struct snd_ctl_elem_value *ucontrol)
2014 {
2015         struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2016         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2017         unsigned int val;
2018         int change;
2019
2020         mutex_lock(&chip->spos_mutex);
2021         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2022                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
2023                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3]))  |
2024                 /* left and right validity bit */
2025                 (1 << 13) | (1 << 12);
2026
2027
2028         change = (unsigned int)ins->spdif_csuv_default != val;
2029         ins->spdif_csuv_default = val;
2030
2031         if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
2032                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2033
2034         mutex_unlock(&chip->spos_mutex);
2035
2036         return change;
2037 }
2038
2039 static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
2040                                      struct snd_ctl_elem_value *ucontrol)
2041 {
2042         ucontrol->value.iec958.status[0] = 0xff;
2043         ucontrol->value.iec958.status[1] = 0xff;
2044         ucontrol->value.iec958.status[2] = 0x00;
2045         ucontrol->value.iec958.status[3] = 0xff;
2046         return 0;
2047 }
2048
2049 static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
2050                                          struct snd_ctl_elem_value *ucontrol)
2051 {
2052         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2053         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2054
2055         mutex_lock(&chip->spos_mutex);
2056         ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
2057         ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
2058         ucontrol->value.iec958.status[2] = 0;
2059         ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
2060         mutex_unlock(&chip->spos_mutex);
2061
2062         return 0;
2063 }
2064
2065 static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
2066                                         struct snd_ctl_elem_value *ucontrol)
2067 {
2068         struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
2069         struct dsp_spos_instance * ins = chip->dsp_spos_instance;
2070         unsigned int val;
2071         int change;
2072
2073         mutex_lock(&chip->spos_mutex);
2074         val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
2075                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
2076                 ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
2077                 /* left and right validity bit */
2078                 (1 << 13) | (1 << 12);
2079
2080
2081         change = ins->spdif_csuv_stream != val;
2082         ins->spdif_csuv_stream = val;
2083
2084         if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
2085                 cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
2086
2087         mutex_unlock(&chip->spos_mutex);
2088
2089         return change;
2090 }
2091
2092 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2093
2094
2095 static struct snd_kcontrol_new snd_cs46xx_controls[] __devinitdata = {
2096 {
2097         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2098         .name = "DAC Volume",
2099         .info = snd_cs46xx_vol_info,
2100 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2101         .get = snd_cs46xx_vol_get,
2102         .put = snd_cs46xx_vol_put,
2103         .private_value = BA1_PVOL,
2104 #else
2105         .get = snd_cs46xx_vol_dac_get,
2106         .put = snd_cs46xx_vol_dac_put,
2107 #endif
2108 },
2109
2110 {
2111         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2112         .name = "ADC Volume",
2113         .info = snd_cs46xx_vol_info,
2114         .get = snd_cs46xx_vol_get,
2115         .put = snd_cs46xx_vol_put,
2116 #ifndef CONFIG_SND_CS46XX_NEW_DSP
2117         .private_value = BA1_CVOL,
2118 #else
2119         .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
2120 #endif
2121 },
2122 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2123 {
2124         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2125         .name = "ADC Capture Switch",
2126         .info = snd_mixer_boolean_info,
2127         .get = snd_cs46xx_adc_capture_get,
2128         .put = snd_cs46xx_adc_capture_put
2129 },
2130 {
2131         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2132         .name = "DAC Capture Switch",
2133         .info = snd_mixer_boolean_info,
2134         .get = snd_cs46xx_pcm_capture_get,
2135         .put = snd_cs46xx_pcm_capture_put
2136 },
2137 {
2138         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2139         .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
2140         .info = snd_mixer_boolean_info,
2141         .get = snd_cs46xx_iec958_get,
2142         .put = snd_cs46xx_iec958_put,
2143         .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
2144 },
2145 {
2146         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2147         .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
2148         .info = snd_mixer_boolean_info,
2149         .get = snd_cs46xx_iec958_get,
2150         .put = snd_cs46xx_iec958_put,
2151         .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
2152 },
2153 #if 0
2154 /* Input IEC958 volume does not work for the moment. (Benny) */
2155 {
2156         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2157         .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
2158         .info = snd_cs46xx_vol_info,
2159         .get = snd_cs46xx_vol_iec958_get,
2160         .put = snd_cs46xx_vol_iec958_put,
2161         .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
2162 },
2163 #endif
2164 {
2165         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2166         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2167         .info =  snd_cs46xx_spdif_info,
2168         .get =   snd_cs46xx_spdif_default_get,
2169         .put =   snd_cs46xx_spdif_default_put,
2170 },
2171 {
2172         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2173         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
2174         .info =  snd_cs46xx_spdif_info,
2175         .get =   snd_cs46xx_spdif_mask_get,
2176         .access = SNDRV_CTL_ELEM_ACCESS_READ
2177 },
2178 {
2179         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2180         .name =  SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2181         .info =  snd_cs46xx_spdif_info,
2182         .get =   snd_cs46xx_spdif_stream_get,
2183         .put =   snd_cs46xx_spdif_stream_put
2184 },
2185
2186 #endif
2187 };
2188
2189 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2190 /* set primary cs4294 codec into Extended Audio Mode */
2191 static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
2192                                     struct snd_ctl_elem_value *ucontrol)
2193 {
2194         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2195         unsigned short val;
2196         val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
2197         ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
2198         return 0;
2199 }
2200
2201 static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
2202                                     struct snd_ctl_elem_value *ucontrol)
2203 {
2204         struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
2205         return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2206                                     AC97_CSR_ACMODE, 0x200,
2207                                     ucontrol->value.integer.value[0] ? 0 : 0x200);
2208 }
2209
2210 static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
2211         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2212         .name = "Duplicate Front",
2213         .info = snd_mixer_boolean_info,
2214         .get = snd_cs46xx_front_dup_get,
2215         .put = snd_cs46xx_front_dup_put,
2216 };
2217 #endif
2218
2219 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2220 /* Only available on the Hercules Game Theater XP soundcard */
2221 static struct snd_kcontrol_new snd_hercules_controls[] = {
2222 {
2223         .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2224         .name = "Optical/Coaxial SPDIF Input Switch",
2225         .info = snd_mixer_boolean_info,
2226         .get = snd_herc_spdif_select_get,
2227         .put = snd_herc_spdif_select_put,
2228 },
2229 };
2230
2231
2232 static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
2233 {
2234         unsigned long end_time;
2235         int err;
2236
2237         /* reset to defaults */
2238         snd_ac97_write(ac97, AC97_RESET, 0);
2239
2240         /* set the desired CODEC mode */
2241         if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
2242                 snd_printdd("cs46xx: CODEC1 mode %04x\n", 0x0);
2243                 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x0);
2244         } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
2245                 snd_printdd("cs46xx: CODEC2 mode %04x\n", 0x3);
2246                 snd_cs46xx_ac97_write(ac97, AC97_CSR_ACMODE, 0x3);
2247         } else {
2248                 snd_BUG(); /* should never happen ... */
2249         }
2250
2251         udelay(50);
2252
2253         /* it's necessary to wait awhile until registers are accessible after RESET */
2254         /* because the PCM or MASTER volume registers can be modified, */
2255         /* the REC_GAIN register is used for tests */
2256         end_time = jiffies + HZ;
2257         do {
2258                 unsigned short ext_mid;
2259
2260                 /* use preliminary reads to settle the communication */
2261                 snd_ac97_read(ac97, AC97_RESET);
2262                 snd_ac97_read(ac97, AC97_VENDOR_ID1);
2263                 snd_ac97_read(ac97, AC97_VENDOR_ID2);
2264                 /* modem? */
2265                 ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
2266                 if (ext_mid != 0xffff && (ext_mid & 1) != 0)
2267                         return;
2268
2269                 /* test if we can write to the record gain volume register */
2270                 snd_ac97_write(ac97, AC97_REC_GAIN, 0x8a05);
2271                 if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
2272                         return;
2273
2274                 msleep(10);
2275         } while (time_after_eq(end_time, jiffies));
2276
2277         snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n");
2278 }
2279 #endif
2280
2281 static int __devinit cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
2282 {
2283         int idx, err;
2284         struct snd_ac97_template ac97;
2285
2286         memset(&ac97, 0, sizeof(ac97));
2287         ac97.private_data = chip;
2288         ac97.private_free = snd_cs46xx_mixer_free_ac97;
2289         ac97.num = codec;
2290         if (chip->amplifier_ctrl == amp_voyetra)
2291                 ac97.scaps = AC97_SCAP_INV_EAPD;
2292
2293         if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
2294                 snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
2295                 udelay(10);
2296                 if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
2297                         snd_printdd("snd_cs46xx: seconadry codec not present\n");
2298                         return -ENXIO;
2299                 }
2300         }
2301
2302         snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
2303         for (idx = 0; idx < 100; ++idx) {
2304                 if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
2305                         err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
2306                         return err;
2307                 }
2308                 msleep(10);
2309         }
2310         snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
2311         return -ENXIO;
2312 }
2313
2314 int __devinit snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
2315 {
2316         struct snd_card *card = chip->card;
2317         struct snd_ctl_elem_id id;
2318         int err;
2319         unsigned int idx;
2320         static struct snd_ac97_bus_ops ops = {
2321 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2322                 .reset = snd_cs46xx_codec_reset,
2323 #endif
2324                 .write = snd_cs46xx_ac97_write,
2325                 .read = snd_cs46xx_ac97_read,
2326         };
2327
2328         /* detect primary codec */
2329         chip->nr_ac97_codecs = 0;
2330         snd_printdd("snd_cs46xx: detecting primary codec\n");
2331         if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
2332                 return err;
2333         chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
2334
2335         if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
2336                 return -ENXIO;
2337         chip->nr_ac97_codecs = 1;
2338
2339 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2340         snd_printdd("snd_cs46xx: detecting seconadry codec\n");
2341         /* try detect a secondary codec */
2342         if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
2343                 chip->nr_ac97_codecs = 2;
2344 #endif /* CONFIG_SND_CS46XX_NEW_DSP */
2345
2346         /* add cs4630 mixer controls */
2347         for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
2348                 struct snd_kcontrol *kctl;
2349                 kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
2350                 if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
2351                         kctl->id.device = spdif_device;
2352                 if ((err = snd_ctl_add(card, kctl)) < 0)
2353                         return err;
2354         }
2355
2356         /* get EAPD mixer switch (for voyetra hack) */
2357         memset(&id, 0, sizeof(id));
2358         id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2359         strcpy(id.name, "External Amplifier");
2360         chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
2361
2362 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2363         if (chip->nr_ac97_codecs == 1) {
2364                 unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
2365                 if (id2 == 0x592b || id2 == 0x592d) {
2366                         err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
2367                         if (err < 0)
2368                                 return err;
2369                         snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
2370                                              AC97_CSR_ACMODE, 0x200);
2371                 }
2372         }
2373         /* do soundcard specific mixer setup */
2374         if (chip->mixer_init) {
2375                 snd_printdd ("calling chip->mixer_init(chip);\n");
2376                 chip->mixer_init(chip);
2377         }
2378 #endif
2379
2380         /* turn on amplifier */
2381         chip->amplifier_ctrl(chip, 1);
2382
2383         return 0;
2384 }
2385
2386 /*
2387  *  RawMIDI interface
2388  */
2389
2390 static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
2391 {
2392         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
2393         udelay(100);
2394         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2395 }
2396
2397 static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
2398 {
2399         struct snd_cs46xx *chip = substream->rmidi->private_data;
2400
2401         chip->active_ctrl(chip, 1);
2402         spin_lock_irq(&chip->reg_lock);
2403         chip->uartm |= CS46XX_MODE_INPUT;
2404         chip->midcr |= MIDCR_RXE;
2405         chip->midi_input = substream;
2406         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2407                 snd_cs46xx_midi_reset(chip);
2408         } else {
2409                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2410         }
2411         spin_unlock_irq(&chip->reg_lock);
2412         return 0;
2413 }
2414
2415 static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
2416 {
2417         struct snd_cs46xx *chip = substream->rmidi->private_data;
2418
2419         spin_lock_irq(&chip->reg_lock);
2420         chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
2421         chip->midi_input = NULL;
2422         if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
2423                 snd_cs46xx_midi_reset(chip);
2424         } else {
2425                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2426         }
2427         chip->uartm &= ~CS46XX_MODE_INPUT;
2428         spin_unlock_irq(&chip->reg_lock);
2429         chip->active_ctrl(chip, -1);
2430         return 0;
2431 }
2432
2433 static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
2434 {
2435         struct snd_cs46xx *chip = substream->rmidi->private_data;
2436
2437         chip->active_ctrl(chip, 1);
2438
2439         spin_lock_irq(&chip->reg_lock);
2440         chip->uartm |= CS46XX_MODE_OUTPUT;
2441         chip->midcr |= MIDCR_TXE;
2442         chip->midi_output = substream;
2443         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2444                 snd_cs46xx_midi_reset(chip);
2445         } else {
2446                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2447         }
2448         spin_unlock_irq(&chip->reg_lock);
2449         return 0;
2450 }
2451
2452 static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
2453 {
2454         struct snd_cs46xx *chip = substream->rmidi->private_data;
2455
2456         spin_lock_irq(&chip->reg_lock);
2457         chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
2458         chip->midi_output = NULL;
2459         if (!(chip->uartm & CS46XX_MODE_INPUT)) {
2460                 snd_cs46xx_midi_reset(chip);
2461         } else {
2462                 snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2463         }
2464         chip->uartm &= ~CS46XX_MODE_OUTPUT;
2465         spin_unlock_irq(&chip->reg_lock);
2466         chip->active_ctrl(chip, -1);
2467         return 0;
2468 }
2469
2470 static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
2471 {
2472         unsigned long flags;
2473         struct snd_cs46xx *chip = substream->rmidi->private_data;
2474
2475         spin_lock_irqsave(&chip->reg_lock, flags);
2476         if (up) {
2477                 if ((chip->midcr & MIDCR_RIE) == 0) {
2478                         chip->midcr |= MIDCR_RIE;
2479                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2480                 }
2481         } else {
2482                 if (chip->midcr & MIDCR_RIE) {
2483                         chip->midcr &= ~MIDCR_RIE;
2484                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2485                 }
2486         }
2487         spin_unlock_irqrestore(&chip->reg_lock, flags);
2488 }
2489
2490 static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
2491 {
2492         unsigned long flags;
2493         struct snd_cs46xx *chip = substream->rmidi->private_data;
2494         unsigned char byte;
2495
2496         spin_lock_irqsave(&chip->reg_lock, flags);
2497         if (up) {
2498                 if ((chip->midcr & MIDCR_TIE) == 0) {
2499                         chip->midcr |= MIDCR_TIE;
2500                         /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
2501                         while ((chip->midcr & MIDCR_TIE) &&
2502                                (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
2503                                 if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
2504                                         chip->midcr &= ~MIDCR_TIE;
2505                                 } else {
2506                                         snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
2507                                 }
2508                         }
2509                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2510                 }
2511         } else {
2512                 if (chip->midcr & MIDCR_TIE) {
2513                         chip->midcr &= ~MIDCR_TIE;
2514                         snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
2515                 }
2516         }
2517         spin_unlock_irqrestore(&chip->reg_lock, flags);
2518 }
2519
2520 static struct snd_rawmidi_ops snd_cs46xx_midi_output =
2521 {
2522         .open =         snd_cs46xx_midi_output_open,
2523         .close =        snd_cs46xx_midi_output_close,
2524         .trigger =      snd_cs46xx_midi_output_trigger,
2525 };
2526
2527 static struct snd_rawmidi_ops snd_cs46xx_midi_input =
2528 {
2529         .open =         snd_cs46xx_midi_input_open,
2530         .close =        snd_cs46xx_midi_input_close,
2531         .trigger =      snd_cs46xx_midi_input_trigger,
2532 };
2533
2534 int __devinit snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi)
2535 {
2536         struct snd_rawmidi *rmidi;
2537         int err;
2538
2539         if (rrawmidi)
2540                 *rrawmidi = NULL;
2541         if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
2542                 return err;
2543         strcpy(rmidi->name, "CS46XX");
2544         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
2545         snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
2546         rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
2547         rmidi->private_data = chip;
2548         chip->rmidi = rmidi;
2549         if (rrawmidi)
2550                 *rrawmidi = NULL;
2551         return 0;
2552 }
2553
2554
2555 /*
2556  * gameport interface
2557  */
2558
2559 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
2560
2561 static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
2562 {
2563         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2564
2565         if (snd_BUG_ON(!chip))
2566                 return;
2567         snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF);  //outb(gameport->io, 0xFF);
2568 }
2569
2570 static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
2571 {
2572         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2573
2574         if (snd_BUG_ON(!chip))
2575                 return 0;
2576         return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
2577 }
2578
2579 static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
2580 {
2581         struct snd_cs46xx *chip = gameport_get_port_data(gameport);
2582         unsigned js1, js2, jst;
2583
2584         if (snd_BUG_ON(!chip))
2585                 return 0;
2586
2587         js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
2588         js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
2589         jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
2590
2591         *buttons = (~jst >> 4) & 0x0F;
2592
2593         axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
2594         axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
2595         axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
2596         axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
2597
2598         for(jst=0;jst<4;++jst)
2599                 if(axes[jst]==0xFFFF) axes[jst] = -1;
2600         return 0;
2601 }
2602
2603 static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
2604 {
2605         switch (mode) {
2606         case GAMEPORT_MODE_COOKED:
2607                 return 0;
2608         case GAMEPORT_MODE_RAW:
2609                 return 0;
2610         default:
2611                 return -1;
2612         }
2613         return 0;
2614 }
2615
2616 int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip)
2617 {
2618         struct gameport *gp;
2619
2620         chip->gameport = gp = gameport_allocate_port();
2621         if (!gp) {
2622                 printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n");
2623                 return -ENOMEM;
2624         }
2625
2626         gameport_set_name(gp, "CS46xx Gameport");
2627         gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2628         gameport_set_dev_parent(gp, &chip->pci->dev);
2629         gameport_set_port_data(gp, chip);
2630
2631         gp->open = snd_cs46xx_gameport_open;
2632         gp->read = snd_cs46xx_gameport_read;
2633         gp->trigger = snd_cs46xx_gameport_trigger;
2634         gp->cooked_read = snd_cs46xx_gameport_cooked_read;
2635
2636         snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
2637         snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
2638
2639         gameport_register_port(gp);
2640
2641         return 0;
2642 }
2643
2644 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
2645 {
2646         if (chip->gameport) {
2647                 gameport_unregister_port(chip->gameport);
2648                 chip->gameport = NULL;
2649         }
2650 }
2651 #else
2652 int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
2653 static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
2654 #endif /* CONFIG_GAMEPORT */
2655
2656 #ifdef CONFIG_PROC_FS
2657 /*
2658  *  proc interface
2659  */
2660
2661 static ssize_t snd_cs46xx_io_read(struct snd_info_entry *entry,
2662                                   void *file_private_data,
2663                                   struct file *file, char __user *buf,
2664                                   size_t count, loff_t pos)
2665 {
2666         struct snd_cs46xx_region *region = entry->private_data;
2667
2668         if (copy_to_user_fromio(buf, region->remap_addr + pos, count))
2669                 return -EFAULT;
2670         return count;
2671 }
2672
2673 static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
2674         .read = snd_cs46xx_io_read,
2675 };
2676
2677 static int __devinit snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
2678 {
2679         struct snd_info_entry *entry;
2680         int idx;
2681
2682         for (idx = 0; idx < 5; idx++) {
2683                 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2684                 if (! snd_card_proc_new(card, region->name, &entry)) {
2685                         entry->content = SNDRV_INFO_CONTENT_DATA;
2686                         entry->private_data = chip;
2687                         entry->c.ops = &snd_cs46xx_proc_io_ops;
2688                         entry->size = region->size;
2689                         entry->mode = S_IFREG | S_IRUSR;
2690                 }
2691         }
2692 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2693         cs46xx_dsp_proc_init(card, chip);
2694 #endif
2695         return 0;
2696 }
2697
2698 static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
2699 {
2700 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2701         cs46xx_dsp_proc_done(chip);
2702 #endif
2703         return 0;
2704 }
2705 #else /* !CONFIG_PROC_FS */
2706 #define snd_cs46xx_proc_init(card, chip)
2707 #define snd_cs46xx_proc_done(chip)
2708 #endif
2709
2710 /*
2711  * stop the h/w
2712  */
2713 static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
2714 {
2715         unsigned int tmp;
2716
2717         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
2718         tmp &= ~0x0000f03f;
2719         tmp |=  0x00000010;
2720         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt disable */
2721
2722         tmp = snd_cs46xx_peek(chip, BA1_CIE);
2723         tmp &= ~0x0000003f;
2724         tmp |=  0x00000011;
2725         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt disable */
2726
2727         /*
2728          *  Stop playback DMA.
2729          */
2730         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
2731         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
2732
2733         /*
2734          *  Stop capture DMA.
2735          */
2736         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
2737         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
2738
2739         /*
2740          *  Reset the processor.
2741          */
2742         snd_cs46xx_reset(chip);
2743
2744         snd_cs46xx_proc_stop(chip);
2745
2746         /*
2747          *  Power down the PLL.
2748          */
2749         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2750
2751         /*
2752          *  Turn off the Processor by turning off the software clock enable flag in
2753          *  the clock control register.
2754          */
2755         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
2756         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
2757 }
2758
2759
2760 static int snd_cs46xx_free(struct snd_cs46xx *chip)
2761 {
2762         int idx;
2763
2764         if (snd_BUG_ON(!chip))
2765                 return -EINVAL;
2766
2767         if (chip->active_ctrl)
2768                 chip->active_ctrl(chip, 1);
2769
2770         snd_cs46xx_remove_gameport(chip);
2771
2772         if (chip->amplifier_ctrl)
2773                 chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
2774
2775         snd_cs46xx_proc_done(chip);
2776
2777         if (chip->region.idx[0].resource)
2778                 snd_cs46xx_hw_stop(chip);
2779
2780         if (chip->irq >= 0)
2781                 free_irq(chip->irq, chip);
2782
2783         if (chip->active_ctrl)
2784                 chip->active_ctrl(chip, -chip->amplifier);
2785
2786         for (idx = 0; idx < 5; idx++) {
2787                 struct snd_cs46xx_region *region = &chip->region.idx[idx];
2788                 if (region->remap_addr)
2789                         iounmap(region->remap_addr);
2790                 release_and_free_resource(region->resource);
2791         }
2792
2793 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2794         if (chip->dsp_spos_instance) {
2795                 cs46xx_dsp_spos_destroy(chip);
2796                 chip->dsp_spos_instance = NULL;
2797         }
2798 #endif
2799
2800 #ifdef CONFIG_PM
2801         kfree(chip->saved_regs);
2802 #endif
2803
2804         pci_disable_device(chip->pci);
2805         kfree(chip);
2806         return 0;
2807 }
2808
2809 static int snd_cs46xx_dev_free(struct snd_device *device)
2810 {
2811         struct snd_cs46xx *chip = device->device_data;
2812         return snd_cs46xx_free(chip);
2813 }
2814
2815 /*
2816  *  initialize chip
2817  */
2818 static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
2819 {
2820         int timeout;
2821
2822         /*
2823          *  First, blast the clock control register to zero so that the PLL starts
2824          *  out in a known state, and blast the master serial port control register
2825          *  to zero so that the serial ports also start out in a known state.
2826          */
2827         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
2828         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
2829
2830         /*
2831          *  If we are in AC97 mode, then we must set the part to a host controlled
2832          *  AC-link.  Otherwise, we won't be able to bring up the link.
2833          */
2834 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2835         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
2836                            SERACC_TWO_CODECS);  /* 2.00 dual codecs */
2837         /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
2838 #else
2839         snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
2840 #endif
2841
2842         /*
2843          *  Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
2844          *  spec) and then drive it high.  This is done for non AC97 modes since
2845          *  there might be logic external to the CS461x that uses the ARST# line
2846          *  for a reset.
2847          */
2848         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
2849 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2850         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
2851 #endif
2852         udelay(50);
2853         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
2854 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2855         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
2856 #endif
2857
2858         /*
2859          *  The first thing we do here is to enable sync generation.  As soon
2860          *  as we start receiving bit clock, we'll start producing the SYNC
2861          *  signal.
2862          */
2863         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
2864 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2865         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
2866 #endif
2867
2868         /*
2869          *  Now wait for a short while to allow the AC97 part to start
2870          *  generating bit clock (so we don't try to start the PLL without an
2871          *  input clock).
2872          */
2873         mdelay(10);
2874
2875         /*
2876          *  Set the serial port timing configuration, so that
2877          *  the clock control circuit gets its clock from the correct place.
2878          */
2879         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
2880
2881         /*
2882          *  Write the selected clock control setup to the hardware.  Do not turn on
2883          *  SWCE yet (if requested), so that the devices clocked by the output of
2884          *  PLL are not clocked until the PLL is stable.
2885          */
2886         snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
2887         snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
2888         snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
2889
2890         /*
2891          *  Power up the PLL.
2892          */
2893         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
2894
2895         /*
2896          *  Wait until the PLL has stabilized.
2897          */
2898         msleep(100);
2899
2900         /*
2901          *  Turn on clocking of the core so that we can setup the serial ports.
2902          */
2903         snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
2904
2905         /*
2906          * Enable FIFO  Host Bypass
2907          */
2908         snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
2909
2910         /*
2911          *  Fill the serial port FIFOs with silence.
2912          */
2913         snd_cs46xx_clear_serial_FIFOs(chip);
2914
2915         /*
2916          *  Set the serial port FIFO pointer to the first sample in the FIFO.
2917          */
2918         /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
2919
2920         /*
2921          *  Write the serial port configuration to the part.  The master
2922          *  enable bit is not set until all other values have been written.
2923          */
2924         snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
2925         snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
2926         snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
2927
2928
2929 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2930         snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
2931         snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
2932         snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
2933         snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
2934         snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
2935 #endif
2936
2937         mdelay(5);
2938
2939
2940         /*
2941          * Wait for the codec ready signal from the AC97 codec.
2942          */
2943         timeout = 150;
2944         while (timeout-- > 0) {
2945                 /*
2946                  *  Read the AC97 status register to see if we've seen a CODEC READY
2947                  *  signal from the AC97 codec.
2948                  */
2949                 if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
2950                         goto ok1;
2951                 msleep(10);
2952         }
2953
2954
2955         snd_printk(KERN_ERR "create - never read codec ready from AC'97\n");
2956         snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n");
2957         return -EIO;
2958  ok1:
2959 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2960         {
2961                 int count;
2962                 for (count = 0; count < 150; count++) {
2963                         /* First, we want to wait for a short time. */
2964                         udelay(25);
2965
2966                         if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
2967                                 break;
2968                 }
2969
2970                 /*
2971                  *  Make sure CODEC is READY.
2972                  */
2973                 if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
2974                         snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
2975         }
2976 #endif
2977
2978         /*
2979          *  Assert the vaid frame signal so that we can start sending commands
2980          *  to the AC97 codec.
2981          */
2982         snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
2983 #ifdef CONFIG_SND_CS46XX_NEW_DSP
2984         snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
2985 #endif
2986
2987
2988         /*
2989          *  Wait until we've sampled input slots 3 and 4 as valid, meaning that
2990          *  the codec is pumping ADC data across the AC-link.
2991          */
2992         timeout = 150;
2993         while (timeout-- > 0) {
2994                 /*
2995                  *  Read the input slot valid register and see if input slots 3 and
2996                  *  4 are valid yet.
2997                  */
2998                 if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
2999                         goto ok2;
3000                 msleep(10);
3001         }
3002
3003 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3004         snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n");
3005         return -EIO;
3006 #else
3007         /* This may happen on a cold boot with a Terratec SiXPack 5.1.
3008            Reloading the driver may help, if there's other soundcards
3009            with the same problem I would like to know. (Benny) */
3010
3011         snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
3012         snd_printk(KERN_ERR "       Try reloading the ALSA driver, if you find something\n");
3013         snd_printk(KERN_ERR "       broken or not working on your soundcard upon\n");
3014         snd_printk(KERN_ERR "       this message please report to alsa-devel@alsa-project.org\n");
3015
3016         return -EIO;
3017 #endif
3018  ok2:
3019
3020         /*
3021          *  Now, assert valid frame and the slot 3 and 4 valid bits.  This will
3022          *  commense the transfer of digital audio data to the AC97 codec.
3023          */
3024
3025         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
3026
3027
3028         /*
3029          *  Power down the DAC and ADC.  We will power them up (if) when we need
3030          *  them.
3031          */
3032         /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
3033
3034         /*
3035          *  Turn off the Processor by turning off the software clock enable flag in
3036          *  the clock control register.
3037          */
3038         /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
3039         /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
3040
3041         return 0;
3042 }
3043
3044 /*
3045  *  start and load DSP
3046  */
3047
3048 static void cs46xx_enable_stream_irqs(struct snd_cs46xx *chip)
3049 {
3050         unsigned int tmp;
3051
3052         snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
3053
3054         tmp = snd_cs46xx_peek(chip, BA1_PFIE);
3055         tmp &= ~0x0000f03f;
3056         snd_cs46xx_poke(chip, BA1_PFIE, tmp);   /* playback interrupt enable */
3057
3058         tmp = snd_cs46xx_peek(chip, BA1_CIE);
3059         tmp &= ~0x0000003f;
3060         tmp |=  0x00000001;
3061         snd_cs46xx_poke(chip, BA1_CIE, tmp);    /* capture interrupt enable */
3062 }
3063
3064 int __devinit snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
3065 {
3066         unsigned int tmp;
3067         /*
3068          *  Reset the processor.
3069          */
3070         snd_cs46xx_reset(chip);
3071         /*
3072          *  Download the image to the processor.
3073          */
3074 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3075 #if 0
3076         if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
3077                 snd_printk(KERN_ERR "image download error\n");
3078                 return -EIO;
3079         }
3080 #endif
3081
3082         if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
3083                 snd_printk(KERN_ERR "image download error [cwc4630]\n");
3084                 return -EIO;
3085         }
3086
3087         if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
3088                 snd_printk(KERN_ERR "image download error [cwcasync]\n");
3089                 return -EIO;
3090         }
3091
3092         if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
3093                 snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
3094                 return -EIO;
3095         }
3096
3097         if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
3098                 snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
3099                 return -EIO;
3100         }
3101
3102         if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
3103                 snd_printk(KERN_ERR "image download error [cwcdma]\n");
3104                 return -EIO;
3105         }
3106
3107         if (cs46xx_dsp_scb_and_task_init(chip) < 0)
3108                 return -EIO;
3109 #else
3110         /* old image */
3111         if (snd_cs46xx_download_image(chip) < 0) {
3112                 snd_printk(KERN_ERR "image download error\n");
3113                 return -EIO;
3114         }
3115
3116         /*
3117          *  Stop playback DMA.
3118          */
3119         tmp = snd_cs46xx_peek(chip, BA1_PCTL);
3120         chip->play_ctl = tmp & 0xffff0000;
3121         snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
3122 #endif
3123
3124         /*
3125          *  Stop capture DMA.
3126          */
3127         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3128         chip->capt.ctl = tmp & 0x0000ffff;
3129         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3130
3131         mdelay(5);
3132
3133         snd_cs46xx_set_play_sample_rate(chip, 8000);
3134         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3135
3136         snd_cs46xx_proc_start(chip);
3137
3138         cs46xx_enable_stream_irqs(chip);
3139
3140 #ifndef CONFIG_SND_CS46XX_NEW_DSP
3141         /* set the attenuation to 0dB */
3142         snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
3143         snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
3144 #endif
3145
3146         return 0;
3147 }
3148
3149
3150 /*
3151  *      AMP control - null AMP
3152  */
3153
3154 static void amp_none(struct snd_cs46xx *chip, int change)
3155 {
3156 }
3157
3158 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3159 static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
3160 {
3161
3162         u32 idx, valid_slots,tmp,powerdown = 0;
3163         u16 modem_power,pin_config,logic_type;
3164
3165         snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
3166
3167         /*
3168          *  See if the devices are powered down.  If so, we must power them up first
3169          *  or they will not respond.
3170          */
3171         tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
3172
3173         if (!(tmp & CLKCR1_SWCE)) {
3174                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
3175                 powerdown = 1;
3176         }
3177
3178         /*
3179          * Clear PRA.  The Bonzo chip will be used for GPIO not for modem
3180          * stuff.
3181          */
3182         if(chip->nr_ac97_codecs != 2) {
3183                 snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
3184                 return -EINVAL;
3185         }
3186
3187         modem_power = snd_cs46xx_codec_read (chip,
3188                                              AC97_EXTENDED_MSTATUS,
3189                                              CS46XX_SECONDARY_CODEC_INDEX);
3190         modem_power &=0xFEFF;
3191
3192         snd_cs46xx_codec_write(chip,
3193                                AC97_EXTENDED_MSTATUS, modem_power,
3194                                CS46XX_SECONDARY_CODEC_INDEX);
3195
3196         /*
3197          * Set GPIO pin's 7 and 8 so that they are configured for output.
3198          */
3199         pin_config = snd_cs46xx_codec_read (chip,
3200                                             AC97_GPIO_CFG,
3201                                             CS46XX_SECONDARY_CODEC_INDEX);
3202         pin_config &=0x27F;
3203
3204         snd_cs46xx_codec_write(chip,
3205                                AC97_GPIO_CFG, pin_config,
3206                                CS46XX_SECONDARY_CODEC_INDEX);
3207
3208         /*
3209          * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
3210          */
3211
3212         logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
3213                                            CS46XX_SECONDARY_CODEC_INDEX);
3214         logic_type &=0x27F;
3215
3216         snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
3217                                 CS46XX_SECONDARY_CODEC_INDEX);
3218
3219         valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
3220         valid_slots |= 0x200;
3221         snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
3222
3223         if ( cs46xx_wait_for_fifo(chip,1) ) {
3224           snd_printdd("FIFO is busy\n");
3225
3226           return -EINVAL;
3227         }
3228
3229         /*
3230          * Fill slots 12 with the correct value for the GPIO pins.
3231          */
3232         for(idx = 0x90; idx <= 0x9F; idx++) {
3233                 /*
3234                  * Initialize the fifo so that bits 7 and 8 are on.
3235                  *
3236                  * Remember that the GPIO pins in bonzo are shifted by 4 bits to
3237                  * the left.  0x1800 corresponds to bits 7 and 8.
3238                  */
3239                 snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
3240
3241                 /*
3242                  * Wait for command to complete
3243                  */
3244                 if ( cs46xx_wait_for_fifo(chip,200) ) {
3245                         snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
3246
3247                         return -EINVAL;
3248                 }
3249
3250                 /*
3251                  * Write the serial port FIFO index.
3252                  */
3253                 snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
3254
3255                 /*
3256                  * Tell the serial port to load the new value into the FIFO location.
3257                  */
3258                 snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
3259         }
3260
3261         /* wait for last command to complete */
3262         cs46xx_wait_for_fifo(chip,200);
3263
3264         /*
3265          *  Now, if we powered up the devices, then power them back down again.
3266          *  This is kinda ugly, but should never happen.
3267          */
3268         if (powerdown)
3269                 snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
3270
3271         return 0;
3272 }
3273 #endif
3274
3275 /*
3276  *      Crystal EAPD mode
3277  */
3278
3279 static void amp_voyetra(struct snd_cs46xx *chip, int change)
3280 {
3281         /* Manage the EAPD bit on the Crystal 4297
3282            and the Analog AD1885 */
3283
3284 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3285         int old = chip->amplifier;
3286 #endif
3287         int oval, val;
3288
3289         chip->amplifier += change;
3290         oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
3291                                      CS46XX_PRIMARY_CODEC_INDEX);
3292         val = oval;
3293         if (chip->amplifier) {
3294                 /* Turn the EAPD amp on */
3295                 val |= 0x8000;
3296         } else {
3297                 /* Turn the EAPD amp off */
3298                 val &= ~0x8000;
3299         }
3300         if (val != oval) {
3301                 snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
3302                                        CS46XX_PRIMARY_CODEC_INDEX);
3303                 if (chip->eapd_switch)
3304                         snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
3305                                        &chip->eapd_switch->id);
3306         }
3307
3308 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3309         if (chip->amplifier && !old) {
3310                 voyetra_setup_eapd_slot(chip);
3311         }
3312 #endif
3313 }
3314
3315 static void hercules_init(struct snd_cs46xx *chip)
3316 {
3317         /* default: AMP off, and SPDIF input optical */
3318         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3319         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3320 }
3321
3322
3323 /*
3324  *      Game Theatre XP card - EGPIO[2] is used to enable the external amp.
3325  */
3326 static void amp_hercules(struct snd_cs46xx *chip, int change)
3327 {
3328         int old = chip->amplifier;
3329         int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
3330         int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
3331
3332         chip->amplifier += change;
3333         if (chip->amplifier && !old) {
3334                 snd_printdd ("Hercules amplifier ON\n");
3335
3336                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
3337                                    EGPIODR_GPOE2 | val1);     /* enable EGPIO2 output */
3338                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
3339                                    EGPIOPTR_GPPT2 | val2);   /* open-drain on output */
3340         } else if (old && !chip->amplifier) {
3341                 snd_printdd ("Hercules amplifier OFF\n");
3342                 snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,  val1 & ~EGPIODR_GPOE2); /* disable */
3343                 snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
3344         }
3345 }
3346
3347 static void voyetra_mixer_init (struct snd_cs46xx *chip)
3348 {
3349         snd_printdd ("initializing Voyetra mixer\n");
3350
3351         /* Enable SPDIF out */
3352         snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
3353         snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
3354 }
3355
3356 static void hercules_mixer_init (struct snd_cs46xx *chip)
3357 {
3358 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3359         unsigned int idx;
3360         int err;
3361         struct snd_card *card = chip->card;
3362 #endif
3363
3364         /* set EGPIO to default */
3365         hercules_init(chip);
3366
3367         snd_printdd ("initializing Hercules mixer\n");
3368
3369 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3370         if (chip->in_suspend)
3371                 return;
3372
3373         for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
3374                 struct snd_kcontrol *kctl;
3375
3376                 kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
3377                 if ((err = snd_ctl_add(card, kctl)) < 0) {
3378                         printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
3379                         break;
3380                 }
3381         }
3382 #endif
3383 }
3384
3385
3386 #if 0
3387 /*
3388  *      Untested
3389  */
3390
3391 static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
3392 {
3393         chip->amplifier += change;
3394
3395         if (chip->amplifier) {
3396                 /* Switch the GPIO pins 7 and 8 to open drain */
3397                 snd_cs46xx_codec_write(chip, 0x4C,
3398                                        snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
3399                 snd_cs46xx_codec_write(chip, 0x4E,
3400                                        snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
3401                 /* Now wake the AMP (this might be backwards) */
3402                 snd_cs46xx_codec_write(chip, 0x54,
3403                                        snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
3404         } else {
3405                 snd_cs46xx_codec_write(chip, 0x54,
3406                                        snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
3407         }
3408 }
3409 #endif
3410
3411
3412 /*
3413  *      Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
3414  *      whenever we need to beat on the chip.
3415  *
3416  *      The original idea and code for this hack comes from David Kaiser at
3417  *      Linuxcare. Perhaps one day Crystal will document their chips well
3418  *      enough to make them useful.
3419  */
3420
3421 static void clkrun_hack(struct snd_cs46xx *chip, int change)
3422 {
3423         u16 control, nval;
3424
3425         if (!chip->acpi_port)
3426                 return;
3427
3428         chip->amplifier += change;
3429
3430         /* Read ACPI port */
3431         nval = control = inw(chip->acpi_port + 0x10);
3432
3433         /* Flip CLKRUN off while running */
3434         if (! chip->amplifier)
3435                 nval |= 0x2000;
3436         else
3437                 nval &= ~0x2000;
3438         if (nval != control)
3439                 outw(nval, chip->acpi_port + 0x10);
3440 }
3441
3442
3443 /*
3444  * detect intel piix4
3445  */
3446 static void clkrun_init(struct snd_cs46xx *chip)
3447 {
3448         struct pci_dev *pdev;
3449         u8 pp;
3450
3451         chip->acpi_port = 0;
3452
3453         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
3454                 PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
3455         if (pdev == NULL)
3456                 return;         /* Not a thinkpad thats for sure */
3457
3458         /* Find the control port */
3459         pci_read_config_byte(pdev, 0x41, &pp);
3460         chip->acpi_port = pp << 8;
3461         pci_dev_put(pdev);
3462 }
3463
3464
3465 /*
3466  * Card subid table
3467  */
3468
3469 struct cs_card_type
3470 {
3471         u16 vendor;
3472         u16 id;
3473         char *name;
3474         void (*init)(struct snd_cs46xx *);
3475         void (*amp)(struct snd_cs46xx *, int);
3476         void (*active)(struct snd_cs46xx *, int);
3477         void (*mixer_init)(struct snd_cs46xx *);
3478 };
3479
3480 static struct cs_card_type __devinitdata cards[] = {
3481         {
3482                 .vendor = 0x1489,
3483                 .id = 0x7001,
3484                 .name = "Genius Soundmaker 128 value",
3485                 /* nothing special */
3486         },
3487         {
3488                 .vendor = 0x5053,
3489                 .id = 0x3357,
3490                 .name = "Voyetra",
3491                 .amp = amp_voyetra,
3492                 .mixer_init = voyetra_mixer_init,
3493         },
3494         {
3495                 .vendor = 0x1071,
3496                 .id = 0x6003,
3497                 .name = "Mitac MI6020/21",
3498                 .amp = amp_voyetra,
3499         },
3500         /* Hercules Game Theatre XP */
3501         {
3502                 .vendor = 0x14af, /* Guillemot Corporation */
3503                 .id = 0x0050,
3504                 .name = "Hercules Game Theatre XP",
3505                 .amp = amp_hercules,
3506                 .mixer_init = hercules_mixer_init,
3507         },
3508         {
3509                 .vendor = 0x1681,
3510                 .id = 0x0050,
3511                 .name = "Hercules Game Theatre XP",
3512                 .amp = amp_hercules,
3513                 .mixer_init = hercules_mixer_init,
3514         },
3515         {
3516                 .vendor = 0x1681,
3517                 .id = 0x0051,
3518                 .name = "Hercules Game Theatre XP",
3519                 .amp = amp_hercules,
3520                 .mixer_init = hercules_mixer_init,
3521
3522         },
3523         {
3524                 .vendor = 0x1681,
3525                 .id = 0x0052,
3526                 .name = "Hercules Game Theatre XP",
3527                 .amp = amp_hercules,
3528                 .mixer_init = hercules_mixer_init,
3529         },
3530         {
3531                 .vendor = 0x1681,
3532                 .id = 0x0053,
3533                 .name = "Hercules Game Theatre XP",
3534                 .amp = amp_hercules,
3535                 .mixer_init = hercules_mixer_init,
3536         },
3537         {
3538                 .vendor = 0x1681,
3539                 .id = 0x0054,
3540                 .name = "Hercules Game Theatre XP",
3541                 .amp = amp_hercules,
3542                 .mixer_init = hercules_mixer_init,
3543         },
3544         /* Herculess Fortissimo */
3545         {
3546                 .vendor = 0x1681,
3547                 .id = 0xa010,
3548                 .name = "Hercules Gamesurround Fortissimo II",
3549         },
3550         {
3551                 .vendor = 0x1681,
3552                 .id = 0xa011,
3553                 .name = "Hercules Gamesurround Fortissimo III 7.1",
3554         },
3555         /* Teratec */
3556         {
3557                 .vendor = 0x153b,
3558                 .id = 0x112e,
3559                 .name = "Terratec DMX XFire 1024",
3560         },
3561         {
3562                 .vendor = 0x153b,
3563                 .id = 0x1136,
3564                 .name = "Terratec SiXPack 5.1",
3565         },
3566         /* Not sure if the 570 needs the clkrun hack */
3567         {
3568                 .vendor = PCI_VENDOR_ID_IBM,
3569                 .id = 0x0132,
3570                 .name = "Thinkpad 570",
3571                 .init = clkrun_init,
3572                 .active = clkrun_hack,
3573         },
3574         {
3575                 .vendor = PCI_VENDOR_ID_IBM,
3576                 .id = 0x0153,
3577                 .name = "Thinkpad 600X/A20/T20",
3578                 .init = clkrun_init,
3579                 .active = clkrun_hack,
3580         },
3581         {
3582                 .vendor = PCI_VENDOR_ID_IBM,
3583                 .id = 0x1010,
3584                 .name = "Thinkpad 600E (unsupported)",
3585         },
3586         {} /* terminator */
3587 };
3588
3589
3590 /*
3591  * APM support
3592  */
3593 #ifdef CONFIG_PM
3594 static unsigned int saved_regs[] = {
3595         BA0_ACOSV,
3596         /*BA0_ASER_FADDR,*/
3597         BA0_ASER_MASTER,
3598         BA1_PVOL,
3599         BA1_CVOL,
3600 };
3601
3602 static int snd_cs46xx_suspend(struct device *dev)
3603 {
3604         struct pci_dev *pci = to_pci_dev(dev);
3605         struct snd_card *card = dev_get_drvdata(dev);
3606         struct snd_cs46xx *chip = card->private_data;
3607         int i, amp_saved;
3608
3609         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3610         chip->in_suspend = 1;
3611         snd_pcm_suspend_all(chip->pcm);
3612         // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
3613         // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
3614
3615         snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3616         snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3617
3618         /* save some registers */
3619         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3620                 chip->saved_regs[i] = snd_cs46xx_peekBA0(chip, saved_regs[i]);
3621
3622         amp_saved = chip->amplifier;
3623         /* turn off amp */
3624         chip->amplifier_ctrl(chip, -chip->amplifier);
3625         snd_cs46xx_hw_stop(chip);
3626         /* disable CLKRUN */
3627         chip->active_ctrl(chip, -chip->amplifier);
3628         chip->amplifier = amp_saved; /* restore the status */
3629
3630         pci_disable_device(pci);
3631         pci_save_state(pci);
3632         pci_set_power_state(pci, PCI_D3hot);
3633         return 0;
3634 }
3635
3636 static int snd_cs46xx_resume(struct device *dev)
3637 {
3638         struct pci_dev *pci = to_pci_dev(dev);
3639         struct snd_card *card = dev_get_drvdata(dev);
3640         struct snd_cs46xx *chip = card->private_data;
3641         int amp_saved;
3642 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3643         int i;
3644 #endif
3645         unsigned int tmp;
3646
3647         pci_set_power_state(pci, PCI_D0);
3648         pci_restore_state(pci);
3649         if (pci_enable_device(pci) < 0) {
3650                 printk(KERN_ERR "cs46xx: pci_enable_device failed, "
3651                        "disabling device\n");
3652                 snd_card_disconnect(card);
3653                 return -EIO;
3654         }
3655         pci_set_master(pci);
3656
3657         amp_saved = chip->amplifier;
3658         chip->amplifier = 0;
3659         chip->active_ctrl(chip, 1); /* force to on */
3660
3661         snd_cs46xx_chip_init(chip);
3662
3663         snd_cs46xx_reset(chip);
3664 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3665         cs46xx_dsp_resume(chip);
3666         /* restore some registers */
3667         for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
3668                 snd_cs46xx_pokeBA0(chip, saved_regs[i], chip->saved_regs[i]);
3669 #else
3670         snd_cs46xx_download_image(chip);
3671 #endif
3672
3673 #if 0
3674         snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
3675                                chip->ac97_general_purpose);
3676         snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
3677                                chip->ac97_powerdown);
3678         mdelay(10);
3679         snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
3680                                chip->ac97_powerdown);
3681         mdelay(5);
3682 #endif
3683
3684         snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
3685         snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
3686
3687         /*
3688          *  Stop capture DMA.
3689          */
3690         tmp = snd_cs46xx_peek(chip, BA1_CCTL);
3691         chip->capt.ctl = tmp & 0x0000ffff;
3692         snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
3693
3694         mdelay(5);
3695
3696         /* reset playback/capture */
3697         snd_cs46xx_set_play_sample_rate(chip, 8000);
3698         snd_cs46xx_set_capture_sample_rate(chip, 8000);
3699         snd_cs46xx_proc_start(chip);
3700
3701         cs46xx_enable_stream_irqs(chip);
3702
3703         if (amp_saved)
3704                 chip->amplifier_ctrl(chip, 1); /* turn amp on */
3705         else
3706                 chip->active_ctrl(chip, -1); /* disable CLKRUN */
3707         chip->amplifier = amp_saved;
3708         chip->in_suspend = 0;
3709         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3710         return 0;
3711 }
3712
3713 SIMPLE_DEV_PM_OPS(snd_cs46xx_pm, snd_cs46xx_suspend, snd_cs46xx_resume);
3714 #endif /* CONFIG_PM */
3715
3716
3717 /*
3718  */
3719
3720 int __devinit snd_cs46xx_create(struct snd_card *card,
3721                       struct pci_dev * pci,
3722                       int external_amp, int thinkpad,
3723                       struct snd_cs46xx ** rchip)
3724 {
3725         struct snd_cs46xx *chip;
3726         int err, idx;
3727         struct snd_cs46xx_region *region;
3728         struct cs_card_type *cp;
3729         u16 ss_card, ss_vendor;
3730         static struct snd_device_ops ops = {
3731                 .dev_free =     snd_cs46xx_dev_free,
3732         };
3733
3734         *rchip = NULL;
3735
3736         /* enable PCI device */
3737         if ((err = pci_enable_device(pci)) < 0)
3738                 return err;
3739
3740         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3741         if (chip == NULL) {
3742                 pci_disable_device(pci);
3743                 return -ENOMEM;
3744         }
3745         spin_lock_init(&chip->reg_lock);
3746 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3747         mutex_init(&chip->spos_mutex);
3748 #endif
3749         chip->card = card;
3750         chip->pci = pci;
3751         chip->irq = -1;
3752         chip->ba0_addr = pci_resource_start(pci, 0);
3753         chip->ba1_addr = pci_resource_start(pci, 1);
3754         if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
3755             chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
3756                 snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
3757                            chip->ba0_addr, chip->ba1_addr);
3758                 snd_cs46xx_free(chip);
3759                 return -ENOMEM;
3760         }
3761
3762         region = &chip->region.name.ba0;
3763         strcpy(region->name, "CS46xx_BA0");
3764         region->base = chip->ba0_addr;
3765         region->size = CS46XX_BA0_SIZE;
3766
3767         region = &chip->region.name.data0;
3768         strcpy(region->name, "CS46xx_BA1_data0");
3769         region->base = chip->ba1_addr + BA1_SP_DMEM0;
3770         region->size = CS46XX_BA1_DATA0_SIZE;
3771
3772         region = &chip->region.name.data1;
3773         strcpy(region->name, "CS46xx_BA1_data1");
3774         region->base = chip->ba1_addr + BA1_SP_DMEM1;
3775         region->size = CS46XX_BA1_DATA1_SIZE;
3776
3777         region = &chip->region.name.pmem;
3778         strcpy(region->name, "CS46xx_BA1_pmem");
3779         region->base = chip->ba1_addr + BA1_SP_PMEM;
3780         region->size = CS46XX_BA1_PRG_SIZE;
3781
3782         region = &chip->region.name.reg;
3783         strcpy(region->name, "CS46xx_BA1_reg");
3784         region->base = chip->ba1_addr + BA1_SP_REG;
3785         region->size = CS46XX_BA1_REG_SIZE;
3786
3787         /* set up amp and clkrun hack */
3788         pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
3789         pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
3790
3791         for (cp = &cards[0]; cp->name; cp++) {
3792                 if (cp->vendor == ss_vendor && cp->id == ss_card) {
3793                         snd_printdd ("hack for %s enabled\n", cp->name);
3794
3795                         chip->amplifier_ctrl = cp->amp;
3796                         chip->active_ctrl = cp->active;
3797                         chip->mixer_init = cp->mixer_init;
3798
3799                         if (cp->init)
3800                                 cp->init(chip);
3801                         break;
3802                 }
3803         }
3804
3805         if (external_amp) {
3806                 snd_printk(KERN_INFO "Crystal EAPD support forced on.\n");
3807                 chip->amplifier_ctrl = amp_voyetra;
3808         }
3809
3810         if (thinkpad) {
3811                 snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n");
3812                 chip->active_ctrl = clkrun_hack;
3813                 clkrun_init(chip);
3814         }
3815
3816         if (chip->amplifier_ctrl == NULL)
3817                 chip->amplifier_ctrl = amp_none;
3818         if (chip->active_ctrl == NULL)
3819                 chip->active_ctrl = amp_none;
3820
3821         chip->active_ctrl(chip, 1); /* enable CLKRUN */
3822
3823         pci_set_master(pci);
3824
3825         for (idx = 0; idx < 5; idx++) {
3826                 region = &chip->region.idx[idx];
3827                 if ((region->resource = request_mem_region(region->base, region->size,
3828                                                            region->name)) == NULL) {
3829                         snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n",
3830                                    region->base, region->base + region->size - 1);
3831                         snd_cs46xx_free(chip);
3832                         return -EBUSY;
3833                 }
3834                 region->remap_addr = ioremap_nocache(region->base, region->size);
3835                 if (region->remap_addr == NULL) {
3836                         snd_printk(KERN_ERR "%s ioremap problem\n", region->name);
3837                         snd_cs46xx_free(chip);
3838                         return -ENOMEM;
3839                 }
3840         }
3841
3842         if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
3843                         KBUILD_MODNAME, chip)) {
3844                 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
3845                 snd_cs46xx_free(chip);
3846                 return -EBUSY;
3847         }
3848         chip->irq = pci->irq;
3849
3850 #ifdef CONFIG_SND_CS46XX_NEW_DSP
3851         chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
3852         if (chip->dsp_spos_instance == NULL) {
3853                 snd_cs46xx_free(chip);
3854                 return -ENOMEM;
3855         }
3856 #endif
3857
3858         err = snd_cs46xx_chip_init(chip);
3859         if (err < 0) {
3860                 snd_cs46xx_free(chip);
3861                 return err;
3862         }
3863
3864         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
3865                 snd_cs46xx_free(chip);
3866                 return err;
3867         }
3868
3869         snd_cs46xx_proc_init(card, chip);
3870
3871 #ifdef CONFIG_PM
3872         chip->saved_regs = kmalloc(sizeof(*chip->saved_regs) *
3873                                    ARRAY_SIZE(saved_regs), GFP_KERNEL);
3874         if (!chip->saved_regs) {
3875                 snd_cs46xx_free(chip);
3876                 return -ENOMEM;
3877         }
3878 #endif
3879
3880         chip->active_ctrl(chip, -1); /* disable CLKRUN */
3881
3882         snd_card_set_dev(card, &pci->dev);
3883
3884         *rchip = chip;
3885         return 0;
3886 }