include/linux/mfd/samsung/irq.h

   1 /* irq.h
   2  *
   3  * Copyright (c) 2012 Samsung Electronics Co., Ltd
   4  *              http://www.samsung.com
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  */
  12
  13 #ifndef __LINUX_MFD_SEC_IRQ_H
  14 #define __LINUX_MFD_SEC_IRQ_H
  15
  16 enum s2mps11_irq {
  17         S2MPS11_IRQ_PWRONF,
  18         S2MPS11_IRQ_PWRONR,
  19         S2MPS11_IRQ_JIGONBF,
  20         S2MPS11_IRQ_JIGONBR,
  21         S2MPS11_IRQ_ACOKBF,
  22         S2MPS11_IRQ_ACOKBR,
  23         S2MPS11_IRQ_PWRON1S,
  24         S2MPS11_IRQ_MRB,
  25
  26         S2MPS11_IRQ_RTC60S,
  27         S2MPS11_IRQ_RTCA0,
  28         S2MPS11_IRQ_RTCA1,
  29         S2MPS11_IRQ_SMPL,
  30         S2MPS11_IRQ_RTC1S,
  31         S2MPS11_IRQ_WTSR,
  32
  33         S2MPS11_IRQ_INT120C,
  34         S2MPS11_IRQ_INT140C,
  35
  36         S2MPS11_IRQ_NR,
  37 };
  38
  39 #define S2MPS11_IRQ_PWRONF_MASK         (1 << 0)
  40 #define S2MPS11_IRQ_PWRONR_MASK         (1 << 1)
  41 #define S2MPS11_IRQ_JIGONBF_MASK        (1 << 2)
  42 #define S2MPS11_IRQ_JIGONBR_MASK        (1 << 3)
  43 #define S2MPS11_IRQ_ACOKBF_MASK         (1 << 4)
  44 #define S2MPS11_IRQ_ACOKBR_MASK         (1 << 5)
  45 #define S2MPS11_IRQ_PWRON1S_MASK        (1 << 6)
  46 #define S2MPS11_IRQ_MRB_MASK            (1 << 7)
  47
  48 #define S2MPS11_IRQ_RTC60S_MASK         (1 << 0)
  49 #define S2MPS11_IRQ_RTCA1_MASK          (1 << 1)
  50 #define S2MPS11_IRQ_RTCA0_MASK          (1 << 2)
  51 #define S2MPS11_IRQ_SMPL_MASK           (1 << 3)
  52 #define S2MPS11_IRQ_RTC1S_MASK          (1 << 4)
  53 #define S2MPS11_IRQ_WTSR_MASK           (1 << 5)
  54
  55 #define S2MPS11_IRQ_INT120C_MASK        (1 << 0)
  56 #define S2MPS11_IRQ_INT140C_MASK        (1 << 1)
  57
  58 enum s5m8767_irq {
  59         S5M8767_IRQ_PWRR,
  60         S5M8767_IRQ_PWRF,
  61         S5M8767_IRQ_PWR1S,
  62         S5M8767_IRQ_JIGR,
  63         S5M8767_IRQ_JIGF,
  64         S5M8767_IRQ_LOWBAT2,
  65         S5M8767_IRQ_LOWBAT1,
  66
  67         S5M8767_IRQ_MRB,
  68         S5M8767_IRQ_DVSOK2,
  69         S5M8767_IRQ_DVSOK3,
  70         S5M8767_IRQ_DVSOK4,
  71
  72         S5M8767_IRQ_RTC60S,
  73         S5M8767_IRQ_RTCA1,
  74         S5M8767_IRQ_RTCA2,
  75         S5M8767_IRQ_SMPL,
  76         S5M8767_IRQ_RTC1S,
  77         S5M8767_IRQ_WTSR,
  78
  79         S5M8767_IRQ_NR,
  80 };
  81
  82 #define S5M8767_IRQ_PWRR_MASK           (1 << 0)
  83 #define S5M8767_IRQ_PWRF_MASK           (1 << 1)
  84 #define S5M8767_IRQ_PWR1S_MASK          (1 << 3)
  85 #define S5M8767_IRQ_JIGR_MASK           (1 << 4)
  86 #define S5M8767_IRQ_JIGF_MASK           (1 << 5)
  87 #define S5M8767_IRQ_LOWBAT2_MASK        (1 << 6)
  88 #define S5M8767_IRQ_LOWBAT1_MASK        (1 << 7)
  89
  90 #define S5M8767_IRQ_MRB_MASK            (1 << 2)
  91 #define S5M8767_IRQ_DVSOK2_MASK         (1 << 3)
  92 #define S5M8767_IRQ_DVSOK3_MASK         (1 << 4)
  93 #define S5M8767_IRQ_DVSOK4_MASK         (1 << 5)
  94
  95 #define S5M8767_IRQ_RTC60S_MASK         (1 << 0)
  96 #define S5M8767_IRQ_RTCA1_MASK          (1 << 1)
  97 #define S5M8767_IRQ_RTCA2_MASK          (1 << 2)
  98 #define S5M8767_IRQ_SMPL_MASK           (1 << 3)
  99 #define S5M8767_IRQ_RTC1S_MASK          (1 << 4)
 100 #define S5M8767_IRQ_WTSR_MASK           (1 << 5)
 101
 102 enum s5m8763_irq {
 103         S5M8763_IRQ_DCINF,
 104         S5M8763_IRQ_DCINR,
 105         S5M8763_IRQ_JIGF,
 106         S5M8763_IRQ_JIGR,
 107         S5M8763_IRQ_PWRONF,
 108         S5M8763_IRQ_PWRONR,
 109
 110         S5M8763_IRQ_WTSREVNT,
 111         S5M8763_IRQ_SMPLEVNT,
 112         S5M8763_IRQ_ALARM1,
 113         S5M8763_IRQ_ALARM0,
 114
 115         S5M8763_IRQ_ONKEY1S,
 116         S5M8763_IRQ_TOPOFFR,
 117         S5M8763_IRQ_DCINOVPR,
 118         S5M8763_IRQ_CHGRSTF,
 119         S5M8763_IRQ_DONER,
 120         S5M8763_IRQ_CHGFAULT,
 121
 122         S5M8763_IRQ_LOBAT1,
 123         S5M8763_IRQ_LOBAT2,
 124
 125         S5M8763_IRQ_NR,
 126 };
 127
 128 #define S5M8763_IRQ_DCINF_MASK          (1 << 2)
 129 #define S5M8763_IRQ_DCINR_MASK          (1 << 3)
 130 #define S5M8763_IRQ_JIGF_MASK           (1 << 4)
 131 #define S5M8763_IRQ_JIGR_MASK           (1 << 5)
 132 #define S5M8763_IRQ_PWRONF_MASK         (1 << 6)
 133 #define S5M8763_IRQ_PWRONR_MASK         (1 << 7)
 134
 135 #define S5M8763_IRQ_WTSREVNT_MASK       (1 << 0)
 136 #define S5M8763_IRQ_SMPLEVNT_MASK       (1 << 1)
 137 #define S5M8763_IRQ_ALARM1_MASK         (1 << 2)
 138 #define S5M8763_IRQ_ALARM0_MASK         (1 << 3)
 139
 140 #define S5M8763_IRQ_ONKEY1S_MASK        (1 << 0)
 141 #define S5M8763_IRQ_TOPOFFR_MASK        (1 << 2)
 142 #define S5M8763_IRQ_DCINOVPR_MASK       (1 << 3)
 143 #define S5M8763_IRQ_CHGRSTF_MASK        (1 << 4)
 144 #define S5M8763_IRQ_DONER_MASK          (1 << 5)
 145 #define S5M8763_IRQ_CHGFAULT_MASK       (1 << 7)
 146
 147 #define S5M8763_IRQ_LOBAT1_MASK         (1 << 0)
 148 #define S5M8763_IRQ_LOBAT2_MASK         (1 << 1)
 149
 150 #define S5M8763_ENRAMP                  (1 << 4)
 151
 152 #endif /*  __LINUX_MFD_SEC_IRQ_H */