include/asm-sh/system.h

   1 #ifndef __ASM_SH_SYSTEM_H
   2 #define __ASM_SH_SYSTEM_H
   3
   4 /*
   5  * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
   6  * Copyright (C) 2002 Paul Mundt
   7  */
   8
   9 #include <asm/types.h>
  10
  11 /*
  12  *      switch_to() should switch tasks to task nr n, first
  13  */
  14
  15 #define switch_to(prev, next, last) do {                                \
  16  struct task_struct *__last;                                            \
  17  register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp;       \
  18  register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc;       \
  19  register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev;  \
  20  register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next;  \
  21  register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp;       \
  22  register unsigned long __ts7 __asm__ ("r7") = next->thread.pc;         \
  23  __asm__ __volatile__ (".balign 4\n\t"                                  \
  24                        "stc.l   gbr, @-r15\n\t"                         \
  25                        "sts.l   pr, @-r15\n\t"                          \
  26                        "mov.l   r8, @-r15\n\t"                          \
  27                        "mov.l   r9, @-r15\n\t"                          \
  28                        "mov.l   r10, @-r15\n\t"                         \
  29                        "mov.l   r11, @-r15\n\t"                         \
  30                        "mov.l   r12, @-r15\n\t"                         \
  31                        "mov.l   r13, @-r15\n\t"                         \
  32                        "mov.l   r14, @-r15\n\t"                         \
  33                        "mov.l   r15, @r1        ! save SP\n\t"          \
  34                        "mov.l   @r6, r15        ! change to new stack\n\t" \
  35                        "mova    1f, %0\n\t"                             \
  36                        "mov.l   %0, @r2         ! save PC\n\t"          \
  37                        "mov.l   2f, %0\n\t"                             \
  38                        "jmp     @%0             ! call __switch_to\n\t" \
  39                        " lds    r7, pr          !  with return to new PC\n\t" \
  40                        ".balign 4\n"                                    \
  41                        "2:\n\t"                                         \
  42                        ".long   __switch_to\n"                          \
  43                        "1:\n\t"                                         \
  44                        "mov.l   @r15+, r14\n\t"                         \
  45                        "mov.l   @r15+, r13\n\t"                         \
  46                        "mov.l   @r15+, r12\n\t"                         \
  47                        "mov.l   @r15+, r11\n\t"                         \
  48                        "mov.l   @r15+, r10\n\t"                         \
  49                        "mov.l   @r15+, r9\n\t"                          \
  50                        "mov.l   @r15+, r8\n\t"                          \
  51                        "lds.l   @r15+, pr\n\t"                          \
  52                        "ldc.l   @r15+, gbr\n\t"                         \
  53                        : "=z" (__last)                                  \
  54                        : "r" (__ts1), "r" (__ts2), "r" (__ts4),         \
  55                          "r" (__ts5), "r" (__ts6), "r" (__ts7)          \
  56                        : "r3", "t");                                    \
  57         last = __last;                                                  \
  58 } while (0)
  59
  60 /*
  61  * On SMP systems, when the scheduler does migration-cost autodetection,
  62  * it needs a way to flush as much of the CPU's caches as possible.
  63  *
  64  * TODO: fill this in!
  65  */
  66 static inline void sched_cacheflush(void)
  67 {
  68 }
  69
  70 #ifdef CONFIG_CPU_SH4A
  71 #define __icbi()                        \
  72 {                                       \
  73         unsigned long __addr;           \
  74         __addr = 0xa8000000;            \
  75         __asm__ __volatile__(           \
  76                 "icbi   %0\n\t"         \
  77                 : /* no output */       \
  78                 : "m" (__m(__addr)));   \
  79 }
  80 #endif
  81
  82 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  83
  84 static __inline__ unsigned long tas(volatile int *m)
  85 { /* #define tas(ptr) (xchg((ptr),1)) */
  86         unsigned long retval;
  87
  88         __asm__ __volatile__ ("tas.b    @%1\n\t"
  89                               "movt     %0"
  90                               : "=r" (retval): "r" (m): "t", "memory");
  91         return retval;
  92 }
  93
  94 extern void __xchg_called_with_bad_pointer(void);
  95
  96 /*
  97  * A brief note on ctrl_barrier(), the control register write barrier.
  98  *
  99  * Legacy SH cores typically require a sequence of 8 nops after
 100  * modification of a control register in order for the changes to take
 101  * effect. On newer cores (like the sh4a and sh5) this is accomplished
 102  * with icbi.
 103  *
 104  * Also note that on sh4a in the icbi case we can forego a synco for the
 105  * write barrier, as it's not necessary for control registers.
 106  *
 107  * Historically we have only done this type of barrier for the MMUCR, but
 108  * it's also necessary for the CCR, so we make it generic here instead.
 109  */
 110 #ifdef CONFIG_CPU_SH4A
 111 #define mb()            __asm__ __volatile__ ("synco": : :"memory")
 112 #define rmb()           mb()
 113 #define wmb()           __asm__ __volatile__ ("synco": : :"memory")
 114 #define ctrl_barrier()  __icbi()
 115 #define read_barrier_depends()  do { } while(0)
 116 #else
 117 #define mb()            __asm__ __volatile__ ("": : :"memory")
 118 #define rmb()           mb()
 119 #define wmb()           __asm__ __volatile__ ("": : :"memory")
 120 #define ctrl_barrier()  __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
 121 #define read_barrier_depends()  do { } while(0)
 122 #endif
 123
 124 #ifdef CONFIG_SMP
 125 #define smp_mb()        mb()
 126 #define smp_rmb()       rmb()
 127 #define smp_wmb()       wmb()
 128 #define smp_read_barrier_depends()      read_barrier_depends()
 129 #else
 130 #define smp_mb()        barrier()
 131 #define smp_rmb()       barrier()
 132 #define smp_wmb()       barrier()
 133 #define smp_read_barrier_depends()      do { } while(0)
 134 #endif
 135
 136 #define set_mb(var, value) do { xchg(&var, value); } while (0)
 137
 138 /* Interrupt Control */
 139 #ifdef CONFIG_CPU_HAS_SR_RB
 140 static inline void local_irq_enable(void)
 141 {
 142         unsigned long __dummy0, __dummy1;
 143
 144         __asm__ __volatile__("stc       sr, %0\n\t"
 145                              "and       %1, %0\n\t"
 146                              "stc       r6_bank, %1\n\t"
 147                              "or        %1, %0\n\t"
 148                              "ldc       %0, sr"
 149                              : "=&r" (__dummy0), "=r" (__dummy1)
 150                              : "1" (~0x000000f0)
 151                              : "memory");
 152 }
 153 #else
 154 static inline void local_irq_enable(void)
 155 {
 156         unsigned long __dummy0, __dummy1;
 157
 158         __asm__ __volatile__ (
 159                 "stc    sr, %0\n\t"
 160                 "and    %1, %0\n\t"
 161                 "ldc    %0, sr\n\t"
 162                 : "=&r" (__dummy0), "=r" (__dummy1)
 163                 : "1" (~0x000000f0)
 164                 : "memory");
 165 }
 166 #endif
 167
 168 static __inline__ void local_irq_disable(void)
 169 {
 170         unsigned long __dummy;
 171         __asm__ __volatile__("stc       sr, %0\n\t"
 172                              "or        #0xf0, %0\n\t"
 173                              "ldc       %0, sr"
 174                              : "=&z" (__dummy)
 175                              : /* no inputs */
 176                              : "memory");
 177 }
 178
 179 #define local_save_flags(x) \
 180         __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" )
 181
 182 #define irqs_disabled()                 \
 183 ({                                      \
 184         unsigned long flags;            \
 185         local_save_flags(flags);        \
 186         (flags != 0);                   \
 187 })
 188
 189 static __inline__ unsigned long local_irq_save(void)
 190 {
 191         unsigned long flags, __dummy;
 192
 193         __asm__ __volatile__("stc       sr, %1\n\t"
 194                              "mov       %1, %0\n\t"
 195                              "or        #0xf0, %0\n\t"
 196                              "ldc       %0, sr\n\t"
 197                              "mov       %1, %0\n\t"
 198                              "and       #0xf0, %0"
 199                              : "=&z" (flags), "=&r" (__dummy)
 200                              :/**/
 201                              : "memory" );
 202         return flags;
 203 }
 204
 205 #ifdef DEBUG_CLI_STI
 206 static __inline__ void  local_irq_restore(unsigned long x)
 207 {
 208         if ((x & 0x000000f0) != 0x000000f0)
 209                 local_irq_enable();
 210         else {
 211                 unsigned long flags;
 212                 local_save_flags(flags);
 213
 214                 if (flags == 0) {
 215                         extern void dump_stack(void);
 216                         printk(KERN_ERR "BUG!\n");
 217                         dump_stack();
 218                         local_irq_disable();
 219                 }
 220         }
 221 }
 222 #else
 223 #define local_irq_restore(x) do {                       \
 224         if ((x & 0x000000f0) != 0x000000f0)             \
 225                 local_irq_enable();                             \
 226 } while (0)
 227 #endif
 228
 229 #define really_restore_flags(x) do {                    \
 230         if ((x & 0x000000f0) != 0x000000f0)             \
 231                 local_irq_enable();                             \
 232         else                                            \
 233                 local_irq_disable();                            \
 234 } while (0)
 235
 236 /*
 237  * Jump to P2 area.
 238  * When handling TLB or caches, we need to do it from P2 area.
 239  */
 240 #define jump_to_P2()                    \
 241 do {                                    \
 242         unsigned long __dummy;          \
 243         __asm__ __volatile__(           \
 244                 "mov.l  1f, %0\n\t"     \
 245                 "or     %1, %0\n\t"     \
 246                 "jmp    @%0\n\t"        \
 247                 " nop\n\t"              \
 248                 ".balign 4\n"           \
 249                 "1:     .long 2f\n"     \
 250                 "2:"                    \
 251                 : "=&r" (__dummy)       \
 252                 : "r" (0x20000000));    \
 253 } while (0)
 254
 255 /*
 256  * Back to P1 area.
 257  */
 258 #define back_to_P1()                                    \
 259 do {                                                    \
 260         unsigned long __dummy;                          \
 261         ctrl_barrier();                                 \
 262         __asm__ __volatile__(                           \
 263                 "mov.l  1f, %0\n\t"                     \
 264                 "jmp    @%0\n\t"                        \
 265                 " nop\n\t"                              \
 266                 ".balign 4\n"                           \
 267                 "1:     .long 2f\n"                     \
 268                 "2:"                                    \
 269                 : "=&r" (__dummy));                     \
 270 } while (0)
 271
 272 /* For spinlocks etc */
 273 #define local_irq_save(x)       x = local_irq_save()
 274
 275 static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val)
 276 {
 277         unsigned long flags, retval;
 278
 279         local_irq_save(flags);
 280         retval = *m;
 281         *m = val;
 282         local_irq_restore(flags);
 283         return retval;
 284 }
 285
 286 static __inline__ unsigned long xchg_u8(volatile unsigned char * m, unsigned long val)
 287 {
 288         unsigned long flags, retval;
 289
 290         local_irq_save(flags);
 291         retval = *m;
 292         *m = val & 0xff;
 293         local_irq_restore(flags);
 294         return retval;
 295 }
 296
 297 static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
 298 {
 299         switch (size) {
 300         case 4:
 301                 return xchg_u32(ptr, x);
 302                 break;
 303         case 1:
 304                 return xchg_u8(ptr, x);
 305                 break;
 306         }
 307         __xchg_called_with_bad_pointer();
 308         return x;
 309 }
 310
 311 static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
 312         unsigned long new)
 313 {
 314         __u32 retval;
 315         unsigned long flags;
 316
 317         local_irq_save(flags);
 318         retval = *m;
 319         if (retval == old)
 320                 *m = new;
 321         local_irq_restore(flags);       /* implies memory barrier  */
 322         return retval;
 323 }
 324
 325 /* This function doesn't exist, so you'll get a linker error
 326  * if something tries to do an invalid cmpxchg(). */
 327 extern void __cmpxchg_called_with_bad_pointer(void);
 328
 329 #define __HAVE_ARCH_CMPXCHG 1
 330
 331 static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
 332                 unsigned long new, int size)
 333 {
 334         switch (size) {
 335         case 4:
 336                 return __cmpxchg_u32(ptr, old, new);
 337         }
 338         __cmpxchg_called_with_bad_pointer();
 339         return old;
 340 }
 341
 342 #define cmpxchg(ptr,o,n)                                                 \
 343   ({                                                                     \
 344      __typeof__(*(ptr)) _o_ = (o);                                       \
 345      __typeof__(*(ptr)) _n_ = (n);                                       \
 346      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 347                                     (unsigned long)_n_, sizeof(*(ptr))); \
 348   })
 349
 350 /* XXX
 351  * disable hlt during certain critical i/o operations
 352  */
 353 #define HAVE_DISABLE_HLT
 354 void disable_hlt(void);
 355 void enable_hlt(void);
 356
 357 #define arch_align_stack(x) (x)
 358
 359 #endif