2 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QUICC Engine (QE) external definitions and structure.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #ifndef _ASM_POWERPC_QE_H
16 #define _ASM_POWERPC_QE_H
19 #include <linux/spinlock.h>
21 #include <asm/immap_qe.h>
23 #define QE_NUM_OF_SNUM 28
24 #define QE_NUM_OF_BRGS 16
25 #define QE_NUM_OF_PORTS 1024
29 #define MEM_PART_SYSTEM 0
30 #define MEM_PART_SECONDARY 1
31 #define MEM_PART_MURAM 2
36 QE_BRG1, /* Baud Rate Generator 1 */
37 QE_BRG2, /* Baud Rate Generator 2 */
38 QE_BRG3, /* Baud Rate Generator 3 */
39 QE_BRG4, /* Baud Rate Generator 4 */
40 QE_BRG5, /* Baud Rate Generator 5 */
41 QE_BRG6, /* Baud Rate Generator 6 */
42 QE_BRG7, /* Baud Rate Generator 7 */
43 QE_BRG8, /* Baud Rate Generator 8 */
44 QE_BRG9, /* Baud Rate Generator 9 */
45 QE_BRG10, /* Baud Rate Generator 10 */
46 QE_BRG11, /* Baud Rate Generator 11 */
47 QE_BRG12, /* Baud Rate Generator 12 */
48 QE_BRG13, /* Baud Rate Generator 13 */
49 QE_BRG14, /* Baud Rate Generator 14 */
50 QE_BRG15, /* Baud Rate Generator 15 */
51 QE_BRG16, /* Baud Rate Generator 16 */
52 QE_CLK1, /* Clock 1 */
53 QE_CLK2, /* Clock 2 */
54 QE_CLK3, /* Clock 3 */
55 QE_CLK4, /* Clock 4 */
56 QE_CLK5, /* Clock 5 */
57 QE_CLK6, /* Clock 6 */
58 QE_CLK7, /* Clock 7 */
59 QE_CLK8, /* Clock 8 */
60 QE_CLK9, /* Clock 9 */
61 QE_CLK10, /* Clock 10 */
62 QE_CLK11, /* Clock 11 */
63 QE_CLK12, /* Clock 12 */
64 QE_CLK13, /* Clock 13 */
65 QE_CLK14, /* Clock 14 */
66 QE_CLK15, /* Clock 15 */
67 QE_CLK16, /* Clock 16 */
68 QE_CLK17, /* Clock 17 */
69 QE_CLK18, /* Clock 18 */
70 QE_CLK19, /* Clock 19 */
71 QE_CLK20, /* Clock 20 */
72 QE_CLK21, /* Clock 21 */
73 QE_CLK22, /* Clock 22 */
74 QE_CLK23, /* Clock 23 */
75 QE_CLK24, /* Clock 24 */
79 static inline bool qe_clock_is_brg(enum qe_clock clk)
81 return clk >= QE_BRG1 && clk <= QE_BRG16;
84 extern spinlock_t cmxgcr_lock;
86 /* Export QE common operations */
87 extern void __init qe_reset(void);
90 #define QE_PIO_PINS 32
93 __be32 cpodr; /* Open drain register */
94 __be32 cpdata; /* Data register */
95 __be32 cpdir1; /* Direction register */
96 __be32 cpdir2; /* Direction register */
97 __be32 cppar1; /* Pin assignment register */
98 __be32 cppar2; /* Pin assignment register */
99 #ifdef CONFIG_PPC_85xx
104 extern void __init qe_add_gpiochips(void);
105 extern int par_io_init(struct device_node *np);
106 extern int par_io_of_config(struct device_node *np);
107 #define QE_PIO_DIR_IN 2
108 #define QE_PIO_DIR_OUT 1
109 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
110 int dir, int open_drain, int assignment,
112 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
113 int assignment, int has_irq);
114 extern int par_io_data_set(u8 port, u8 pin, u8 val);
116 /* QE internal API */
117 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
118 enum qe_clock qe_clock_source(const char *source);
119 unsigned int qe_get_brg_clk(void);
120 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
121 int qe_get_snum(void);
122 void qe_put_snum(u8 snum);
123 /* we actually use cpm_muram implementation, define this for convenience */
124 #define qe_muram_init cpm_muram_init
125 #define qe_muram_alloc cpm_muram_alloc
126 #define qe_muram_alloc_fixed cpm_muram_alloc_fixed
127 #define qe_muram_free cpm_muram_free
128 #define qe_muram_addr cpm_muram_addr
129 #define qe_muram_offset cpm_muram_offset
131 /* Structure that defines QE firmware binary files.
133 * See Documentation/powerpc/qe-firmware.txt for a description of these
138 __be32 length; /* Length of the entire structure, in bytes */
139 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
140 u8 version; /* Version of this layout. First ver is '1' */
142 u8 id[62]; /* Null-terminated identifier string */
143 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
144 u8 count; /* Number of microcode[] structures */
146 __be16 model; /* The SOC model */
147 u8 major; /* The SOC revision major */
148 u8 minor; /* The SOC revision minor */
149 } __attribute__ ((packed)) soc;
150 u8 padding[4]; /* Reserved, for alignment */
151 __be64 extended_modes; /* Extended modes */
152 __be32 vtraps[8]; /* Virtual trap addresses */
153 u8 reserved[4]; /* Reserved, for future expansion */
154 struct qe_microcode {
155 u8 id[32]; /* Null-terminated identifier */
156 __be32 traps[16]; /* Trap addresses, 0 == ignore */
157 __be32 eccr; /* The value for the ECCR register */
158 __be32 iram_offset; /* Offset into I-RAM for the code */
159 __be32 count; /* Number of 32-bit words of the code */
160 __be32 code_offset; /* Offset of the actual microcode */
161 u8 major; /* The microcode version major */
162 u8 minor; /* The microcode version minor */
163 u8 revision; /* The microcode version revision */
164 u8 padding; /* Reserved, for alignment */
165 u8 reserved[4]; /* Reserved, for future expansion */
166 } __attribute__ ((packed)) microcode[1];
167 /* All microcode binaries should be located here */
168 /* CRC32 should be located here, after the microcode binaries */
169 } __attribute__ ((packed));
171 struct qe_firmware_info {
172 char id[64]; /* Firmware name */
173 u32 vtraps[8]; /* Virtual trap addresses */
174 u64 extended_modes; /* Extended modes */
177 /* Upload a firmware to the QE */
178 int qe_upload_firmware(const struct qe_firmware *firmware);
180 /* Obtain information on the uploaded firmware */
181 struct qe_firmware_info *qe_get_firmware_info(void);
184 int qe_usb_clock_set(enum qe_clock clk, int rate);
186 /* Buffer descriptors */
191 } __attribute__ ((packed));
193 #define BD_STATUS_MASK 0xffff0000
194 #define BD_LENGTH_MASK 0x0000ffff
197 #define QE_INTR_TABLE_ALIGN 16 /* ??? */
198 #define QE_ALIGNMENT_OF_BD 8
199 #define QE_ALIGNMENT_OF_PRAM 64
201 /* RISC allocation */
202 enum qe_risc_allocation {
203 QE_RISC_ALLOCATION_RISC1 = 1, /* RISC 1 */
204 QE_RISC_ALLOCATION_RISC2 = 2, /* RISC 2 */
205 QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3 /* Dynamically choose
209 /* QE extended filtering Table Lookup Key Size */
210 enum qe_fltr_tbl_lookup_key_size {
211 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
212 = 0x3f, /* LookupKey parsed by the Generate LookupKey
213 CMD is truncated to 8 bytes */
214 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
215 = 0x5f, /* LookupKey parsed by the Generate LookupKey
216 CMD is truncated to 16 bytes */
219 /* QE FLTR extended filtering Largest External Table Lookup Key Size */
220 enum qe_fltr_largest_external_tbl_lookup_key_size {
221 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
223 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
224 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
225 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
226 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
229 /* structure representing QE parameter RAM */
230 struct qe_timer_tables {
231 u16 tm_base; /* QE timer table base adr */
232 u16 tm_ptr; /* QE timer table pointer */
233 u16 r_tmr; /* QE timer mode register */
234 u16 r_tmv; /* QE timer valid register */
235 u32 tm_cmd; /* QE timer cmd register */
236 u32 tm_cnt; /* QE timer internal cnt */
237 } __attribute__ ((packed));
239 #define QE_FLTR_TAD_SIZE 8
241 /* QE extended filtering Termination Action Descriptor (TAD) */
243 u8 serialized[QE_FLTR_TAD_SIZE];
244 } __attribute__ ((packed));
246 /* Communication Direction */
251 COMM_DIR_RX_AND_TX = 3
254 /* QE CMXUCR Registers.
255 * There are two UCCs represented in each of the four CMXUCR registers.
256 * These values are for the UCC in the LSBs
258 #define QE_CMXUCR_MII_ENET_MNG 0x00007000
259 #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
260 #define QE_CMXUCR_GRANT 0x00008000
261 #define QE_CMXUCR_TSA 0x00004000
262 #define QE_CMXUCR_BKPT 0x00000100
263 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
265 /* QE CMXGCR Registers.
267 #define QE_CMXGCR_MII_ENET_MNG 0x00007000
268 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
269 #define QE_CMXGCR_USBCS 0x0000000f
270 #define QE_CMXGCR_USBCS_CLK3 0x1
271 #define QE_CMXGCR_USBCS_CLK5 0x2
272 #define QE_CMXGCR_USBCS_CLK7 0x3
273 #define QE_CMXGCR_USBCS_CLK9 0x4
274 #define QE_CMXGCR_USBCS_CLK13 0x5
275 #define QE_CMXGCR_USBCS_CLK17 0x6
276 #define QE_CMXGCR_USBCS_CLK19 0x7
277 #define QE_CMXGCR_USBCS_CLK21 0x8
278 #define QE_CMXGCR_USBCS_BRG9 0x9
279 #define QE_CMXGCR_USBCS_BRG10 0xa
283 #define QE_CR_FLG 0x00010000
284 #define QE_RESET 0x80000000
285 #define QE_INIT_TX_RX 0x00000000
286 #define QE_INIT_RX 0x00000001
287 #define QE_INIT_TX 0x00000002
288 #define QE_ENTER_HUNT_MODE 0x00000003
289 #define QE_STOP_TX 0x00000004
290 #define QE_GRACEFUL_STOP_TX 0x00000005
291 #define QE_RESTART_TX 0x00000006
292 #define QE_CLOSE_RX_BD 0x00000007
293 #define QE_SWITCH_COMMAND 0x00000007
294 #define QE_SET_GROUP_ADDRESS 0x00000008
295 #define QE_START_IDMA 0x00000009
296 #define QE_MCC_STOP_RX 0x00000009
297 #define QE_ATM_TRANSMIT 0x0000000a
298 #define QE_HPAC_CLEAR_ALL 0x0000000b
299 #define QE_GRACEFUL_STOP_RX 0x0000001a
300 #define QE_RESTART_RX 0x0000001b
301 #define QE_HPAC_SET_PRIORITY 0x0000010b
302 #define QE_HPAC_STOP_TX 0x0000020b
303 #define QE_HPAC_STOP_RX 0x0000030b
304 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
305 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
306 #define QE_HPAC_START_TX 0x0000060b
307 #define QE_HPAC_START_RX 0x0000070b
308 #define QE_USB_STOP_TX 0x0000000a
309 #define QE_USB_RESTART_TX 0x0000000c
310 #define QE_QMC_STOP_TX 0x0000000c
311 #define QE_QMC_STOP_RX 0x0000000d
312 #define QE_SS7_SU_FIL_RESET 0x0000000e
313 /* jonathbr added from here down for 83xx */
314 #define QE_RESET_BCS 0x0000000a
315 #define QE_MCC_INIT_TX_RX_16 0x00000003
316 #define QE_MCC_STOP_TX 0x00000004
317 #define QE_MCC_INIT_TX_1 0x00000005
318 #define QE_MCC_INIT_RX_1 0x00000006
319 #define QE_MCC_RESET 0x00000007
320 #define QE_SET_TIMER 0x00000008
321 #define QE_RANDOM_NUMBER 0x0000000c
322 #define QE_ATM_MULTI_THREAD_INIT 0x00000011
323 #define QE_ASSIGN_PAGE 0x00000012
324 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
325 #define QE_START_FLOW_CONTROL 0x00000014
326 #define QE_STOP_FLOW_CONTROL 0x00000015
327 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
329 #define QE_ASSIGN_RISC 0x00000010
330 #define QE_CR_MCN_NORMAL_SHIFT 6
331 #define QE_CR_MCN_USB_SHIFT 4
332 #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
333 #define QE_CR_SNUM_SHIFT 17
335 /* QE CECR Sub Block - sub block of QE command.
337 #define QE_CR_SUBBLOCK_INVALID 0x00000000
338 #define QE_CR_SUBBLOCK_USB 0x03200000
339 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
340 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
341 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
342 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
343 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
344 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
345 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
346 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
347 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
348 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
349 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
350 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
351 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
352 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
353 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
354 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
355 #define QE_CR_SUBBLOCK_MCC1 0x03800000
356 #define QE_CR_SUBBLOCK_MCC2 0x03a00000
357 #define QE_CR_SUBBLOCK_MCC3 0x03000000
358 #define QE_CR_SUBBLOCK_IDMA1 0x02800000
359 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000
360 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000
361 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000
362 #define QE_CR_SUBBLOCK_HPAC 0x01e00000
363 #define QE_CR_SUBBLOCK_SPI1 0x01400000
364 #define QE_CR_SUBBLOCK_SPI2 0x01600000
365 #define QE_CR_SUBBLOCK_RAND 0x01c00000
366 #define QE_CR_SUBBLOCK_TIMER 0x01e00000
367 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000
369 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
370 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
371 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
372 #define QE_CR_PROTOCOL_QMC 0x02
373 #define QE_CR_PROTOCOL_UART 0x04
374 #define QE_CR_PROTOCOL_ATM_POS 0x0A
375 #define QE_CR_PROTOCOL_ETHERNET 0x0C
376 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D
378 /* BRG configuration register */
379 #define QE_BRGC_ENABLE 0x00010000
380 #define QE_BRGC_DIVISOR_SHIFT 1
381 #define QE_BRGC_DIVISOR_MAX 0xFFF
382 #define QE_BRGC_DIV16 1
384 /* QE Timers registers */
385 #define QE_GTCFR1_PCAS 0x80
386 #define QE_GTCFR1_STP2 0x20
387 #define QE_GTCFR1_RST2 0x10
388 #define QE_GTCFR1_GM2 0x08
389 #define QE_GTCFR1_GM1 0x04
390 #define QE_GTCFR1_STP1 0x02
391 #define QE_GTCFR1_RST1 0x01
394 #define QE_SDSR_BER1 0x02000000
395 #define QE_SDSR_BER2 0x01000000
397 #define QE_SDMR_GLB_1_MSK 0x80000000
398 #define QE_SDMR_ADR_SEL 0x20000000
399 #define QE_SDMR_BER1_MSK 0x02000000
400 #define QE_SDMR_BER2_MSK 0x01000000
401 #define QE_SDMR_EB1_MSK 0x00800000
402 #define QE_SDMR_ER1_MSK 0x00080000
403 #define QE_SDMR_ER2_MSK 0x00040000
404 #define QE_SDMR_CEN_MASK 0x0000E000
405 #define QE_SDMR_SBER_1 0x00000200
406 #define QE_SDMR_SBER_2 0x00000200
407 #define QE_SDMR_EB1_PR_MASK 0x000000C0
408 #define QE_SDMR_ER1_PR 0x00000008
410 #define QE_SDMR_CEN_SHIFT 13
411 #define QE_SDMR_EB1_PR_SHIFT 6
413 #define QE_SDTM_MSNUM_SHIFT 24
415 #define QE_SDEBCR_BA_MASK 0x01FFFFFF
417 /* Communication Processor */
418 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
419 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
420 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
423 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
424 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
427 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
428 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
429 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
430 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
431 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
433 /* UCC GUEMR register */
434 #define UCC_GUEMR_MODE_MASK_RX 0x02
435 #define UCC_GUEMR_MODE_FAST_RX 0x02
436 #define UCC_GUEMR_MODE_SLOW_RX 0x00
437 #define UCC_GUEMR_MODE_MASK_TX 0x01
438 #define UCC_GUEMR_MODE_FAST_TX 0x01
439 #define UCC_GUEMR_MODE_SLOW_TX 0x00
440 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
441 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
444 /* structure representing UCC SLOW parameter RAM */
445 struct ucc_slow_pram {
446 __be16 rbase; /* RX BD base address */
447 __be16 tbase; /* TX BD base address */
448 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
449 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
450 __be16 mrblr; /* Rx buffer length */
451 __be32 rstate; /* Rx internal state */
452 __be32 rptr; /* Rx internal data pointer */
453 __be16 rbptr; /* rb BD Pointer */
454 __be16 rcount; /* Rx internal byte count */
455 __be32 rtemp; /* Rx temp */
456 __be32 tstate; /* Tx internal state */
457 __be32 tptr; /* Tx internal data pointer */
458 __be16 tbptr; /* Tx BD pointer */
459 __be16 tcount; /* Tx byte count */
460 __be32 ttemp; /* Tx temp */
461 __be32 rcrc; /* temp receive CRC */
462 __be32 tcrc; /* temp transmit CRC */
463 } __attribute__ ((packed));
465 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */
466 #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
467 #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
468 #define UCC_SLOW_GUMR_H_REVD 0x00002000
469 #define UCC_SLOW_GUMR_H_TRX 0x00001000
470 #define UCC_SLOW_GUMR_H_TTX 0x00000800
471 #define UCC_SLOW_GUMR_H_CDP 0x00000400
472 #define UCC_SLOW_GUMR_H_CTSP 0x00000200
473 #define UCC_SLOW_GUMR_H_CDS 0x00000100
474 #define UCC_SLOW_GUMR_H_CTSS 0x00000080
475 #define UCC_SLOW_GUMR_H_TFL 0x00000040
476 #define UCC_SLOW_GUMR_H_RFW 0x00000020
477 #define UCC_SLOW_GUMR_H_TXSY 0x00000010
478 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004
479 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008
480 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
481 #define UCC_SLOW_GUMR_H_RTSM 0x00000002
482 #define UCC_SLOW_GUMR_H_RSYN 0x00000001
484 #define UCC_SLOW_GUMR_L_TCI 0x10000000
485 #define UCC_SLOW_GUMR_L_RINV 0x02000000
486 #define UCC_SLOW_GUMR_L_TINV 0x01000000
487 #define UCC_SLOW_GUMR_L_TEND 0x00040000
488 #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
489 #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
490 #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
491 #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
492 #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
493 #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
494 #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
495 #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
496 #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
497 #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
498 #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
499 #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
500 #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
501 #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
502 #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
503 #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
504 #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
505 #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
506 #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
507 #define UCC_SLOW_GUMR_L_ENR 0x00000020
508 #define UCC_SLOW_GUMR_L_ENT 0x00000010
509 #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
510 #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
511 #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
512 #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
513 #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
515 /* General UCC FAST Mode Register */
516 #define UCC_FAST_GUMR_TCI 0x20000000
517 #define UCC_FAST_GUMR_TRX 0x10000000
518 #define UCC_FAST_GUMR_TTX 0x08000000
519 #define UCC_FAST_GUMR_CDP 0x04000000
520 #define UCC_FAST_GUMR_CTSP 0x02000000
521 #define UCC_FAST_GUMR_CDS 0x01000000
522 #define UCC_FAST_GUMR_CTSS 0x00800000
523 #define UCC_FAST_GUMR_TXSY 0x00020000
524 #define UCC_FAST_GUMR_RSYN 0x00010000
525 #define UCC_FAST_GUMR_RTSM 0x00002000
526 #define UCC_FAST_GUMR_REVD 0x00000400
527 #define UCC_FAST_GUMR_ENR 0x00000020
528 #define UCC_FAST_GUMR_ENT 0x00000010
530 /* UART Slow UCC Event Register (UCCE) */
531 #define UCC_UART_UCCE_AB 0x0200
532 #define UCC_UART_UCCE_IDLE 0x0100
533 #define UCC_UART_UCCE_GRA 0x0080
534 #define UCC_UART_UCCE_BRKE 0x0040
535 #define UCC_UART_UCCE_BRKS 0x0020
536 #define UCC_UART_UCCE_CCR 0x0008
537 #define UCC_UART_UCCE_BSY 0x0004
538 #define UCC_UART_UCCE_TX 0x0002
539 #define UCC_UART_UCCE_RX 0x0001
541 /* HDLC Slow UCC Event Register (UCCE) */
542 #define UCC_HDLC_UCCE_GLR 0x1000
543 #define UCC_HDLC_UCCE_GLT 0x0800
544 #define UCC_HDLC_UCCE_IDLE 0x0100
545 #define UCC_HDLC_UCCE_BRKE 0x0040
546 #define UCC_HDLC_UCCE_BRKS 0x0020
547 #define UCC_HDLC_UCCE_TXE 0x0010
548 #define UCC_HDLC_UCCE_RXF 0x0008
549 #define UCC_HDLC_UCCE_BSY 0x0004
550 #define UCC_HDLC_UCCE_TXB 0x0002
551 #define UCC_HDLC_UCCE_RXB 0x0001
553 /* BISYNC Slow UCC Event Register (UCCE) */
554 #define UCC_BISYNC_UCCE_GRA 0x0080
555 #define UCC_BISYNC_UCCE_TXE 0x0010
556 #define UCC_BISYNC_UCCE_RCH 0x0008
557 #define UCC_BISYNC_UCCE_BSY 0x0004
558 #define UCC_BISYNC_UCCE_TXB 0x0002
559 #define UCC_BISYNC_UCCE_RXB 0x0001
561 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */
562 #define UCC_GETH_UCCE_MPD 0x80000000
563 #define UCC_GETH_UCCE_SCAR 0x40000000
564 #define UCC_GETH_UCCE_GRA 0x20000000
565 #define UCC_GETH_UCCE_CBPR 0x10000000
566 #define UCC_GETH_UCCE_BSY 0x08000000
567 #define UCC_GETH_UCCE_RXC 0x04000000
568 #define UCC_GETH_UCCE_TXC 0x02000000
569 #define UCC_GETH_UCCE_TXE 0x01000000
570 #define UCC_GETH_UCCE_TXB7 0x00800000
571 #define UCC_GETH_UCCE_TXB6 0x00400000
572 #define UCC_GETH_UCCE_TXB5 0x00200000
573 #define UCC_GETH_UCCE_TXB4 0x00100000
574 #define UCC_GETH_UCCE_TXB3 0x00080000
575 #define UCC_GETH_UCCE_TXB2 0x00040000
576 #define UCC_GETH_UCCE_TXB1 0x00020000
577 #define UCC_GETH_UCCE_TXB0 0x00010000
578 #define UCC_GETH_UCCE_RXB7 0x00008000
579 #define UCC_GETH_UCCE_RXB6 0x00004000
580 #define UCC_GETH_UCCE_RXB5 0x00002000
581 #define UCC_GETH_UCCE_RXB4 0x00001000
582 #define UCC_GETH_UCCE_RXB3 0x00000800
583 #define UCC_GETH_UCCE_RXB2 0x00000400
584 #define UCC_GETH_UCCE_RXB1 0x00000200
585 #define UCC_GETH_UCCE_RXB0 0x00000100
586 #define UCC_GETH_UCCE_RXF7 0x00000080
587 #define UCC_GETH_UCCE_RXF6 0x00000040
588 #define UCC_GETH_UCCE_RXF5 0x00000020
589 #define UCC_GETH_UCCE_RXF4 0x00000010
590 #define UCC_GETH_UCCE_RXF3 0x00000008
591 #define UCC_GETH_UCCE_RXF2 0x00000004
592 #define UCC_GETH_UCCE_RXF1 0x00000002
593 #define UCC_GETH_UCCE_RXF0 0x00000001
595 /* UPSMR, when used as a UART */
596 #define UCC_UART_UPSMR_FLC 0x8000
597 #define UCC_UART_UPSMR_SL 0x4000
598 #define UCC_UART_UPSMR_CL_MASK 0x3000
599 #define UCC_UART_UPSMR_CL_8 0x3000
600 #define UCC_UART_UPSMR_CL_7 0x2000
601 #define UCC_UART_UPSMR_CL_6 0x1000
602 #define UCC_UART_UPSMR_CL_5 0x0000
603 #define UCC_UART_UPSMR_UM_MASK 0x0c00
604 #define UCC_UART_UPSMR_UM_NORMAL 0x0000
605 #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
606 #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
607 #define UCC_UART_UPSMR_FRZ 0x0200
608 #define UCC_UART_UPSMR_RZS 0x0100
609 #define UCC_UART_UPSMR_SYN 0x0080
610 #define UCC_UART_UPSMR_DRT 0x0040
611 #define UCC_UART_UPSMR_PEN 0x0010
612 #define UCC_UART_UPSMR_RPM_MASK 0x000c
613 #define UCC_UART_UPSMR_RPM_ODD 0x0000
614 #define UCC_UART_UPSMR_RPM_LOW 0x0004
615 #define UCC_UART_UPSMR_RPM_EVEN 0x0008
616 #define UCC_UART_UPSMR_RPM_HIGH 0x000C
617 #define UCC_UART_UPSMR_TPM_MASK 0x0003
618 #define UCC_UART_UPSMR_TPM_ODD 0x0000
619 #define UCC_UART_UPSMR_TPM_LOW 0x0001
620 #define UCC_UART_UPSMR_TPM_EVEN 0x0002
621 #define UCC_UART_UPSMR_TPM_HIGH 0x0003
623 /* UCC Transmit On Demand Register (UTODR) */
624 #define UCC_SLOW_TOD 0x8000
625 #define UCC_FAST_TOD 0x8000
627 /* UCC Bus Mode Register masks */
628 /* Not to be confused with the Bundle Mode Register */
629 #define UCC_BMR_GBL 0x20
630 #define UCC_BMR_BO_BE 0x10
631 #define UCC_BMR_CETM 0x04
632 #define UCC_BMR_DTB 0x02
633 #define UCC_BMR_BDB 0x01
635 /* Function code masks */
637 #define FC_DTB_LCL 0x02
638 #define UCC_FAST_FUNCTION_CODE_GBL 0x20
639 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
640 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
642 #endif /* __KERNEL__ */
643 #endif /* _ASM_POWERPC_QE_H */