drivers/video/sh_mobile_hdmi.c

   1 /*
   2  * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
   3  * for SLISHDMI13T and SLIPHDMIT IP cores
   4  *
   5  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/console.h>
  14 #include <linux/delay.h>
  15 #include <linux/err.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/slab.h>
  23 #include <linux/types.h>
  24 #include <linux/workqueue.h>
  25 #include <sound/soc-dapm.h>
  26 #include <sound/initval.h>
  27
  28 #include <video/sh_mobile_hdmi.h>
  29 #include <video/sh_mobile_lcdc.h>
  30
  31 #include "sh_mobile_lcdcfb.h"
  32
  33 #define HDMI_SYSTEM_CTRL                        0x00 /* System control */
  34 #define HDMI_L_R_DATA_SWAP_CTRL_RPKT            0x01 /* L/R data swap control,
  35                                                         bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
  36 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8       0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
  37 #define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0        0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
  38 #define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS          0x04 /* SPDIF audio sampling frequency,
  39                                                         bits 19..16 of Internal CTS */
  40 #define HDMI_INTERNAL_CTS_15_8                  0x05 /* bits 15..8 of Internal CTS */
  41 #define HDMI_INTERNAL_CTS_7_0                   0x06 /* bits 7..0 of Internal CTS */
  42 #define HDMI_EXTERNAL_CTS_19_16                 0x07 /* External CTS */
  43 #define HDMI_EXTERNAL_CTS_15_8                  0x08 /* External CTS */
  44 #define HDMI_EXTERNAL_CTS_7_0                   0x09 /* External CTS */
  45 #define HDMI_AUDIO_SETTING_1                    0x0A /* Audio setting.1 */
  46 #define HDMI_AUDIO_SETTING_2                    0x0B /* Audio setting.2 */
  47 #define HDMI_I2S_AUDIO_SET                      0x0C /* I2S audio setting */
  48 #define HDMI_DSD_AUDIO_SET                      0x0D /* DSD audio setting */
  49 #define HDMI_DEBUG_MONITOR_1                    0x0E /* Debug monitor.1 */
  50 #define HDMI_DEBUG_MONITOR_2                    0x0F /* Debug monitor.2 */
  51 #define HDMI_I2S_INPUT_PIN_SWAP                 0x10 /* I2S input pin swap */
  52 #define HDMI_AUDIO_STATUS_BITS_SETTING_1        0x11 /* Audio status bits setting.1 */
  53 #define HDMI_AUDIO_STATUS_BITS_SETTING_2        0x12 /* Audio status bits setting.2 */
  54 #define HDMI_CATEGORY_CODE                      0x13 /* Category code */
  55 #define HDMI_SOURCE_NUM_AUDIO_WORD_LEN          0x14 /* Source number/Audio word length */
  56 #define HDMI_AUDIO_VIDEO_SETTING_1              0x15 /* Audio/Video setting.1 */
  57 #define HDMI_VIDEO_SETTING_1                    0x16 /* Video setting.1 */
  58 #define HDMI_DEEP_COLOR_MODES                   0x17 /* Deep Color Modes */
  59
  60 /* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
  61 #define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS  0x18
  62
  63 #define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS      0x30 /* External video parameter settings */
  64 #define HDMI_EXTERNAL_H_TOTAL_7_0               0x31 /* External horizontal total (LSB) */
  65 #define HDMI_EXTERNAL_H_TOTAL_11_8              0x32 /* External horizontal total (MSB) */
  66 #define HDMI_EXTERNAL_H_BLANK_7_0               0x33 /* External horizontal blank (LSB) */
  67 #define HDMI_EXTERNAL_H_BLANK_9_8               0x34 /* External horizontal blank (MSB) */
  68 #define HDMI_EXTERNAL_H_DELAY_7_0               0x35 /* External horizontal delay (LSB) */
  69 #define HDMI_EXTERNAL_H_DELAY_9_8               0x36 /* External horizontal delay (MSB) */
  70 #define HDMI_EXTERNAL_H_DURATION_7_0            0x37 /* External horizontal duration (LSB) */
  71 #define HDMI_EXTERNAL_H_DURATION_9_8            0x38 /* External horizontal duration (MSB) */
  72 #define HDMI_EXTERNAL_V_TOTAL_7_0               0x39 /* External vertical total (LSB) */
  73 #define HDMI_EXTERNAL_V_TOTAL_9_8               0x3A /* External vertical total (MSB) */
  74 #define HDMI_AUDIO_VIDEO_SETTING_2              0x3B /* Audio/Video setting.2 */
  75 #define HDMI_EXTERNAL_V_BLANK                   0x3D /* External vertical blank */
  76 #define HDMI_EXTERNAL_V_DELAY                   0x3E /* External vertical delay */
  77 #define HDMI_EXTERNAL_V_DURATION                0x3F /* External vertical duration */
  78 #define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL       0x40 /* Control packet manual send control */
  79 #define HDMI_CTRL_PKT_AUTO_SEND                 0x41 /* Control packet auto send with VSYNC control */
  80 #define HDMI_AUTO_CHECKSUM_OPTION               0x42 /* Auto checksum option */
  81 #define HDMI_VIDEO_SETTING_2                    0x45 /* Video setting.2 */
  82 #define HDMI_OUTPUT_OPTION                      0x46 /* Output option */
  83 #define HDMI_SLIPHDMIT_PARAM_OPTION             0x51 /* SLIPHDMIT parameter option */
  84 #define HDMI_HSYNC_PMENT_AT_EMB_7_0             0x52 /* HSYNC placement at embedded sync (LSB) */
  85 #define HDMI_HSYNC_PMENT_AT_EMB_15_8            0x53 /* HSYNC placement at embedded sync (MSB) */
  86 #define HDMI_VSYNC_PMENT_AT_EMB_7_0             0x54 /* VSYNC placement at embedded sync (LSB) */
  87 #define HDMI_VSYNC_PMENT_AT_EMB_14_8            0x55 /* VSYNC placement at embedded sync (MSB) */
  88 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_1         0x56 /* SLIPHDMIT parameter settings.1 */
  89 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_2         0x57 /* SLIPHDMIT parameter settings.2 */
  90 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_3         0x58 /* SLIPHDMIT parameter settings.3 */
  91 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_5         0x59 /* SLIPHDMIT parameter settings.5 */
  92 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_6         0x5A /* SLIPHDMIT parameter settings.6 */
  93 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_7         0x5B /* SLIPHDMIT parameter settings.7 */
  94 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_8         0x5C /* SLIPHDMIT parameter settings.8 */
  95 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_9         0x5D /* SLIPHDMIT parameter settings.9 */
  96 #define HDMI_SLIPHDMIT_PARAM_SETTINGS_10        0x5E /* SLIPHDMIT parameter settings.10 */
  97 #define HDMI_CTRL_PKT_BUF_INDEX                 0x5F /* Control packet buffer index */
  98 #define HDMI_CTRL_PKT_BUF_ACCESS_HB0            0x60 /* Control packet data buffer access window - HB0 */
  99 #define HDMI_CTRL_PKT_BUF_ACCESS_HB1            0x61 /* Control packet data buffer access window - HB1 */
 100 #define HDMI_CTRL_PKT_BUF_ACCESS_HB2            0x62 /* Control packet data buffer access window - HB2 */
 101 #define HDMI_CTRL_PKT_BUF_ACCESS_PB0            0x63 /* Control packet data buffer access window - PB0 */
 102 #define HDMI_CTRL_PKT_BUF_ACCESS_PB1            0x64 /* Control packet data buffer access window - PB1 */
 103 #define HDMI_CTRL_PKT_BUF_ACCESS_PB2            0x65 /* Control packet data buffer access window - PB2 */
 104 #define HDMI_CTRL_PKT_BUF_ACCESS_PB3            0x66 /* Control packet data buffer access window - PB3 */
 105 #define HDMI_CTRL_PKT_BUF_ACCESS_PB4            0x67 /* Control packet data buffer access window - PB4 */
 106 #define HDMI_CTRL_PKT_BUF_ACCESS_PB5            0x68 /* Control packet data buffer access window - PB5 */
 107 #define HDMI_CTRL_PKT_BUF_ACCESS_PB6            0x69 /* Control packet data buffer access window - PB6 */
 108 #define HDMI_CTRL_PKT_BUF_ACCESS_PB7            0x6A /* Control packet data buffer access window - PB7 */
 109 #define HDMI_CTRL_PKT_BUF_ACCESS_PB8            0x6B /* Control packet data buffer access window - PB8 */
 110 #define HDMI_CTRL_PKT_BUF_ACCESS_PB9            0x6C /* Control packet data buffer access window - PB9 */
 111 #define HDMI_CTRL_PKT_BUF_ACCESS_PB10           0x6D /* Control packet data buffer access window - PB10 */
 112 #define HDMI_CTRL_PKT_BUF_ACCESS_PB11           0x6E /* Control packet data buffer access window - PB11 */
 113 #define HDMI_CTRL_PKT_BUF_ACCESS_PB12           0x6F /* Control packet data buffer access window - PB12 */
 114 #define HDMI_CTRL_PKT_BUF_ACCESS_PB13           0x70 /* Control packet data buffer access window - PB13 */
 115 #define HDMI_CTRL_PKT_BUF_ACCESS_PB14           0x71 /* Control packet data buffer access window - PB14 */
 116 #define HDMI_CTRL_PKT_BUF_ACCESS_PB15           0x72 /* Control packet data buffer access window - PB15 */
 117 #define HDMI_CTRL_PKT_BUF_ACCESS_PB16           0x73 /* Control packet data buffer access window - PB16 */
 118 #define HDMI_CTRL_PKT_BUF_ACCESS_PB17           0x74 /* Control packet data buffer access window - PB17 */
 119 #define HDMI_CTRL_PKT_BUF_ACCESS_PB18           0x75 /* Control packet data buffer access window - PB18 */
 120 #define HDMI_CTRL_PKT_BUF_ACCESS_PB19           0x76 /* Control packet data buffer access window - PB19 */
 121 #define HDMI_CTRL_PKT_BUF_ACCESS_PB20           0x77 /* Control packet data buffer access window - PB20 */
 122 #define HDMI_CTRL_PKT_BUF_ACCESS_PB21           0x78 /* Control packet data buffer access window - PB21 */
 123 #define HDMI_CTRL_PKT_BUF_ACCESS_PB22           0x79 /* Control packet data buffer access window - PB22 */
 124 #define HDMI_CTRL_PKT_BUF_ACCESS_PB23           0x7A /* Control packet data buffer access window - PB23 */
 125 #define HDMI_CTRL_PKT_BUF_ACCESS_PB24           0x7B /* Control packet data buffer access window - PB24 */
 126 #define HDMI_CTRL_PKT_BUF_ACCESS_PB25           0x7C /* Control packet data buffer access window - PB25 */
 127 #define HDMI_CTRL_PKT_BUF_ACCESS_PB26           0x7D /* Control packet data buffer access window - PB26 */
 128 #define HDMI_CTRL_PKT_BUF_ACCESS_PB27           0x7E /* Control packet data buffer access window - PB27 */
 129 #define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW        0x80 /* EDID/KSV FIFO access window */
 130 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0       0x81 /* DDC bus access frequency control (LSB) */
 131 #define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8      0x82 /* DDC bus access frequency control (MSB) */
 132 #define HDMI_INTERRUPT_MASK_1                   0x92 /* Interrupt mask.1 */
 133 #define HDMI_INTERRUPT_MASK_2                   0x93 /* Interrupt mask.2 */
 134 #define HDMI_INTERRUPT_STATUS_1                 0x94 /* Interrupt status.1 */
 135 #define HDMI_INTERRUPT_STATUS_2                 0x95 /* Interrupt status.2 */
 136 #define HDMI_INTERRUPT_MASK_3                   0x96 /* Interrupt mask.3 */
 137 #define HDMI_INTERRUPT_MASK_4                   0x97 /* Interrupt mask.4 */
 138 #define HDMI_INTERRUPT_STATUS_3                 0x98 /* Interrupt status.3 */
 139 #define HDMI_INTERRUPT_STATUS_4                 0x99 /* Interrupt status.4 */
 140 #define HDMI_SOFTWARE_HDCP_CONTROL_1            0x9A /* Software HDCP control.1 */
 141 #define HDMI_FRAME_COUNTER                      0x9C /* Frame counter */
 142 #define HDMI_FRAME_COUNTER_FOR_RI_CHECK         0x9D /* Frame counter for Ri check */
 143 #define HDMI_HDCP_CONTROL                       0xAF /* HDCP control */
 144 #define HDMI_RI_FRAME_COUNT_REGISTER            0xB2 /* Ri frame count register */
 145 #define HDMI_DDC_BUS_CONTROL                    0xB7 /* DDC bus control */
 146 #define HDMI_HDCP_STATUS                        0xB8 /* HDCP status */
 147 #define HDMI_SHA0                               0xB9 /* sha0 */
 148 #define HDMI_SHA1                               0xBA /* sha1 */
 149 #define HDMI_SHA2                               0xBB /* sha2 */
 150 #define HDMI_SHA3                               0xBC /* sha3 */
 151 #define HDMI_SHA4                               0xBD /* sha4 */
 152 #define HDMI_BCAPS_READ                         0xBE /* BCAPS read / debug */
 153 #define HDMI_AKSV_BKSV_7_0_MONITOR              0xBF /* AKSV/BKSV[7:0] monitor */
 154 #define HDMI_AKSV_BKSV_15_8_MONITOR             0xC0 /* AKSV/BKSV[15:8] monitor */
 155 #define HDMI_AKSV_BKSV_23_16_MONITOR            0xC1 /* AKSV/BKSV[23:16] monitor */
 156 #define HDMI_AKSV_BKSV_31_24_MONITOR            0xC2 /* AKSV/BKSV[31:24] monitor */
 157 #define HDMI_AKSV_BKSV_39_32_MONITOR            0xC3 /* AKSV/BKSV[39:32] monitor */
 158 #define HDMI_EDID_SEGMENT_POINTER               0xC4 /* EDID segment pointer */
 159 #define HDMI_EDID_WORD_ADDRESS                  0xC5 /* EDID word address */
 160 #define HDMI_EDID_DATA_FIFO_ADDRESS             0xC6 /* EDID data FIFO address */
 161 #define HDMI_NUM_OF_HDMI_DEVICES                0xC7 /* Number of HDMI devices */
 162 #define HDMI_HDCP_ERROR_CODE                    0xC8 /* HDCP error code */
 163 #define HDMI_100MS_TIMER_SET                    0xC9 /* 100ms timer setting */
 164 #define HDMI_5SEC_TIMER_SET                     0xCA /* 5sec timer setting */
 165 #define HDMI_RI_READ_COUNT                      0xCB /* Ri read count */
 166 #define HDMI_AN_SEED                            0xCC /* An seed */
 167 #define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED          0xCD /* Maximum number of receivers allowed */
 168 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1       0xCE /* HDCP memory access control.1 */
 169 #define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2       0xCF /* HDCP memory access control.2 */
 170 #define HDMI_HDCP_CONTROL_2                     0xD0 /* HDCP Control 2 */
 171 #define HDMI_HDCP_KEY_MEMORY_CONTROL            0xD2 /* HDCP Key Memory Control */
 172 #define HDMI_COLOR_SPACE_CONV_CONFIG_1          0xD3 /* Color space conversion configuration.1 */
 173 #define HDMI_VIDEO_SETTING_3                    0xD4 /* Video setting.3 */
 174 #define HDMI_RI_7_0                             0xD5 /* Ri[7:0] */
 175 #define HDMI_RI_15_8                            0xD6 /* Ri[15:8] */
 176 #define HDMI_PJ                                 0xD7 /* Pj */
 177 #define HDMI_SHA_RD                             0xD8 /* sha_rd */
 178 #define HDMI_RI_7_0_SAVED                       0xD9 /* Ri[7:0] saved */
 179 #define HDMI_RI_15_8_SAVED                      0xDA /* Ri[15:8] saved */
 180 #define HDMI_PJ_SAVED                           0xDB /* Pj saved */
 181 #define HDMI_NUM_OF_DEVICES                     0xDC /* Number of devices */
 182 #define HDMI_HOT_PLUG_MSENS_STATUS              0xDF /* Hot plug/MSENS status */
 183 #define HDMI_BCAPS_WRITE                        0xE0 /* bcaps */
 184 #define HDMI_BSTAT_7_0                          0xE1 /* bstat[7:0] */
 185 #define HDMI_BSTAT_15_8                         0xE2 /* bstat[15:8] */
 186 #define HDMI_BKSV_7_0                           0xE3 /* bksv[7:0] */
 187 #define HDMI_BKSV_15_8                          0xE4 /* bksv[15:8] */
 188 #define HDMI_BKSV_23_16                         0xE5 /* bksv[23:16] */
 189 #define HDMI_BKSV_31_24                         0xE6 /* bksv[31:24] */
 190 #define HDMI_BKSV_39_32                         0xE7 /* bksv[39:32] */
 191 #define HDMI_AN_7_0                             0xE8 /* An[7:0] */
 192 #define HDMI_AN_15_8                            0xE9 /* An [15:8] */
 193 #define HDMI_AN_23_16                           0xEA /* An [23:16] */
 194 #define HDMI_AN_31_24                           0xEB /* An [31:24] */
 195 #define HDMI_AN_39_32                           0xEC /* An [39:32] */
 196 #define HDMI_AN_47_40                           0xED /* An [47:40] */
 197 #define HDMI_AN_55_48                           0xEE /* An [55:48] */
 198 #define HDMI_AN_63_56                           0xEF /* An [63:56] */
 199 #define HDMI_PRODUCT_ID                         0xF0 /* Product ID */
 200 #define HDMI_REVISION_ID                        0xF1 /* Revision ID */
 201 #define HDMI_TEST_MODE                          0xFE /* Test mode */
 202
 203 enum hotplug_state {
 204         HDMI_HOTPLUG_DISCONNECTED,
 205         HDMI_HOTPLUG_CONNECTED,
 206         HDMI_HOTPLUG_EDID_DONE,
 207 };
 208
 209 struct sh_hdmi {
 210         void __iomem *base;
 211         enum hotplug_state hp_state;    /* hot-plug status */
 212         bool preprogrammed_mode;        /* use a pre-programmed VIC or the external mode */
 213         struct clk *hdmi_clk;
 214         struct device *dev;
 215         struct fb_info *info;
 216         struct mutex mutex;             /* Protect the info pointer */
 217         struct delayed_work edid_work;
 218         struct fb_var_screeninfo var;
 219         struct fb_monspecs monspec;
 220 };
 221
 222 static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
 223 {
 224         iowrite8(data, hdmi->base + reg);
 225 }
 226
 227 static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
 228 {
 229         return ioread8(hdmi->base + reg);
 230 }
 231
 232 /*
 233  *      HDMI sound
 234  */
 235 static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
 236                                      unsigned int reg)
 237 {
 238         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 239
 240         return hdmi_read(hdmi, reg);
 241 }
 242
 243 static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
 244                              unsigned int reg,
 245                              unsigned int value)
 246 {
 247         struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
 248
 249         hdmi_write(hdmi, value, reg);
 250         return 0;
 251 }
 252
 253 static struct snd_soc_dai_driver sh_hdmi_dai = {
 254         .name = "sh_mobile_hdmi-hifi",
 255         .playback = {
 256                 .stream_name = "Playback",
 257                 .channels_min = 2,
 258                 .channels_max = 8,
 259                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100  |
 260                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200  |
 261                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 262                          SNDRV_PCM_RATE_192000,
 263                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 264         },
 265 };
 266
 267 static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
 268 {
 269         dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
 270
 271         return 0;
 272 }
 273
 274 static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
 275         .probe          = sh_hdmi_snd_probe,
 276         .read           = sh_hdmi_snd_read,
 277         .write          = sh_hdmi_snd_write,
 278 };
 279
 280 /*
 281  *      HDMI video
 282  */
 283
 284 /* External video parameter settings */
 285 static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
 286 {
 287         struct fb_var_screeninfo *var = &hdmi->var;
 288         u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
 289         u8 sync = 0;
 290
 291         htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
 292
 293         hdelay = var->hsync_len + var->left_margin;
 294         hblank = var->right_margin + hdelay;
 295
 296         /*
 297          * Vertical timing looks a bit different in Figure 18,
 298          * but let's try the same first by setting offset = 0
 299          */
 300         vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
 301
 302         vdelay = var->vsync_len + var->upper_margin;
 303         vblank = var->lower_margin + vdelay;
 304         voffset = min(var->upper_margin / 2, 6U);
 305
 306         /*
 307          * [3]: VSYNC polarity: Positive
 308          * [2]: HSYNC polarity: Positive
 309          * [1]: Interlace/Progressive: Progressive
 310          * [0]: External video settings enable: used.
 311          */
 312         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
 313                 sync |= 4;
 314         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 315                 sync |= 8;
 316
 317         dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
 318                 htotal, hblank, hdelay, var->hsync_len,
 319                 vtotal, vblank, vdelay, var->vsync_len, sync);
 320
 321         hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 322
 323         hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
 324         hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
 325
 326         hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
 327         hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
 328
 329         hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
 330         hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
 331
 332         hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
 333         hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
 334
 335         hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
 336         hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
 337
 338         hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
 339
 340         hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
 341
 342         hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
 343
 344         /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
 345         if (!hdmi->preprogrammed_mode)
 346                 hdmi_write(hdmi, sync | 1 | (voffset << 4),
 347                            HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
 348 }
 349
 350 /**
 351  * sh_hdmi_video_config()
 352  */
 353 static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
 354 {
 355         /*
 356          * [7:4]: Audio sampling frequency: 48kHz
 357          * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
 358          * [0]: Internal/External DE select: internal
 359          */
 360         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 361
 362         /*
 363          * [7:6]: Video output format: RGB 4:4:4
 364          * [5:4]: Input video data width: 8 bit
 365          * [3:1]: EAV/SAV location: channel 1
 366          * [0]: Video input color space: RGB
 367          */
 368         hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
 369
 370         /*
 371          * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
 372          * left at 0 by default, this configures 24bpp and sets the Color Depth
 373          * (CD) field in the General Control Packet
 374          */
 375         hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
 376 }
 377
 378 /**
 379  * sh_hdmi_audio_config()
 380  */
 381 static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
 382 {
 383         u8 data;
 384         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 385
 386         /*
 387          * [7:4] L/R data swap control
 388          * [3:0] appropriate N[19:16]
 389          */
 390         hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
 391         /* appropriate N[15:8] */
 392         hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
 393         /* appropriate N[7:0] */
 394         hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
 395
 396         /* [7:4] 48 kHz SPDIF not used */
 397         hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
 398
 399         /*
 400          * [6:5] set required down sampling rate if required
 401          * [4:3] set required audio source
 402          */
 403         switch (pdata->flags & HDMI_SND_SRC_MASK) {
 404         default:
 405                 /* fall through */
 406         case HDMI_SND_SRC_I2S:
 407                 data = 0x0 << 3;
 408                 break;
 409         case HDMI_SND_SRC_SPDIF:
 410                 data = 0x1 << 3;
 411                 break;
 412         case HDMI_SND_SRC_DSD:
 413                 data = 0x2 << 3;
 414                 break;
 415         case HDMI_SND_SRC_HBR:
 416                 data = 0x3 << 3;
 417                 break;
 418         }
 419         hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
 420
 421         /* [3:0] set sending channel number for channel status */
 422         hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
 423
 424         /*
 425          * [5:2] set valid I2S source input pin
 426          * [1:0] set input I2S source mode
 427          */
 428         hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
 429
 430         /* [7:4] set valid DSD source input pin */
 431         hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
 432
 433         /* [7:0] set appropriate I2S input pin swap settings if required */
 434         hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
 435
 436         /*
 437          * [7] set validity bit for channel status
 438          * [3:0] set original sample frequency for channel status
 439          */
 440         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
 441
 442         /*
 443          * [7] set value for channel status
 444          * [6] set value for channel status
 445          * [5] set copyright bit for channel status
 446          * [4:2] set additional information for channel status
 447          * [1:0] set clock accuracy for channel status
 448          */
 449         hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
 450
 451         /* [7:0] set category code for channel status */
 452         hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
 453
 454         /*
 455          * [7:4] set source number for channel status
 456          * [3:0] set word length for channel status
 457          */
 458         hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
 459
 460         /* [7:4] set sample frequency for channel status */
 461         hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
 462 }
 463
 464 /**
 465  * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
 466  */
 467 static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
 468 {
 469         if (hdmi->var.pixclock < 30000) {
 470                 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
 471                 /*
 472                  * [1:0]        Speed_A
 473                  * [3:2]        Speed_B
 474                  * [4]          PLLA_Bypass
 475                  * [6]          DRV_TEST_EN
 476                  * [7]          DRV_TEST_IN
 477                  */
 478                 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 479                 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
 480                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 481                 /*
 482                  * [2:0]        BGR_I_OFFSET
 483                  * [6:4]        BGR_V_OFFSET
 484                  */
 485                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 486                 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
 487                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 488                 /*
 489                  * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
 490                  * LPF capacitance, LPF resistance[1]
 491                  */
 492                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 493                 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
 494                 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 495                 /*
 496                  * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
 497                  * LPF capacitance, LPF resistance[1]
 498                  */
 499                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 500                 /* DRV_CONFIG, PE_CONFIG */
 501                 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 502                 /*
 503                  * [2:0]        AMON_SEL (4 == LPF voltage)
 504                  * [4]          PLLA_CONFIG[16]
 505                  * [5]          PLLB_CONFIG[16]
 506                  */
 507                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 508         } else {
 509                 /* for 480p8bit 27MHz */
 510                 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
 511                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
 512                 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
 513                 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
 514                 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
 515                 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
 516                 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
 517                 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
 518                 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
 519         }
 520 }
 521
 522 /**
 523  * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
 524  */
 525 static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
 526 {
 527         u8 vic;
 528
 529         /* AVI InfoFrame */
 530         hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
 531
 532         /* Packet Type = 0x82 */
 533         hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 534
 535         /* Version = 0x02 */
 536         hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 537
 538         /* Length = 13 (0x0D) */
 539         hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 540
 541         /* N. A. Checksum */
 542         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 543
 544         /*
 545          * Y = RGB
 546          * A0 = No Data
 547          * B = Bar Data not valid
 548          * S = No Data
 549          */
 550         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 551
 552         /*
 553          * [7:6] C = Colorimetry: no data
 554          * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
 555          * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
 556          */
 557         hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 558
 559         /*
 560          * ITC = No Data
 561          * EC = xvYCC601
 562          * Q = Default (depends on video format)
 563          * SC = No Known non_uniform Scaling
 564          */
 565         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 566
 567         /*
 568          * VIC = 1280 x 720p: ignored if external config is used
 569          * Send 2 for 720 x 480p, 16 for 1080p, ignored in external mode
 570          */
 571         if (hdmi->var.yres == 1080 && hdmi->var.xres == 1920)
 572                 vic = 16;
 573         else if (hdmi->var.yres == 576 && hdmi->var.xres == 720)
 574                 vic = 17;
 575         else if (hdmi->var.yres == 480 && hdmi->var.xres == 720)
 576                 vic = 2;
 577         else if (hdmi->var.yres == 480 && hdmi->var.xres == 640)
 578                 vic = 1;
 579         else
 580                 vic = 4;
 581         hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 582
 583         /* PR = No Repetition */
 584         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 585
 586         /* Line Number of End of Top Bar (lower 8 bits) */
 587         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 588
 589         /* Line Number of End of Top Bar (upper 8 bits) */
 590         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 591
 592         /* Line Number of Start of Bottom Bar (lower 8 bits) */
 593         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 594
 595         /* Line Number of Start of Bottom Bar (upper 8 bits) */
 596         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 597
 598         /* Pixel Number of End of Left Bar (lower 8 bits) */
 599         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 600
 601         /* Pixel Number of End of Left Bar (upper 8 bits) */
 602         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
 603
 604         /* Pixel Number of Start of Right Bar (lower 8 bits) */
 605         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
 606
 607         /* Pixel Number of Start of Right Bar (upper 8 bits) */
 608         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
 609 }
 610
 611 /**
 612  * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
 613  */
 614 static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
 615 {
 616         /* Audio InfoFrame */
 617         hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
 618
 619         /* Packet Type = 0x84 */
 620         hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
 621
 622         /* Version Number = 0x01 */
 623         hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
 624
 625         /* 0 Length = 10 (0x0A) */
 626         hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
 627
 628         /* n. a. Checksum */
 629         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
 630
 631         /* Audio Channel Count = Refer to Stream Header */
 632         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
 633
 634         /* Refer to Stream Header */
 635         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
 636
 637         /* Format depends on coding type (i.e. CT0...CT3) */
 638         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
 639
 640         /* Speaker Channel Allocation = Front Right + Front Left */
 641         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
 642
 643         /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
 644         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
 645
 646         /* Reserved (0) */
 647         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
 648         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
 649         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
 650         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
 651         hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
 652 }
 653
 654 /**
 655  * sh_hdmi_configure() - Initialise HDMI for output
 656  */
 657 static void sh_hdmi_configure(struct sh_hdmi *hdmi)
 658 {
 659         /* Configure video format */
 660         sh_hdmi_video_config(hdmi);
 661
 662         /* Configure audio format */
 663         sh_hdmi_audio_config(hdmi);
 664
 665         /* Configure PHY */
 666         sh_hdmi_phy_config(hdmi);
 667
 668         /* Auxiliary Video Information (AVI) InfoFrame */
 669         sh_hdmi_avi_infoframe_setup(hdmi);
 670
 671         /* Audio InfoFrame */
 672         sh_hdmi_audio_infoframe_setup(hdmi);
 673
 674         /*
 675          * Control packet auto send with VSYNC control: auto send
 676          * General control, Gamut metadata, ISRC, and ACP packets
 677          */
 678         hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
 679
 680         /* FIXME */
 681         msleep(10);
 682
 683         /* PS mode b->d, reset PLLA and PLLB */
 684         hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
 685
 686         udelay(10);
 687
 688         hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
 689 }
 690
 691 static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
 692                 const struct fb_videomode *mode,
 693                 unsigned long *hdmi_rate, unsigned long *parent_rate)
 694 {
 695         unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
 696         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 697
 698         *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
 699         if ((long)*hdmi_rate < 0)
 700                 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
 701
 702         rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
 703         if (rate_error && pdata->clk_optimize_parent)
 704                 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
 705         else if (clk_get_parent(hdmi->hdmi_clk))
 706                 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
 707
 708         dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
 709                 mode->left_margin, mode->xres,
 710                 mode->right_margin, mode->hsync_len,
 711                 mode->upper_margin, mode->yres,
 712                 mode->lower_margin, mode->vsync_len);
 713
 714         dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
 715                 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
 716                 mode->refresh, *parent_rate);
 717
 718         return rate_error;
 719 }
 720
 721 static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
 722                              unsigned long *parent_rate)
 723 {
 724         struct fb_var_screeninfo tmpvar;
 725         struct fb_var_screeninfo *var = &tmpvar;
 726         const struct fb_videomode *mode, *found = NULL;
 727         struct fb_info *info = hdmi->info;
 728         struct fb_modelist *modelist = NULL;
 729         unsigned int f_width = 0, f_height = 0, f_refresh = 0;
 730         unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
 731         bool exact_match = false;
 732         u8 edid[128];
 733         char *forced;
 734         int i;
 735
 736         /* Read EDID */
 737         dev_dbg(hdmi->dev, "Read back EDID code:");
 738         for (i = 0; i < 128; i++) {
 739                 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
 740 #ifdef DEBUG
 741                 if ((i % 16) == 0) {
 742                         printk(KERN_CONT "\n");
 743                         printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
 744                 } else {
 745                         printk(KERN_CONT " %02X", edid[i]);
 746                 }
 747 #endif
 748         }
 749 #ifdef DEBUG
 750         printk(KERN_CONT "\n");
 751 #endif
 752
 753         fb_edid_to_monspecs(edid, &hdmi->monspec);
 754
 755         fb_get_options("sh_mobile_lcdc", &forced);
 756         if (forced && *forced) {
 757                 /* Only primitive parsing so far */
 758                 i = sscanf(forced, "%ux%u@%u",
 759                            &f_width, &f_height, &f_refresh);
 760                 if (i < 2) {
 761                         f_width = 0;
 762                         f_height = 0;
 763                 }
 764                 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
 765                         f_width, f_height, f_refresh);
 766         }
 767
 768         /* Walk monitor modes to find the best or the exact match */
 769         for (i = 0, mode = hdmi->monspec.modedb;
 770              f_width && f_height && i < hdmi->monspec.modedb_len && !exact_match;
 771              i++, mode++) {
 772                 unsigned long rate_error;
 773
 774                 /* No interest in unmatching modes */
 775                 if (f_width != mode->xres || f_height != mode->yres)
 776                         continue;
 777
 778                 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
 779
 780                 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
 781                         /*
 782                          * Exact match if either the refresh rate matches or it
 783                          * hasn't been specified and we've found a mode, for
 784                          * which we can configure the clock precisely
 785                          */
 786                         exact_match = true;
 787                 else if (found && found_rate_error <= rate_error)
 788                         /*
 789                          * We otherwise search for the closest matching clock
 790                          * rate - either if no refresh rate has been specified
 791                          * or we cannot find an exactly matching one
 792                          */
 793                         continue;
 794
 795                 /* Check if supported: sufficient fb memory, supported clock-rate */
 796                 fb_videomode_to_var(var, mode);
 797
 798                 if (info && info->fbops->fb_check_var &&
 799                     info->fbops->fb_check_var(var, info)) {
 800                         exact_match = false;
 801                         continue;
 802                 }
 803
 804                 found = mode;
 805                 found_rate_error = rate_error;
 806         }
 807
 808         /*
 809          * TODO 1: if no ->info is present, postpone running the config until
 810          * after ->info first gets registered.
 811          * TODO 2: consider registering the HDMI platform device from the LCDC
 812          * driver, and passing ->info with HDMI platform data.
 813          */
 814         if (info && !found) {
 815                 modelist = hdmi->info->modelist.next &&
 816                         !list_empty(&hdmi->info->modelist) ?
 817                         list_entry(hdmi->info->modelist.next,
 818                                    struct fb_modelist, list) :
 819                         NULL;
 820
 821                 if (modelist) {
 822                         found = &modelist->mode;
 823                         found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
 824                 }
 825         }
 826
 827         /* No cookie today */
 828         if (!found)
 829                 return -ENXIO;
 830
 831         if ((found->xres == 640 && found->yres == 480 && found->refresh == 60) ||
 832             (found->xres == 720 && found->yres == 480 && found->refresh == 60) ||
 833             (found->xres == 720 && found->yres == 576 && found->refresh == 50) ||
 834             (found->xres == 1280 && found->yres == 720 && found->refresh == 60) ||
 835             (found->xres == 1920 && found->yres == 1080 && found->refresh == 60))
 836                 hdmi->preprogrammed_mode = true;
 837         else
 838                 hdmi->preprogrammed_mode = false;
 839
 840         dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
 841                 modelist ? "default" : "EDID", hdmi->preprogrammed_mode ? "VIC" : "external",
 842                 found->xres, found->yres, found->refresh,
 843                 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
 844
 845         fb_videomode_to_var(&hdmi->var, found);
 846         sh_hdmi_external_video_param(hdmi);
 847
 848         return 0;
 849 }
 850
 851 static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
 852 {
 853         struct sh_hdmi *hdmi = dev_id;
 854         u8 status1, status2, mask1, mask2;
 855
 856         /* mode_b and PLLA and PLLB reset */
 857         hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
 858
 859         /* How long shall reset be held? */
 860         udelay(10);
 861
 862         /* mode_b and PLLA and PLLB reset release */
 863         hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
 864
 865         status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
 866         status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
 867
 868         mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
 869         mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
 870
 871         /* Correct would be to ack only set bits, but the datasheet requires 0xff */
 872         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
 873         hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
 874
 875         if (printk_ratelimit())
 876                 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
 877                         irq, status1, mask1, status2, mask2);
 878
 879         if (!((status1 & mask1) | (status2 & mask2))) {
 880                 return IRQ_NONE;
 881         } else if (status1 & 0xc0) {
 882                 u8 msens;
 883
 884                 /* Datasheet specifies 10ms... */
 885                 udelay(500);
 886
 887                 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
 888                 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
 889                 /* Check, if hot plug & MSENS pin status are both high */
 890                 if ((msens & 0xC0) == 0xC0) {
 891                         /* Display plug in */
 892                         hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
 893
 894                         /* Set EDID word address  */
 895                         hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 896                         /* Set EDID segment pointer */
 897                         hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 898                         /* Enable EDID interrupt */
 899                         hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
 900                 } else if (!(status1 & 0x80)) {
 901                         /* Display unplug, beware multiple interrupts */
 902                         if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED)
 903                                 schedule_delayed_work(&hdmi->edid_work, 0);
 904
 905                         hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
 906                         /* display_off will switch back to mode_a */
 907                 }
 908         } else if (status1 & 2) {
 909                 /* EDID error interrupt: retry */
 910                 /* Set EDID word address  */
 911                 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
 912                 /* Set EDID segment pointer */
 913                 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
 914         } else if (status1 & 4) {
 915                 /* Disable EDID interrupt */
 916                 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
 917                 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
 918                 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
 919         }
 920
 921         return IRQ_HANDLED;
 922 }
 923
 924 /* locking:     called with info->lock held, or before register_framebuffer() */
 925 static void sh_hdmi_display_on(void *arg, struct fb_info *info)
 926 {
 927         /*
 928          * info is guaranteed to be valid, when we are called, because our
 929          * FB_EVENT_FB_UNBIND notify is also called with info->lock held
 930          */
 931         struct sh_hdmi *hdmi = arg;
 932         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 933         struct sh_mobile_lcdc_chan *ch = info->par;
 934
 935         dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
 936                 pdata->lcd_dev, info->state);
 937
 938         /* No need to lock */
 939         hdmi->info = info;
 940
 941         /*
 942          * hp_state can be set to
 943          * HDMI_HOTPLUG_DISCONNECTED:   on monitor unplug
 944          * HDMI_HOTPLUG_CONNECTED:      on monitor plug-in
 945          * HDMI_HOTPLUG_EDID_DONE:      on EDID read completion
 946          */
 947         switch (hdmi->hp_state) {
 948         case HDMI_HOTPLUG_EDID_DONE:
 949                 /* PS mode d->e. All functions are active */
 950                 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
 951                 dev_dbg(hdmi->dev, "HDMI running\n");
 952                 break;
 953         case HDMI_HOTPLUG_DISCONNECTED:
 954                 info->state = FBINFO_STATE_SUSPENDED;
 955         default:
 956                 hdmi->var = ch->display_var;
 957         }
 958 }
 959
 960 /* locking: called with info->lock held */
 961 static void sh_hdmi_display_off(void *arg)
 962 {
 963         struct sh_hdmi *hdmi = arg;
 964         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
 965
 966         dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
 967         /* PS mode e->a */
 968         hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
 969 }
 970
 971 static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
 972 {
 973         struct fb_info *info = hdmi->info;
 974         struct sh_mobile_lcdc_chan *ch = info->par;
 975         struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
 976         struct fb_videomode mode1, mode2;
 977
 978         fb_var_to_videomode(&mode1, old_var);
 979         fb_var_to_videomode(&mode2, new_var);
 980
 981         dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
 982                 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
 983
 984         if (fb_mode_is_equal(&mode1, &mode2))
 985                 return false;
 986
 987         dev_dbg(info->dev, "Switching %u -> %u lines\n",
 988                 mode1.yres, mode2.yres);
 989         *old_var = *new_var;
 990
 991         return true;
 992 }
 993
 994 /**
 995  * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
 996  * @hdmi:               driver context
 997  * @hdmi_rate:          HDMI clock frequency in Hz
 998  * @parent_rate:        if != 0 - set parent clock rate for optimal precision
 999  * return:              configured positive rate if successful
1000  *                      0 if couldn't set the rate, but managed to enable the
1001  *                      clock, negative error, if couldn't enable the clock
1002  */
1003 static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1004                                   unsigned long parent_rate)
1005 {
1006         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1007         int ret;
1008
1009         if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1010                 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
1011                 if (ret < 0) {
1012                         dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1013                         hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
1014                 } else {
1015                         dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
1016                 }
1017         }
1018
1019         ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
1020         if (ret < 0) {
1021                 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1022                 hdmi_rate = 0;
1023         } else {
1024                 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
1025         }
1026
1027         return hdmi_rate;
1028 }
1029
1030 /* Hotplug interrupt occurred, read EDID */
1031 static void sh_hdmi_edid_work_fn(struct work_struct *work)
1032 {
1033         struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1034         struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1035         struct sh_mobile_lcdc_chan *ch;
1036         int ret;
1037
1038         dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1039                 pdata->lcd_dev, hdmi->hp_state);
1040
1041         if (!pdata->lcd_dev)
1042                 return;
1043
1044         mutex_lock(&hdmi->mutex);
1045
1046         if (hdmi->hp_state == HDMI_HOTPLUG_EDID_DONE) {
1047                 unsigned long parent_rate = 0, hdmi_rate;
1048
1049                 /* A device has been plugged in */
1050                 pm_runtime_get_sync(hdmi->dev);
1051
1052                 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
1053                 if (ret < 0)
1054                         goto out;
1055
1056                 /* Reconfigure the clock */
1057                 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
1058                 if (ret < 0)
1059                         goto out;
1060
1061                 msleep(10);
1062                 sh_hdmi_configure(hdmi);
1063                 /* Switched to another (d) power-save mode */
1064                 msleep(10);
1065
1066                 if (!hdmi->info)
1067                         goto out;
1068
1069                 ch = hdmi->info->par;
1070
1071                 acquire_console_sem();
1072
1073                 /* HDMI plug in */
1074                 if (!sh_hdmi_must_reconfigure(hdmi) &&
1075                     hdmi->info->state == FBINFO_STATE_RUNNING) {
1076                         /*
1077                          * First activation with the default monitor - just turn
1078                          * on, if we run a resume here, the logo disappears
1079                          */
1080                         if (lock_fb_info(hdmi->info)) {
1081                                 sh_hdmi_display_on(hdmi, hdmi->info);
1082                                 unlock_fb_info(hdmi->info);
1083                         }
1084                 } else {
1085                         /* New monitor or have to wake up */
1086                         fb_set_suspend(hdmi->info, 0);
1087                 }
1088
1089                 release_console_sem();
1090         } else {
1091                 ret = 0;
1092                 if (!hdmi->info)
1093                         goto out;
1094
1095                 hdmi->monspec.modedb_len = 0;
1096                 fb_destroy_modedb(hdmi->monspec.modedb);
1097                 hdmi->monspec.modedb = NULL;
1098
1099                 acquire_console_sem();
1100
1101                 /* HDMI disconnect */
1102                 fb_set_suspend(hdmi->info, 1);
1103
1104                 release_console_sem();
1105                 pm_runtime_put(hdmi->dev);
1106         }
1107
1108 out:
1109         if (ret < 0)
1110                 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
1111         mutex_unlock(&hdmi->mutex);
1112
1113         dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
1114 }
1115
1116 static int sh_hdmi_notify(struct notifier_block *nb,
1117                           unsigned long action, void *data);
1118
1119 static struct notifier_block sh_hdmi_notifier = {
1120         .notifier_call = sh_hdmi_notify,
1121 };
1122
1123 static int sh_hdmi_notify(struct notifier_block *nb,
1124                           unsigned long action, void *data)
1125 {
1126         struct fb_event *event = data;
1127         struct fb_info *info = event->info;
1128         struct sh_mobile_lcdc_chan *ch = info->par;
1129         struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1130         struct sh_hdmi *hdmi = board_cfg->board_data;
1131
1132         if (nb != &sh_hdmi_notifier || !hdmi || hdmi->info != info)
1133                 return NOTIFY_DONE;
1134
1135         switch(action) {
1136         case FB_EVENT_FB_REGISTERED:
1137                 /* Unneeded, activation taken care by sh_hdmi_display_on() */
1138                 break;
1139         case FB_EVENT_FB_UNREGISTERED:
1140                 /*
1141                  * We are called from unregister_framebuffer() with the
1142                  * info->lock held. This is bad for us, because we can race with
1143                  * the scheduled work, which has to call fb_set_suspend(), which
1144                  * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1145                  * cannot take and hold info->lock for the whole function
1146                  * duration. Using an additional lock creates a classical AB-BA
1147                  * lock up. Therefore, we have to release the info->lock
1148                  * temporarily, synchronise with the work queue and re-acquire
1149                  * the info->lock.
1150                  */
1151                 unlock_fb_info(hdmi->info);
1152                 mutex_lock(&hdmi->mutex);
1153                 hdmi->info = NULL;
1154                 mutex_unlock(&hdmi->mutex);
1155                 lock_fb_info(hdmi->info);
1156                 return NOTIFY_OK;
1157         }
1158         return NOTIFY_DONE;
1159 }
1160
1161 static int __init sh_hdmi_probe(struct platform_device *pdev)
1162 {
1163         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1164         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1165         struct sh_mobile_lcdc_board_cfg *board_cfg;
1166         int irq = platform_get_irq(pdev, 0), ret;
1167         struct sh_hdmi *hdmi;
1168         long rate;
1169
1170         if (!res || !pdata || irq < 0)
1171                 return -ENODEV;
1172
1173         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1174         if (!hdmi) {
1175                 dev_err(&pdev->dev, "Cannot allocate device data\n");
1176                 return -ENOMEM;
1177         }
1178
1179         mutex_init(&hdmi->mutex);
1180
1181         hdmi->dev = &pdev->dev;
1182
1183         hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1184         if (IS_ERR(hdmi->hdmi_clk)) {
1185                 ret = PTR_ERR(hdmi->hdmi_clk);
1186                 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1187                 goto egetclk;
1188         }
1189
1190         /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1191         rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1192         if (rate > 0)
1193                 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1194
1195         if (rate < 0) {
1196                 ret = rate;
1197                 goto erate;
1198         }
1199
1200         ret = clk_enable(hdmi->hdmi_clk);
1201         if (ret < 0) {
1202                 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1203                 goto erate;
1204         }
1205
1206         dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
1207
1208         if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1209                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1210                 ret = -EBUSY;
1211                 goto ereqreg;
1212         }
1213
1214         hdmi->base = ioremap(res->start, resource_size(res));
1215         if (!hdmi->base) {
1216                 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1217                 ret = -ENOMEM;
1218                 goto emap;
1219         }
1220
1221         platform_set_drvdata(pdev, hdmi);
1222
1223         /* Set up LCDC callbacks */
1224         board_cfg = &pdata->lcd_chan->board_cfg;
1225         board_cfg->owner = THIS_MODULE;
1226         board_cfg->board_data = hdmi;
1227         board_cfg->display_on = sh_hdmi_display_on;
1228         board_cfg->display_off = sh_hdmi_display_off;
1229
1230         INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
1231
1232         pm_runtime_enable(&pdev->dev);
1233         pm_runtime_resume(&pdev->dev);
1234
1235         /* Product and revision IDs are 0 in sh-mobile version */
1236         dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1237                  hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1238
1239         ret = request_irq(irq, sh_hdmi_hotplug, 0,
1240                           dev_name(&pdev->dev), hdmi);
1241         if (ret < 0) {
1242                 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1243                 goto ereqirq;
1244         }
1245
1246         ret = snd_soc_register_codec(&pdev->dev,
1247                         &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1248         if (ret < 0) {
1249                 dev_err(&pdev->dev, "codec registration failed\n");
1250                 goto ecodec;
1251         }
1252
1253         return 0;
1254
1255 ecodec:
1256         free_irq(irq, hdmi);
1257 ereqirq:
1258         pm_runtime_disable(&pdev->dev);
1259         iounmap(hdmi->base);
1260 emap:
1261         release_mem_region(res->start, resource_size(res));
1262 ereqreg:
1263         clk_disable(hdmi->hdmi_clk);
1264 erate:
1265         clk_put(hdmi->hdmi_clk);
1266 egetclk:
1267         mutex_destroy(&hdmi->mutex);
1268         kfree(hdmi);
1269
1270         return ret;
1271 }
1272
1273 static int __exit sh_hdmi_remove(struct platform_device *pdev)
1274 {
1275         struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1276         struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1277         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1278         struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
1279         int irq = platform_get_irq(pdev, 0);
1280
1281         snd_soc_unregister_codec(&pdev->dev);
1282
1283         board_cfg->display_on = NULL;
1284         board_cfg->display_off = NULL;
1285         board_cfg->board_data = NULL;
1286         board_cfg->owner = NULL;
1287
1288         /* No new work will be scheduled, wait for running ISR */
1289         free_irq(irq, hdmi);
1290         /* Wait for already scheduled work */
1291         cancel_delayed_work_sync(&hdmi->edid_work);
1292         pm_runtime_disable(&pdev->dev);
1293         clk_disable(hdmi->hdmi_clk);
1294         clk_put(hdmi->hdmi_clk);
1295         iounmap(hdmi->base);
1296         release_mem_region(res->start, resource_size(res));
1297         mutex_destroy(&hdmi->mutex);
1298         kfree(hdmi);
1299
1300         return 0;
1301 }
1302
1303 static struct platform_driver sh_hdmi_driver = {
1304         .remove         = __exit_p(sh_hdmi_remove),
1305         .driver = {
1306                 .name   = "sh-mobile-hdmi",
1307         },
1308 };
1309
1310 static int __init sh_hdmi_init(void)
1311 {
1312         return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1313 }
1314 module_init(sh_hdmi_init);
1315
1316 static void __exit sh_hdmi_exit(void)
1317 {
1318         platform_driver_unregister(&sh_hdmi_driver);
1319 }
1320 module_exit(sh_hdmi_exit);
1321
1322 MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1323 MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1324 MODULE_LICENSE("GPL v2");