drivers/usb/host/xhci-ring.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Ring initialization rules:
  25  * 1. Each segment is initialized to zero, except for link TRBs.
  26  * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27  *    Consumer Cycle State (CCS), depending on ring function.
  28  * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29  *
  30  * Ring behavior rules:
  31  * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32  *    least one free TRB in the ring.  This is useful if you want to turn that
  33  *    into a link TRB and expand the ring.
  34  * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35  *    link TRB, then load the pointer with the address in the link TRB.  If the
  36  *    link TRB had its toggle bit set, you may need to update the ring cycle
  37  *    state (see cycle bit rules).  You may have to do this multiple times
  38  *    until you reach a non-link TRB.
  39  * 3. A ring is full if enqueue++ (for the definition of increment above)
  40  *    equals the dequeue pointer.
  41  *
  42  * Cycle bit rules:
  43  * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44  *    in a link TRB, it must toggle the ring cycle state.
  45  * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46  *    in a link TRB, it must toggle the ring cycle state.
  47  *
  48  * Producer rules:
  49  * 1. Check if ring is full before you enqueue.
  50  * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51  *    Update enqueue pointer between each write (which may update the ring
  52  *    cycle state).
  53  * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54  *    and endpoint rings.  If HC is the producer for the event ring,
  55  *    and it generates an interrupt according to interrupt modulation rules.
  56  *
  57  * Consumer rules:
  58  * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59  *    the TRB is owned by the consumer.
  60  * 2. Update dequeue pointer (which may update the ring cycle state) and
  61  *    continue processing TRBs until you reach a TRB which is not owned by you.
  62  * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63  *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64  *   endpoint rings; it generates events on the event ring for these.
  65  */
  66
  67 #include <linux/scatterlist.h>
  68 #include <linux/slab.h>
  69 #include "xhci.h"
  70
  71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                 struct xhci_virt_device *virt_dev,
  73                 struct xhci_event_cmd *event);
  74
  75 /*
  76  * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77  * address of the TRB.
  78  */
  79 dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                 union xhci_trb *trb)
  81 {
  82         unsigned long segment_offset;
  83
  84         if (!seg || !trb || trb < seg->trbs)
  85                 return 0;
  86         /* offset in TRBs */
  87         segment_offset = trb - seg->trbs;
  88         if (segment_offset >= TRBS_PER_SEGMENT)
  89                 return 0;
  90         return seg->dma + (segment_offset * sizeof(*trb));
  91 }
  92
  93 /* Does this link TRB point to the first segment in a ring,
  94  * or was the previous TRB the last TRB on the last segment in the ERST?
  95  */
  96 static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                 struct xhci_segment *seg, union xhci_trb *trb)
  98 {
  99         if (ring == xhci->event_ring)
 100                 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                         (seg->next == xhci->event_ring->first_seg);
 102         else
 103                 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104 }
 105
 106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107  * segment?  I.e. would the updated event TRB pointer step off the end of the
 108  * event seg?
 109  */
 110 static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                 struct xhci_segment *seg, union xhci_trb *trb)
 112 {
 113         if (ring == xhci->event_ring)
 114                 return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115         else
 116                 return TRB_TYPE_LINK_LE32(trb->link.control);
 117 }
 118
 119 static int enqueue_is_link_trb(struct xhci_ring *ring)
 120 {
 121         struct xhci_link_trb *link = &ring->enqueue->link;
 122         return TRB_TYPE_LINK_LE32(link->control);
 123 }
 124
 125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126  * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127  * effect the ring dequeue or enqueue pointers.
 128  */
 129 static void next_trb(struct xhci_hcd *xhci,
 130                 struct xhci_ring *ring,
 131                 struct xhci_segment **seg,
 132                 union xhci_trb **trb)
 133 {
 134         if (last_trb(xhci, ring, *seg, *trb)) {
 135                 *seg = (*seg)->next;
 136                 *trb = ((*seg)->trbs);
 137         } else {
 138                 (*trb)++;
 139         }
 140 }
 141
 142 /*
 143  * See Cycle bit rules. SW is the consumer for the event ring only.
 144  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145  */
 146 static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
 147 {
 148         unsigned long long addr;
 149
 150         ring->deq_updates++;
 151
 152         do {
 153                 /*
 154                  * Update the dequeue pointer further if that was a link TRB or
 155                  * we're at the end of an event ring segment (which doesn't have
 156                  * link TRBS)
 157                  */
 158                 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 159                         if (consumer && last_trb_on_last_seg(xhci, ring,
 160                                                 ring->deq_seg, ring->dequeue)) {
 161                                 if (!in_interrupt())
 162                                         xhci_dbg(xhci, "Toggle cycle state "
 163                                                         "for ring %p = %i\n",
 164                                                         ring,
 165                                                         (unsigned int)
 166                                                         ring->cycle_state);
 167                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 168                         }
 169                         ring->deq_seg = ring->deq_seg->next;
 170                         ring->dequeue = ring->deq_seg->trbs;
 171                 } else {
 172                         ring->dequeue++;
 173                 }
 174         } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 175
 176         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 177 }
 178
 179 /*
 180  * See Cycle bit rules. SW is the consumer for the event ring only.
 181  * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 182  *
 183  * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 184  * chain bit is set), then set the chain bit in all the following link TRBs.
 185  * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 186  * have their chain bit cleared (so that each Link TRB is a separate TD).
 187  *
 188  * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 189  * set, but other sections talk about dealing with the chain bit set.  This was
 190  * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 191  * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 192  *
 193  * @more_trbs_coming:   Will you enqueue more TRBs before calling
 194  *                      prepare_transfer()?
 195  */
 196 static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 197                 bool consumer, bool more_trbs_coming, bool isoc)
 198 {
 199         u32 chain;
 200         union xhci_trb *next;
 201         unsigned long long addr;
 202
 203         chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 204         next = ++(ring->enqueue);
 205
 206         ring->enq_updates++;
 207         /* Update the dequeue pointer further if that was a link TRB or we're at
 208          * the end of an event ring segment (which doesn't have link TRBS)
 209          */
 210         while (last_trb(xhci, ring, ring->enq_seg, next)) {
 211                 if (!consumer) {
 212                         if (ring != xhci->event_ring) {
 213                                 /*
 214                                  * If the caller doesn't plan on enqueueing more
 215                                  * TDs before ringing the doorbell, then we
 216                                  * don't want to give the link TRB to the
 217                                  * hardware just yet.  We'll give the link TRB
 218                                  * back in prepare_ring() just before we enqueue
 219                                  * the TD at the top of the ring.
 220                                  */
 221                                 if (!chain && !more_trbs_coming)
 222                                         break;
 223
 224                                 /* If we're not dealing with 0.95 hardware or
 225                                  * isoc rings on AMD 0.96 host,
 226                                  * carry over the chain bit of the previous TRB
 227                                  * (which may mean the chain bit is cleared).
 228                                  */
 229                                 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
 230                                                 && !xhci_link_trb_quirk(xhci)) {
 231                                         next->link.control &=
 232                                                 cpu_to_le32(~TRB_CHAIN);
 233                                         next->link.control |=
 234                                                 cpu_to_le32(chain);
 235                                 }
 236                                 /* Give this link TRB to the hardware */
 237                                 wmb();
 238                                 next->link.control ^= cpu_to_le32(TRB_CYCLE);
 239                         }
 240                         /* Toggle the cycle bit after the last ring segment. */
 241                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 242                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
 243                                 if (!in_interrupt())
 244                                         xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
 245                                                         ring,
 246                                                         (unsigned int) ring->cycle_state);
 247                         }
 248                 }
 249                 ring->enq_seg = ring->enq_seg->next;
 250                 ring->enqueue = ring->enq_seg->trbs;
 251                 next = ring->enqueue;
 252         }
 253         addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 254 }
 255
 256 /*
 257  * Check to see if there's room to enqueue num_trbs on the ring.  See rules
 258  * above.
 259  * FIXME: this would be simpler and faster if we just kept track of the number
 260  * of free TRBs in a ring.
 261  */
 262 static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 263                 unsigned int num_trbs)
 264 {
 265         int i;
 266         union xhci_trb *enq = ring->enqueue;
 267         struct xhci_segment *enq_seg = ring->enq_seg;
 268         struct xhci_segment *cur_seg;
 269         unsigned int left_on_ring;
 270
 271         /* If we are currently pointing to a link TRB, advance the
 272          * enqueue pointer before checking for space */
 273         while (last_trb(xhci, ring, enq_seg, enq)) {
 274                 enq_seg = enq_seg->next;
 275                 enq = enq_seg->trbs;
 276         }
 277
 278         /* Check if ring is empty */
 279         if (enq == ring->dequeue) {
 280                 /* Can't use link trbs */
 281                 left_on_ring = TRBS_PER_SEGMENT - 1;
 282                 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
 283                                 cur_seg = cur_seg->next)
 284                         left_on_ring += TRBS_PER_SEGMENT - 1;
 285
 286                 /* Always need one TRB free in the ring. */
 287                 left_on_ring -= 1;
 288                 if (num_trbs > left_on_ring) {
 289                         xhci_warn(xhci, "Not enough room on ring; "
 290                                         "need %u TRBs, %u TRBs left\n",
 291                                         num_trbs, left_on_ring);
 292                         return 0;
 293                 }
 294                 return 1;
 295         }
 296         /* Make sure there's an extra empty TRB available */
 297         for (i = 0; i <= num_trbs; ++i) {
 298                 if (enq == ring->dequeue)
 299                         return 0;
 300                 enq++;
 301                 while (last_trb(xhci, ring, enq_seg, enq)) {
 302                         enq_seg = enq_seg->next;
 303                         enq = enq_seg->trbs;
 304                 }
 305         }
 306         return 1;
 307 }
 308
 309 /* Ring the host controller doorbell after placing a command on the ring */
 310 void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 311 {
 312         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 313                 return;
 314
 315         xhci_dbg(xhci, "// Ding dong!\n");
 316         xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 317         /* Flush PCI posted writes */
 318         xhci_readl(xhci, &xhci->dba->doorbell[0]);
 319 }
 320
 321 static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 322 {
 323         u64 temp_64;
 324         int ret;
 325
 326         xhci_dbg(xhci, "Abort command ring\n");
 327
 328         if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 329                 xhci_dbg(xhci, "The command ring isn't running, "
 330                                 "Have the command ring been stopped?\n");
 331                 return 0;
 332         }
 333
 334         temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 335         if (!(temp_64 & CMD_RING_RUNNING)) {
 336                 xhci_dbg(xhci, "Command ring had been stopped\n");
 337                 return 0;
 338         }
 339         xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 340         xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 341                         &xhci->op_regs->cmd_ring);
 342
 343         /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 344          * time the completion od all xHCI commands, including
 345          * the Command Abort operation. If software doesn't see
 346          * CRR negated in a timely manner (e.g. longer than 5
 347          * seconds), then it should assume that the there are
 348          * larger problems with the xHC and assert HCRST.
 349          */
 350         ret = handshake(xhci, &xhci->op_regs->cmd_ring,
 351                         CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 352         if (ret < 0) {
 353                 /* we are about to kill xhci, give it one more chance */
 354                 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 355                               &xhci->op_regs->cmd_ring);
 356                 udelay(1000);
 357                 ret = handshake(xhci, &xhci->op_regs->cmd_ring,
 358                                 CMD_RING_RUNNING, 0, 3 * 1000 * 1000);
 359                 if (ret == 0)
 360                         return 0;
 361
 362                 xhci_err(xhci, "Stopped the command ring failed, "
 363                                 "maybe the host is dead\n");
 364                 xhci->xhc_state |= XHCI_STATE_DYING;
 365                 xhci_quiesce(xhci);
 366                 xhci_halt(xhci);
 367                 return -ESHUTDOWN;
 368         }
 369
 370         return 0;
 371 }
 372
 373 static int xhci_queue_cd(struct xhci_hcd *xhci,
 374                 struct xhci_command *command,
 375                 union xhci_trb *cmd_trb)
 376 {
 377         struct xhci_cd *cd;
 378         cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 379         if (!cd)
 380                 return -ENOMEM;
 381         INIT_LIST_HEAD(&cd->cancel_cmd_list);
 382
 383         cd->command = command;
 384         cd->cmd_trb = cmd_trb;
 385         list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 386
 387         return 0;
 388 }
 389
 390 /*
 391  * Cancel the command which has issue.
 392  *
 393  * Some commands may hang due to waiting for acknowledgement from
 394  * usb device. It is outside of the xHC's ability to control and
 395  * will cause the command ring is blocked. When it occurs software
 396  * should intervene to recover the command ring.
 397  * See Section 4.6.1.1 and 4.6.1.2
 398  */
 399 int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 400                 union xhci_trb *cmd_trb)
 401 {
 402         int retval = 0;
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&xhci->lock, flags);
 406
 407         if (xhci->xhc_state & XHCI_STATE_DYING) {
 408                 xhci_warn(xhci, "Abort the command ring,"
 409                                 " but the xHCI is dead.\n");
 410                 retval = -ESHUTDOWN;
 411                 goto fail;
 412         }
 413
 414         /* queue the cmd desriptor to cancel_cmd_list */
 415         retval = xhci_queue_cd(xhci, command, cmd_trb);
 416         if (retval) {
 417                 xhci_warn(xhci, "Queuing command descriptor failed.\n");
 418                 goto fail;
 419         }
 420
 421         /* abort command ring */
 422         retval = xhci_abort_cmd_ring(xhci);
 423         if (retval) {
 424                 xhci_err(xhci, "Abort command ring failed\n");
 425                 if (unlikely(retval == -ESHUTDOWN)) {
 426                         spin_unlock_irqrestore(&xhci->lock, flags);
 427                         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 428                         xhci_dbg(xhci, "xHCI host controller is dead.\n");
 429                         return retval;
 430                 }
 431         }
 432
 433 fail:
 434         spin_unlock_irqrestore(&xhci->lock, flags);
 435         return retval;
 436 }
 437
 438 void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 439                 unsigned int slot_id,
 440                 unsigned int ep_index,
 441                 unsigned int stream_id)
 442 {
 443         __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 444         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 445         unsigned int ep_state = ep->ep_state;
 446
 447         /* Don't ring the doorbell for this endpoint if there are pending
 448          * cancellations because we don't want to interrupt processing.
 449          * We don't want to restart any stream rings if there's a set dequeue
 450          * pointer command pending because the device can choose to start any
 451          * stream once the endpoint is on the HW schedule.
 452          * FIXME - check all the stream rings for pending cancellations.
 453          */
 454         if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 455             (ep_state & EP_HALTED))
 456                 return;
 457         xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 458         /* The CPU has better things to do at this point than wait for a
 459          * write-posting flush.  It'll get there soon enough.
 460          */
 461 }
 462
 463 /* Ring the doorbell for any rings with pending URBs */
 464 static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 465                 unsigned int slot_id,
 466                 unsigned int ep_index)
 467 {
 468         unsigned int stream_id;
 469         struct xhci_virt_ep *ep;
 470
 471         ep = &xhci->devs[slot_id]->eps[ep_index];
 472
 473         /* A ring has pending URBs if its TD list is not empty */
 474         if (!(ep->ep_state & EP_HAS_STREAMS)) {
 475                 if (ep->ring && !(list_empty(&ep->ring->td_list)))
 476                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 477                 return;
 478         }
 479
 480         for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 481                         stream_id++) {
 482                 struct xhci_stream_info *stream_info = ep->stream_info;
 483                 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 484                         xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 485                                                 stream_id);
 486         }
 487 }
 488
 489 /*
 490  * Find the segment that trb is in.  Start searching in start_seg.
 491  * If we must move past a segment that has a link TRB with a toggle cycle state
 492  * bit set, then we will toggle the value pointed at by cycle_state.
 493  */
 494 static struct xhci_segment *find_trb_seg(
 495                 struct xhci_segment *start_seg,
 496                 union xhci_trb  *trb, int *cycle_state)
 497 {
 498         struct xhci_segment *cur_seg = start_seg;
 499         struct xhci_generic_trb *generic_trb;
 500
 501         while (cur_seg->trbs > trb ||
 502                         &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 503                 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 504                 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 505                         *cycle_state ^= 0x1;
 506                 cur_seg = cur_seg->next;
 507                 if (cur_seg == start_seg)
 508                         /* Looped over the entire list.  Oops! */
 509                         return NULL;
 510         }
 511         return cur_seg;
 512 }
 513
 514
 515 static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 516                 unsigned int slot_id, unsigned int ep_index,
 517                 unsigned int stream_id)
 518 {
 519         struct xhci_virt_ep *ep;
 520
 521         ep = &xhci->devs[slot_id]->eps[ep_index];
 522         /* Common case: no streams */
 523         if (!(ep->ep_state & EP_HAS_STREAMS))
 524                 return ep->ring;
 525
 526         if (stream_id == 0) {
 527                 xhci_warn(xhci,
 528                                 "WARN: Slot ID %u, ep index %u has streams, "
 529                                 "but URB has no stream ID.\n",
 530                                 slot_id, ep_index);
 531                 return NULL;
 532         }
 533
 534         if (stream_id < ep->stream_info->num_streams)
 535                 return ep->stream_info->stream_rings[stream_id];
 536
 537         xhci_warn(xhci,
 538                         "WARN: Slot ID %u, ep index %u has "
 539                         "stream IDs 1 to %u allocated, "
 540                         "but stream ID %u is requested.\n",
 541                         slot_id, ep_index,
 542                         ep->stream_info->num_streams - 1,
 543                         stream_id);
 544         return NULL;
 545 }
 546
 547 /* Get the right ring for the given URB.
 548  * If the endpoint supports streams, boundary check the URB's stream ID.
 549  * If the endpoint doesn't support streams, return the singular endpoint ring.
 550  */
 551 static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 552                 struct urb *urb)
 553 {
 554         return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 555                 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 556 }
 557
 558 /*
 559  * Move the xHC's endpoint ring dequeue pointer past cur_td.
 560  * Record the new state of the xHC's endpoint ring dequeue segment,
 561  * dequeue pointer, and new consumer cycle state in state.
 562  * Update our internal representation of the ring's dequeue pointer.
 563  *
 564  * We do this in three jumps:
 565  *  - First we update our new ring state to be the same as when the xHC stopped.
 566  *  - Then we traverse the ring to find the segment that contains
 567  *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 568  *    any link TRBs with the toggle cycle bit set.
 569  *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 570  *    if we've moved it past a link TRB with the toggle cycle bit set.
 571  *
 572  * Some of the uses of xhci_generic_trb are grotty, but if they're done
 573  * with correct __le32 accesses they should work fine.  Only users of this are
 574  * in here.
 575  */
 576 void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 577                 unsigned int slot_id, unsigned int ep_index,
 578                 unsigned int stream_id, struct xhci_td *cur_td,
 579                 struct xhci_dequeue_state *state)
 580 {
 581         struct xhci_virt_device *dev = xhci->devs[slot_id];
 582         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 583         struct xhci_ring *ep_ring;
 584         struct xhci_segment *new_seg;
 585         union xhci_trb *new_deq;
 586         dma_addr_t addr;
 587         u64 hw_dequeue;
 588         bool cycle_found = false;
 589         bool td_last_trb_found = false;
 590
 591         ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 592                         ep_index, stream_id);
 593         if (!ep_ring) {
 594                 xhci_warn(xhci, "WARN can't find new dequeue state "
 595                                 "for invalid stream ID %u.\n",
 596                                 stream_id);
 597                 return;
 598         }
 599
 600         /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 601         xhci_dbg(xhci, "Finding endpoint context\n");
 602         /* 4.6.9 the css flag is written to the stream context for streams */
 603         if (ep->ep_state & EP_HAS_STREAMS) {
 604                 struct xhci_stream_ctx *ctx =
 605                         &ep->stream_info->stream_ctx_array[stream_id];
 606                 hw_dequeue = le64_to_cpu(ctx->stream_ring);
 607         } else {
 608                 struct xhci_ep_ctx *ep_ctx
 609                         = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 610                 hw_dequeue = le64_to_cpu(ep_ctx->deq);
 611         }
 612
 613         new_seg = ep_ring->deq_seg;
 614         new_deq = ep_ring->dequeue;
 615         state->new_cycle_state = hw_dequeue & 0x1;
 616
 617         /*
 618          * We want to find the pointer, segment and cycle state of the new trb
 619          * (the one after current TD's last_trb). We know the cycle state at
 620          * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
 621          * found.
 622          */
 623         do {
 624                 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
 625                     == (dma_addr_t)(hw_dequeue & ~0xf)) {
 626                         cycle_found = true;
 627                         if (td_last_trb_found)
 628                                 break;
 629                 }
 630                 if (new_deq == cur_td->last_trb)
 631                         td_last_trb_found = true;
 632
 633                 if (cycle_found &&
 634                     TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
 635                     new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
 636                         state->new_cycle_state ^= 0x1;
 637
 638                 next_trb(xhci, ep_ring, &new_seg, &new_deq);
 639
 640                 /* Search wrapped around, bail out */
 641                 if (new_deq == ep->ring->dequeue) {
 642                         xhci_err(xhci, "Error: Failed finding new dequeue state\n");
 643                         state->new_deq_seg = NULL;
 644                         state->new_deq_ptr = NULL;
 645                         return;
 646                 }
 647
 648         } while (!cycle_found || !td_last_trb_found);
 649
 650         state->new_deq_seg = new_seg;
 651         state->new_deq_ptr = new_deq;
 652
 653         /* Don't update the ring cycle state for the producer (us). */
 654         xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 655
 656         xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 657                         state->new_deq_seg);
 658         addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 659         xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 660                         (unsigned long long) addr);
 661 }
 662
 663 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
 664  * (The last TRB actually points to the ring enqueue pointer, which is not part
 665  * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 666  */
 667 static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 668                 struct xhci_td *cur_td, bool flip_cycle)
 669 {
 670         struct xhci_segment *cur_seg;
 671         union xhci_trb *cur_trb;
 672
 673         for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 674                         true;
 675                         next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 676                 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 677                         /* Unchain any chained Link TRBs, but
 678                          * leave the pointers intact.
 679                          */
 680                         cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 681                         /* Flip the cycle bit (link TRBs can't be the first
 682                          * or last TRB).
 683                          */
 684                         if (flip_cycle)
 685                                 cur_trb->generic.field[3] ^=
 686                                         cpu_to_le32(TRB_CYCLE);
 687                         xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 688                         xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 689                                         "in seg %p (0x%llx dma)\n",
 690                                         cur_trb,
 691                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 692                                         cur_seg,
 693                                         (unsigned long long)cur_seg->dma);
 694                 } else {
 695                         cur_trb->generic.field[0] = 0;
 696                         cur_trb->generic.field[1] = 0;
 697                         cur_trb->generic.field[2] = 0;
 698                         /* Preserve only the cycle bit of this TRB */
 699                         cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 700                         /* Flip the cycle bit except on the first or last TRB */
 701                         if (flip_cycle && cur_trb != cur_td->first_trb &&
 702                                         cur_trb != cur_td->last_trb)
 703                                 cur_trb->generic.field[3] ^=
 704                                         cpu_to_le32(TRB_CYCLE);
 705                         cur_trb->generic.field[3] |= cpu_to_le32(
 706                                 TRB_TYPE(TRB_TR_NOOP));
 707                         xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
 708                                         "in seg %p (0x%llx dma)\n",
 709                                         cur_trb,
 710                                         (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 711                                         cur_seg,
 712                                         (unsigned long long)cur_seg->dma);
 713                 }
 714                 if (cur_trb == cur_td->last_trb)
 715                         break;
 716         }
 717 }
 718
 719 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 720                 unsigned int ep_index, unsigned int stream_id,
 721                 struct xhci_segment *deq_seg,
 722                 union xhci_trb *deq_ptr, u32 cycle_state);
 723
 724 void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 725                 unsigned int slot_id, unsigned int ep_index,
 726                 unsigned int stream_id,
 727                 struct xhci_dequeue_state *deq_state)
 728 {
 729         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 730
 731         xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 732                         "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 733                         deq_state->new_deq_seg,
 734                         (unsigned long long)deq_state->new_deq_seg->dma,
 735                         deq_state->new_deq_ptr,
 736                         (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 737                         deq_state->new_cycle_state);
 738         queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 739                         deq_state->new_deq_seg,
 740                         deq_state->new_deq_ptr,
 741                         (u32) deq_state->new_cycle_state);
 742         /* Stop the TD queueing code from ringing the doorbell until
 743          * this command completes.  The HC won't set the dequeue pointer
 744          * if the ring is running, and ringing the doorbell starts the
 745          * ring running.
 746          */
 747         ep->ep_state |= SET_DEQ_PENDING;
 748 }
 749
 750 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 751                 struct xhci_virt_ep *ep)
 752 {
 753         ep->ep_state &= ~EP_HALT_PENDING;
 754         /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 755          * timer is running on another CPU, we don't decrement stop_cmds_pending
 756          * (since we didn't successfully stop the watchdog timer).
 757          */
 758         if (del_timer(&ep->stop_cmd_timer))
 759                 ep->stop_cmds_pending--;
 760 }
 761
 762 /* Must be called with xhci->lock held in interrupt context */
 763 static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 764                 struct xhci_td *cur_td, int status, char *adjective)
 765 {
 766         struct usb_hcd *hcd;
 767         struct urb      *urb;
 768         struct urb_priv *urb_priv;
 769
 770         urb = cur_td->urb;
 771         urb_priv = urb->hcpriv;
 772         urb_priv->td_cnt++;
 773         hcd = bus_to_hcd(urb->dev->bus);
 774
 775         /* Only giveback urb when this is the last td in urb */
 776         if (urb_priv->td_cnt == urb_priv->length) {
 777                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 778                         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 779                         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 780                                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
 781                                         usb_amd_quirk_pll_enable();
 782                         }
 783                 }
 784                 usb_hcd_unlink_urb_from_ep(hcd, urb);
 785
 786                 spin_unlock(&xhci->lock);
 787                 usb_hcd_giveback_urb(hcd, urb, status);
 788                 xhci_urb_free_priv(xhci, urb_priv);
 789                 spin_lock(&xhci->lock);
 790         }
 791 }
 792
 793 /*
 794  * When we get a command completion for a Stop Endpoint Command, we need to
 795  * unlink any cancelled TDs from the ring.  There are two ways to do that:
 796  *
 797  *  1. If the HW was in the middle of processing the TD that needs to be
 798  *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 799  *     in the TD with a Set Dequeue Pointer Command.
 800  *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 801  *     bit cleared) so that the HW will skip over them.
 802  */
 803 static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 804                 union xhci_trb *trb, struct xhci_event_cmd *event)
 805 {
 806         unsigned int slot_id;
 807         unsigned int ep_index;
 808         struct xhci_virt_device *virt_dev;
 809         struct xhci_ring *ep_ring;
 810         struct xhci_virt_ep *ep;
 811         struct list_head *entry;
 812         struct xhci_td *cur_td = NULL;
 813         struct xhci_td *last_unlinked_td;
 814
 815         struct xhci_dequeue_state deq_state;
 816
 817         if (unlikely(TRB_TO_SUSPEND_PORT(
 818                              le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 819                 slot_id = TRB_TO_SLOT_ID(
 820                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 821                 virt_dev = xhci->devs[slot_id];
 822                 if (virt_dev)
 823                         handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 824                                 event);
 825                 else
 826                         xhci_warn(xhci, "Stop endpoint command "
 827                                 "completion for disabled slot %u\n",
 828                                 slot_id);
 829                 return;
 830         }
 831
 832         memset(&deq_state, 0, sizeof(deq_state));
 833         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 834         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 835         ep = &xhci->devs[slot_id]->eps[ep_index];
 836
 837         if (list_empty(&ep->cancelled_td_list)) {
 838                 xhci_stop_watchdog_timer_in_irq(xhci, ep);
 839                 ep->stopped_td = NULL;
 840                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 841                 return;
 842         }
 843
 844         /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 845          * We have the xHCI lock, so nothing can modify this list until we drop
 846          * it.  We're also in the event handler, so we can't get re-interrupted
 847          * if another Stop Endpoint command completes
 848          */
 849         list_for_each(entry, &ep->cancelled_td_list) {
 850                 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 851                 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
 852                                 cur_td->first_trb,
 853                                 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
 854                 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 855                 if (!ep_ring) {
 856                         /* This shouldn't happen unless a driver is mucking
 857                          * with the stream ID after submission.  This will
 858                          * leave the TD on the hardware ring, and the hardware
 859                          * will try to execute it, and may access a buffer
 860                          * that has already been freed.  In the best case, the
 861                          * hardware will execute it, and the event handler will
 862                          * ignore the completion event for that TD, since it was
 863                          * removed from the td_list for that endpoint.  In
 864                          * short, don't muck with the stream ID after
 865                          * submission.
 866                          */
 867                         xhci_warn(xhci, "WARN Cancelled URB %p "
 868                                         "has invalid stream ID %u.\n",
 869                                         cur_td->urb,
 870                                         cur_td->urb->stream_id);
 871                         goto remove_finished_td;
 872                 }
 873                 /*
 874                  * If we stopped on the TD we need to cancel, then we have to
 875                  * move the xHC endpoint ring dequeue pointer past this TD.
 876                  */
 877                 if (cur_td == ep->stopped_td)
 878                         xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 879                                         cur_td->urb->stream_id,
 880                                         cur_td, &deq_state);
 881                 else
 882                         td_to_noop(xhci, ep_ring, cur_td, false);
 883 remove_finished_td:
 884                 /*
 885                  * The event handler won't see a completion for this TD anymore,
 886                  * so remove it from the endpoint ring's TD list.  Keep it in
 887                  * the cancelled TD list for URB completion later.
 888                  */
 889                 list_del_init(&cur_td->td_list);
 890         }
 891         last_unlinked_td = cur_td;
 892         xhci_stop_watchdog_timer_in_irq(xhci, ep);
 893
 894         /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 895         if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 896                 xhci_queue_new_dequeue_state(xhci,
 897                                 slot_id, ep_index,
 898                                 ep->stopped_td->urb->stream_id,
 899                                 &deq_state);
 900                 xhci_ring_cmd_db(xhci);
 901         } else {
 902                 /* Otherwise ring the doorbell(s) to restart queued transfers */
 903                 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 904         }
 905
 906         /* Clear stopped_td if endpoint is not halted */
 907         if (!(ep->ep_state & EP_HALTED))
 908                 ep->stopped_td = NULL;
 909
 910         /*
 911          * Drop the lock and complete the URBs in the cancelled TD list.
 912          * New TDs to be cancelled might be added to the end of the list before
 913          * we can complete all the URBs for the TDs we already unlinked.
 914          * So stop when we've completed the URB for the last TD we unlinked.
 915          */
 916         do {
 917                 cur_td = list_entry(ep->cancelled_td_list.next,
 918                                 struct xhci_td, cancelled_td_list);
 919                 list_del_init(&cur_td->cancelled_td_list);
 920
 921                 /* Clean up the cancelled URB */
 922                 /* Doesn't matter what we pass for status, since the core will
 923                  * just overwrite it (because the URB has been unlinked).
 924                  */
 925                 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 926
 927                 /* Stop processing the cancelled list if the watchdog timer is
 928                  * running.
 929                  */
 930                 if (xhci->xhc_state & XHCI_STATE_DYING)
 931                         return;
 932         } while (cur_td != last_unlinked_td);
 933
 934         /* Return to the event handler with xhci->lock re-acquired */
 935 }
 936
 937 /* Watchdog timer function for when a stop endpoint command fails to complete.
 938  * In this case, we assume the host controller is broken or dying or dead.  The
 939  * host may still be completing some other events, so we have to be careful to
 940  * let the event ring handler and the URB dequeueing/enqueueing functions know
 941  * through xhci->state.
 942  *
 943  * The timer may also fire if the host takes a very long time to respond to the
 944  * command, and the stop endpoint command completion handler cannot delete the
 945  * timer before the timer function is called.  Another endpoint cancellation may
 946  * sneak in before the timer function can grab the lock, and that may queue
 947  * another stop endpoint command and add the timer back.  So we cannot use a
 948  * simple flag to say whether there is a pending stop endpoint command for a
 949  * particular endpoint.
 950  *
 951  * Instead we use a combination of that flag and a counter for the number of
 952  * pending stop endpoint commands.  If the timer is the tail end of the last
 953  * stop endpoint command, and the endpoint's command is still pending, we assume
 954  * the host is dying.
 955  */
 956 void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 957 {
 958         struct xhci_hcd *xhci;
 959         struct xhci_virt_ep *ep;
 960         struct xhci_virt_ep *temp_ep;
 961         struct xhci_ring *ring;
 962         struct xhci_td *cur_td;
 963         int ret, i, j;
 964         unsigned long flags;
 965
 966         ep = (struct xhci_virt_ep *) arg;
 967         xhci = ep->xhci;
 968
 969         spin_lock_irqsave(&xhci->lock, flags);
 970
 971         ep->stop_cmds_pending--;
 972         if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 973                 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 974                                 "exiting.\n");
 975                 spin_unlock_irqrestore(&xhci->lock, flags);
 976                 return;
 977         }
 978
 979         xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 980         xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 981         /* Oops, HC is dead or dying or at least not responding to the stop
 982          * endpoint command.
 983          */
 984         xhci->xhc_state |= XHCI_STATE_DYING;
 985         /* Disable interrupts from the host controller and start halting it */
 986         xhci_quiesce(xhci);
 987         spin_unlock_irqrestore(&xhci->lock, flags);
 988
 989         ret = xhci_halt(xhci);
 990
 991         spin_lock_irqsave(&xhci->lock, flags);
 992         if (ret < 0) {
 993                 /* This is bad; the host is not responding to commands and it's
 994                  * not allowing itself to be halted.  At least interrupts are
 995                  * disabled. If we call usb_hc_died(), it will attempt to
 996                  * disconnect all device drivers under this host.  Those
 997                  * disconnect() methods will wait for all URBs to be unlinked,
 998                  * so we must complete them.
 999                  */
1000                 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
1001                 xhci_warn(xhci, "Completing active URBs anyway.\n");
1002                 /* We could turn all TDs on the rings to no-ops.  This won't
1003                  * help if the host has cached part of the ring, and is slow if
1004                  * we want to preserve the cycle bit.  Skip it and hope the host
1005                  * doesn't touch the memory.
1006                  */
1007         }
1008         for (i = 0; i < MAX_HC_SLOTS; i++) {
1009                 if (!xhci->devs[i])
1010                         continue;
1011                 for (j = 0; j < 31; j++) {
1012                         temp_ep = &xhci->devs[i]->eps[j];
1013                         ring = temp_ep->ring;
1014                         if (!ring)
1015                                 continue;
1016                         xhci_dbg(xhci, "Killing URBs for slot ID %u, "
1017                                         "ep index %u\n", i, j);
1018                         while (!list_empty(&ring->td_list)) {
1019                                 cur_td = list_first_entry(&ring->td_list,
1020                                                 struct xhci_td,
1021                                                 td_list);
1022                                 list_del_init(&cur_td->td_list);
1023                                 if (!list_empty(&cur_td->cancelled_td_list))
1024                                         list_del_init(&cur_td->cancelled_td_list);
1025                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1026                                                 -ESHUTDOWN, "killed");
1027                         }
1028                         while (!list_empty(&temp_ep->cancelled_td_list)) {
1029                                 cur_td = list_first_entry(
1030                                                 &temp_ep->cancelled_td_list,
1031                                                 struct xhci_td,
1032                                                 cancelled_td_list);
1033                                 list_del_init(&cur_td->cancelled_td_list);
1034                                 xhci_giveback_urb_in_irq(xhci, cur_td,
1035                                                 -ESHUTDOWN, "killed");
1036                         }
1037                 }
1038         }
1039         spin_unlock_irqrestore(&xhci->lock, flags);
1040         xhci_dbg(xhci, "Calling usb_hc_died()\n");
1041         usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1042         xhci_dbg(xhci, "xHCI host controller is dead.\n");
1043 }
1044
1045 /*
1046  * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1047  * we need to clear the set deq pending flag in the endpoint ring state, so that
1048  * the TD queueing code can ring the doorbell again.  We also need to ring the
1049  * endpoint doorbell to restart the ring, but only if there aren't more
1050  * cancellations pending.
1051  */
1052 static void handle_set_deq_completion(struct xhci_hcd *xhci,
1053                 struct xhci_event_cmd *event,
1054                 union xhci_trb *trb)
1055 {
1056         unsigned int slot_id;
1057         unsigned int ep_index;
1058         unsigned int stream_id;
1059         struct xhci_ring *ep_ring;
1060         struct xhci_virt_device *dev;
1061         struct xhci_ep_ctx *ep_ctx;
1062         struct xhci_slot_ctx *slot_ctx;
1063
1064         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1065         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1066         stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1067         dev = xhci->devs[slot_id];
1068
1069         ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1070         if (!ep_ring) {
1071                 xhci_warn(xhci, "WARN Set TR deq ptr command for "
1072                                 "freed stream ID %u\n",
1073                                 stream_id);
1074                 /* XXX: Harmless??? */
1075                 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1076                 return;
1077         }
1078
1079         ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1080         slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1081
1082         if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1083                 unsigned int ep_state;
1084                 unsigned int slot_state;
1085
1086                 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1087                 case COMP_TRB_ERR:
1088                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1089                                         "of stream ID configuration\n");
1090                         break;
1091                 case COMP_CTX_STATE:
1092                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1093                                         "to incorrect slot or ep state.\n");
1094                         ep_state = le32_to_cpu(ep_ctx->ep_info);
1095                         ep_state &= EP_STATE_MASK;
1096                         slot_state = le32_to_cpu(slot_ctx->dev_state);
1097                         slot_state = GET_SLOT_STATE(slot_state);
1098                         xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1099                                         slot_state, ep_state);
1100                         break;
1101                 case COMP_EBADSLT:
1102                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1103                                         "slot %u was not enabled.\n", slot_id);
1104                         break;
1105                 default:
1106                         xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1107                                         "completion code of %u.\n",
1108                                   GET_COMP_CODE(le32_to_cpu(event->status)));
1109                         break;
1110                 }
1111                 /* OK what do we do now?  The endpoint state is hosed, and we
1112                  * should never get to this point if the synchronization between
1113                  * queueing, and endpoint state are correct.  This might happen
1114                  * if the device gets disconnected after we've finished
1115                  * cancelling URBs, which might not be an error...
1116                  */
1117         } else {
1118                 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1119                          le64_to_cpu(ep_ctx->deq));
1120                 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1121                                          dev->eps[ep_index].queued_deq_ptr) ==
1122                     (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1123                         /* Update the ring's dequeue segment and dequeue pointer
1124                          * to reflect the new position.
1125                          */
1126                         ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
1127                         ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
1128                 } else {
1129                         xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1130                                         "Ptr command & xHCI internal state.\n");
1131                         xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1132                                         dev->eps[ep_index].queued_deq_seg,
1133                                         dev->eps[ep_index].queued_deq_ptr);
1134                 }
1135         }
1136
1137         dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1138         dev->eps[ep_index].queued_deq_seg = NULL;
1139         dev->eps[ep_index].queued_deq_ptr = NULL;
1140         /* Restart any rings with pending URBs */
1141         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1142 }
1143
1144 static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1145                 struct xhci_event_cmd *event,
1146                 union xhci_trb *trb)
1147 {
1148         int slot_id;
1149         unsigned int ep_index;
1150
1151         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1152         ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1153         /* This command will only fail if the endpoint wasn't halted,
1154          * but we don't care.
1155          */
1156         xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1157                  GET_COMP_CODE(le32_to_cpu(event->status)));
1158
1159         /* HW with the reset endpoint quirk needs to have a configure endpoint
1160          * command complete before the endpoint can be used.  Queue that here
1161          * because the HW can't handle two commands being queued in a row.
1162          */
1163         if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1164                 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1165                 xhci_queue_configure_endpoint(xhci,
1166                                 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1167                                 false);
1168                 xhci_ring_cmd_db(xhci);
1169         } else {
1170                 /* Clear our internal halted state */
1171                 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1172         }
1173 }
1174
1175 /* Complete the command and detele it from the devcie's command queue.
1176  */
1177 static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1178                 struct xhci_command *command, u32 status)
1179 {
1180         command->status = status;
1181         list_del(&command->cmd_list);
1182         if (command->completion)
1183                 complete(command->completion);
1184         else
1185                 xhci_free_command(xhci, command);
1186 }
1187
1188
1189 /* Check to see if a command in the device's command queue matches this one.
1190  * Signal the completion or free the command, and return 1.  Return 0 if the
1191  * completed command isn't at the head of the command list.
1192  */
1193 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1194                 struct xhci_virt_device *virt_dev,
1195                 struct xhci_event_cmd *event)
1196 {
1197         struct xhci_command *command;
1198
1199         if (list_empty(&virt_dev->cmd_list))
1200                 return 0;
1201
1202         command = list_entry(virt_dev->cmd_list.next,
1203                         struct xhci_command, cmd_list);
1204         if (xhci->cmd_ring->dequeue != command->command_trb)
1205                 return 0;
1206
1207         xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1208                         GET_COMP_CODE(le32_to_cpu(event->status)));
1209         return 1;
1210 }
1211
1212 /*
1213  * Finding the command trb need to be cancelled and modifying it to
1214  * NO OP command. And if the command is in device's command wait
1215  * list, finishing and freeing it.
1216  *
1217  * If we can't find the command trb, we think it had already been
1218  * executed.
1219  */
1220 static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1221 {
1222         struct xhci_segment *cur_seg;
1223         union xhci_trb *cmd_trb;
1224         u32 cycle_state;
1225
1226         if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1227                 return;
1228
1229         /* find the current segment of command ring */
1230         cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1231                         xhci->cmd_ring->dequeue, &cycle_state);
1232
1233         if (!cur_seg) {
1234                 xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1235                                 xhci->cmd_ring->dequeue,
1236                                 (unsigned long long)
1237                                 xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1238                                         xhci->cmd_ring->dequeue));
1239                 xhci_debug_ring(xhci, xhci->cmd_ring);
1240                 xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1241                 return;
1242         }
1243
1244         /* find the command trb matched by cd from command ring */
1245         for (cmd_trb = xhci->cmd_ring->dequeue;
1246                         cmd_trb != xhci->cmd_ring->enqueue;
1247                         next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1248                 /* If the trb is link trb, continue */
1249                 if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1250                         continue;
1251
1252                 if (cur_cd->cmd_trb == cmd_trb) {
1253
1254                         /* If the command in device's command list, we should
1255                          * finish it and free the command structure.
1256                          */
1257                         if (cur_cd->command)
1258                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1259                                         cur_cd->command, COMP_CMD_STOP);
1260
1261                         /* get cycle state from the origin command trb */
1262                         cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1263                                 & TRB_CYCLE;
1264
1265                         /* modify the command trb to NO OP command */
1266                         cmd_trb->generic.field[0] = 0;
1267                         cmd_trb->generic.field[1] = 0;
1268                         cmd_trb->generic.field[2] = 0;
1269                         cmd_trb->generic.field[3] = cpu_to_le32(
1270                                         TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1271                         break;
1272                 }
1273         }
1274 }
1275
1276 static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1277 {
1278         struct xhci_cd *cur_cd, *next_cd;
1279
1280         if (list_empty(&xhci->cancel_cmd_list))
1281                 return;
1282
1283         list_for_each_entry_safe(cur_cd, next_cd,
1284                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1285                 xhci_cmd_to_noop(xhci, cur_cd);
1286                 list_del(&cur_cd->cancel_cmd_list);
1287                 kfree(cur_cd);
1288         }
1289 }
1290
1291 /*
1292  * traversing the cancel_cmd_list. If the command descriptor according
1293  * to cmd_trb is found, the function free it and return 1, otherwise
1294  * return 0.
1295  */
1296 static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1297                 union xhci_trb *cmd_trb)
1298 {
1299         struct xhci_cd *cur_cd, *next_cd;
1300
1301         if (list_empty(&xhci->cancel_cmd_list))
1302                 return 0;
1303
1304         list_for_each_entry_safe(cur_cd, next_cd,
1305                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1306                 if (cur_cd->cmd_trb == cmd_trb) {
1307                         if (cur_cd->command)
1308                                 xhci_complete_cmd_in_cmd_wait_list(xhci,
1309                                         cur_cd->command, COMP_CMD_STOP);
1310                         list_del(&cur_cd->cancel_cmd_list);
1311                         kfree(cur_cd);
1312                         return 1;
1313                 }
1314         }
1315
1316         return 0;
1317 }
1318
1319 /*
1320  * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1321  * trb pointed by the command ring dequeue pointer is the trb we want to
1322  * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1323  * traverse the cancel_cmd_list to trun the all of the commands according
1324  * to command descriptor to NO-OP trb.
1325  */
1326 static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1327                 int cmd_trb_comp_code)
1328 {
1329         int cur_trb_is_good = 0;
1330
1331         /* Searching the cmd trb pointed by the command ring dequeue
1332          * pointer in command descriptor list. If it is found, free it.
1333          */
1334         cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1335                         xhci->cmd_ring->dequeue);
1336
1337         if (cmd_trb_comp_code == COMP_CMD_ABORT)
1338                 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1339         else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1340                 /* traversing the cancel_cmd_list and canceling
1341                  * the command according to command descriptor
1342                  */
1343                 xhci_cancel_cmd_in_cd_list(xhci);
1344
1345                 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1346                 /*
1347                  * ring command ring doorbell again to restart the
1348                  * command ring
1349                  */
1350                 if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1351                         xhci_ring_cmd_db(xhci);
1352         }
1353         return cur_trb_is_good;
1354 }
1355
1356 static void handle_cmd_completion(struct xhci_hcd *xhci,
1357                 struct xhci_event_cmd *event)
1358 {
1359         int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1360         u64 cmd_dma;
1361         dma_addr_t cmd_dequeue_dma;
1362         struct xhci_input_control_ctx *ctrl_ctx;
1363         struct xhci_virt_device *virt_dev;
1364         unsigned int ep_index;
1365         struct xhci_ring *ep_ring;
1366         unsigned int ep_state;
1367
1368         cmd_dma = le64_to_cpu(event->cmd_trb);
1369         cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1370                         xhci->cmd_ring->dequeue);
1371         /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1372         if (cmd_dequeue_dma == 0) {
1373                 xhci->error_bitmask |= 1 << 4;
1374                 return;
1375         }
1376         /* Does the DMA address match our internal dequeue pointer address? */
1377         if (cmd_dma != (u64) cmd_dequeue_dma) {
1378                 xhci->error_bitmask |= 1 << 5;
1379                 return;
1380         }
1381
1382         if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1383                 (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1384                 /* If the return value is 0, we think the trb pointed by
1385                  * command ring dequeue pointer is a good trb. The good
1386                  * trb means we don't want to cancel the trb, but it have
1387                  * been stopped by host. So we should handle it normally.
1388                  * Otherwise, driver should invoke inc_deq() and return.
1389                  */
1390                 if (handle_stopped_cmd_ring(xhci,
1391                                 GET_COMP_CODE(le32_to_cpu(event->status)))) {
1392                         inc_deq(xhci, xhci->cmd_ring, false);
1393                         return;
1394                 }
1395         }
1396
1397         switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1398                 & TRB_TYPE_BITMASK) {
1399         case TRB_TYPE(TRB_ENABLE_SLOT):
1400                 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1401                         xhci->slot_id = slot_id;
1402                 else
1403                         xhci->slot_id = 0;
1404                 complete(&xhci->addr_dev);
1405                 break;
1406         case TRB_TYPE(TRB_DISABLE_SLOT):
1407                 if (xhci->devs[slot_id]) {
1408                         if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1409                                 /* Delete default control endpoint resources */
1410                                 xhci_free_device_endpoint_resources(xhci,
1411                                                 xhci->devs[slot_id], true);
1412                         xhci_free_virt_device(xhci, slot_id);
1413                 }
1414                 break;
1415         case TRB_TYPE(TRB_CONFIG_EP):
1416                 virt_dev = xhci->devs[slot_id];
1417                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1418                         break;
1419                 /*
1420                  * Configure endpoint commands can come from the USB core
1421                  * configuration or alt setting changes, or because the HW
1422                  * needed an extra configure endpoint command after a reset
1423                  * endpoint command or streams were being configured.
1424                  * If the command was for a halted endpoint, the xHCI driver
1425                  * is not waiting on the configure endpoint command.
1426                  */
1427                 ctrl_ctx = xhci_get_input_control_ctx(xhci,
1428                                 virt_dev->in_ctx);
1429                 /* Input ctx add_flags are the endpoint index plus one */
1430                 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1431                 /* A usb_set_interface() call directly after clearing a halted
1432                  * condition may race on this quirky hardware.  Not worth
1433                  * worrying about, since this is prototype hardware.  Not sure
1434                  * if this will work for streams, but streams support was
1435                  * untested on this prototype.
1436                  */
1437                 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1438                                 ep_index != (unsigned int) -1 &&
1439                     le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1440                     le32_to_cpu(ctrl_ctx->drop_flags)) {
1441                         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1442                         ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1443                         if (!(ep_state & EP_HALTED))
1444                                 goto bandwidth_change;
1445                         xhci_dbg(xhci, "Completed config ep cmd - "
1446                                         "last ep index = %d, state = %d\n",
1447                                         ep_index, ep_state);
1448                         /* Clear internal halted state and restart ring(s) */
1449                         xhci->devs[slot_id]->eps[ep_index].ep_state &=
1450                                 ~EP_HALTED;
1451                         ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1452                         break;
1453                 }
1454 bandwidth_change:
1455                 xhci_dbg(xhci, "Completed config ep cmd\n");
1456                 xhci->devs[slot_id]->cmd_status =
1457                         GET_COMP_CODE(le32_to_cpu(event->status));
1458                 complete(&xhci->devs[slot_id]->cmd_completion);
1459                 break;
1460         case TRB_TYPE(TRB_EVAL_CONTEXT):
1461                 virt_dev = xhci->devs[slot_id];
1462                 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1463                         break;
1464                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1465                 complete(&xhci->devs[slot_id]->cmd_completion);
1466                 break;
1467         case TRB_TYPE(TRB_ADDR_DEV):
1468                 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1469                 complete(&xhci->addr_dev);
1470                 break;
1471         case TRB_TYPE(TRB_STOP_RING):
1472                 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1473                 break;
1474         case TRB_TYPE(TRB_SET_DEQ):
1475                 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1476                 break;
1477         case TRB_TYPE(TRB_CMD_NOOP):
1478                 break;
1479         case TRB_TYPE(TRB_RESET_EP):
1480                 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1481                 break;
1482         case TRB_TYPE(TRB_RESET_DEV):
1483                 xhci_dbg(xhci, "Completed reset device command.\n");
1484                 slot_id = TRB_TO_SLOT_ID(
1485                         le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1486                 virt_dev = xhci->devs[slot_id];
1487                 if (virt_dev)
1488                         handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1489                 else
1490                         xhci_warn(xhci, "Reset device command completion "
1491                                         "for disabled slot %u\n", slot_id);
1492                 break;
1493         case TRB_TYPE(TRB_NEC_GET_FW):
1494                 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1495                         xhci->error_bitmask |= 1 << 6;
1496                         break;
1497                 }
1498                 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1499                          NEC_FW_MAJOR(le32_to_cpu(event->status)),
1500                          NEC_FW_MINOR(le32_to_cpu(event->status)));
1501                 break;
1502         default:
1503                 /* Skip over unknown commands on the event ring */
1504                 xhci->error_bitmask |= 1 << 6;
1505                 break;
1506         }
1507         inc_deq(xhci, xhci->cmd_ring, false);
1508 }
1509
1510 static void handle_vendor_event(struct xhci_hcd *xhci,
1511                 union xhci_trb *event)
1512 {
1513         u32 trb_type;
1514
1515         trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1516         xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1517         if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1518                 handle_cmd_completion(xhci, &event->event_cmd);
1519 }
1520
1521 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1522  * port registers -- USB 3.0 and USB 2.0).
1523  *
1524  * Returns a zero-based port number, which is suitable for indexing into each of
1525  * the split roothubs' port arrays and bus state arrays.
1526  * Add one to it in order to call xhci_find_slot_id_by_port.
1527  */
1528 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1529                 struct xhci_hcd *xhci, u32 port_id)
1530 {
1531         unsigned int i;
1532         unsigned int num_similar_speed_ports = 0;
1533
1534         /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1535          * and usb2_ports are 0-based indexes.  Count the number of similar
1536          * speed ports, up to 1 port before this port.
1537          */
1538         for (i = 0; i < (port_id - 1); i++) {
1539                 u8 port_speed = xhci->port_array[i];
1540
1541                 /*
1542                  * Skip ports that don't have known speeds, or have duplicate
1543                  * Extended Capabilities port speed entries.
1544                  */
1545                 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1546                         continue;
1547
1548                 /*
1549                  * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1550                  * 1.1 ports are under the USB 2.0 hub.  If the port speed
1551                  * matches the device speed, it's a similar speed port.
1552                  */
1553                 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1554                         num_similar_speed_ports++;
1555         }
1556         return num_similar_speed_ports;
1557 }
1558
1559 static void handle_port_status(struct xhci_hcd *xhci,
1560                 union xhci_trb *event)
1561 {
1562         struct usb_hcd *hcd;
1563         u32 port_id;
1564         u32 temp, temp1;
1565         int max_ports;
1566         int slot_id;
1567         unsigned int faked_port_index;
1568         u8 major_revision;
1569         struct xhci_bus_state *bus_state;
1570         __le32 __iomem **port_array;
1571         bool bogus_port_status = false;
1572
1573         /* Port status change events always have a successful completion code */
1574         if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1575                 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1576                 xhci->error_bitmask |= 1 << 8;
1577         }
1578         port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1579         xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1580
1581         max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1582         if ((port_id <= 0) || (port_id > max_ports)) {
1583                 xhci_warn(xhci, "Invalid port id %d\n", port_id);
1584                 bogus_port_status = true;
1585                 goto cleanup;
1586         }
1587
1588         /* Figure out which usb_hcd this port is attached to:
1589          * is it a USB 3.0 port or a USB 2.0/1.1 port?
1590          */
1591         major_revision = xhci->port_array[port_id - 1];
1592         if (major_revision == 0) {
1593                 xhci_warn(xhci, "Event for port %u not in "
1594                                 "Extended Capabilities, ignoring.\n",
1595                                 port_id);
1596                 bogus_port_status = true;
1597                 goto cleanup;
1598         }
1599         if (major_revision == DUPLICATE_ENTRY) {
1600                 xhci_warn(xhci, "Event for port %u duplicated in"
1601                                 "Extended Capabilities, ignoring.\n",
1602                                 port_id);
1603                 bogus_port_status = true;
1604                 goto cleanup;
1605         }
1606
1607         /*
1608          * Hardware port IDs reported by a Port Status Change Event include USB
1609          * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1610          * resume event, but we first need to translate the hardware port ID
1611          * into the index into the ports on the correct split roothub, and the
1612          * correct bus_state structure.
1613          */
1614         /* Find the right roothub. */
1615         hcd = xhci_to_hcd(xhci);
1616         if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1617                 hcd = xhci->shared_hcd;
1618         bus_state = &xhci->bus_state[hcd_index(hcd)];
1619         if (hcd->speed == HCD_USB3)
1620                 port_array = xhci->usb3_ports;
1621         else
1622                 port_array = xhci->usb2_ports;
1623         /* Find the faked port hub number */
1624         faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1625                         port_id);
1626
1627         temp = xhci_readl(xhci, port_array[faked_port_index]);
1628         if (hcd->state == HC_STATE_SUSPENDED) {
1629                 xhci_dbg(xhci, "resume root hub\n");
1630                 usb_hcd_resume_root_hub(hcd);
1631         }
1632
1633         if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1634                 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1635
1636                 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1637                 if (!(temp1 & CMD_RUN)) {
1638                         xhci_warn(xhci, "xHC is not running.\n");
1639                         goto cleanup;
1640                 }
1641
1642                 if (DEV_SUPERSPEED(temp)) {
1643                         xhci_dbg(xhci, "resume SS port %d\n", port_id);
1644                         xhci_set_link_state(xhci, port_array, faked_port_index,
1645                                                 XDEV_U0);
1646                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1647                                         faked_port_index + 1);
1648                         if (!slot_id) {
1649                                 xhci_dbg(xhci, "slot_id is zero\n");
1650                                 goto cleanup;
1651                         }
1652                         xhci_ring_device(xhci, slot_id);
1653                         xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1654                         /* Clear PORT_PLC */
1655                         xhci_test_and_clear_bit(xhci, port_array,
1656                                                 faked_port_index, PORT_PLC);
1657                 } else {
1658                         xhci_dbg(xhci, "resume HS port %d\n", port_id);
1659                         bus_state->resume_done[faked_port_index] = jiffies +
1660                                 msecs_to_jiffies(20);
1661                         mod_timer(&hcd->rh_timer,
1662                                   bus_state->resume_done[faked_port_index]);
1663                         /* Do the rest in GetPortStatus */
1664                 }
1665         }
1666
1667         if (hcd->speed != HCD_USB3)
1668                 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1669                                         PORT_PLC);
1670
1671 cleanup:
1672         /* Update event ring dequeue pointer before dropping the lock */
1673         inc_deq(xhci, xhci->event_ring, true);
1674
1675         /* Don't make the USB core poll the roothub if we got a bad port status
1676          * change event.  Besides, at that point we can't tell which roothub
1677          * (USB 2.0 or USB 3.0) to kick.
1678          */
1679         if (bogus_port_status)
1680                 return;
1681
1682         /*
1683          * xHCI port-status-change events occur when the "or" of all the
1684          * status-change bits in the portsc register changes from 0 to 1.
1685          * New status changes won't cause an event if any other change
1686          * bits are still set.  When an event occurs, switch over to
1687          * polling to avoid losing status changes.
1688          */
1689         xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1690         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1691         spin_unlock(&xhci->lock);
1692         /* Pass this up to the core */
1693         usb_hcd_poll_rh_status(hcd);
1694         spin_lock(&xhci->lock);
1695 }
1696
1697 /*
1698  * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1699  * at end_trb, which may be in another segment.  If the suspect DMA address is a
1700  * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1701  * returns 0.
1702  */
1703 struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1704                 union xhci_trb  *start_trb,
1705                 union xhci_trb  *end_trb,
1706                 dma_addr_t      suspect_dma)
1707 {
1708         dma_addr_t start_dma;
1709         dma_addr_t end_seg_dma;
1710         dma_addr_t end_trb_dma;
1711         struct xhci_segment *cur_seg;
1712
1713         start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1714         cur_seg = start_seg;
1715
1716         do {
1717                 if (start_dma == 0)
1718                         return NULL;
1719                 /* We may get an event for a Link TRB in the middle of a TD */
1720                 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1721                                 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1722                 /* If the end TRB isn't in this segment, this is set to 0 */
1723                 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1724
1725                 if (end_trb_dma > 0) {
1726                         /* The end TRB is in this segment, so suspect should be here */
1727                         if (start_dma <= end_trb_dma) {
1728                                 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1729                                         return cur_seg;
1730                         } else {
1731                                 /* Case for one segment with
1732                                  * a TD wrapped around to the top
1733                                  */
1734                                 if ((suspect_dma >= start_dma &&
1735                                                         suspect_dma <= end_seg_dma) ||
1736                                                 (suspect_dma >= cur_seg->dma &&
1737                                                  suspect_dma <= end_trb_dma))
1738                                         return cur_seg;
1739                         }
1740                         return NULL;
1741                 } else {
1742                         /* Might still be somewhere in this segment */
1743                         if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1744                                 return cur_seg;
1745                 }
1746                 cur_seg = cur_seg->next;
1747                 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1748         } while (cur_seg != start_seg);
1749
1750         return NULL;
1751 }
1752
1753 static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1754                 unsigned int slot_id, unsigned int ep_index,
1755                 unsigned int stream_id,
1756                 struct xhci_td *td, union xhci_trb *event_trb)
1757 {
1758         struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1759         ep->ep_state |= EP_HALTED;
1760         ep->stopped_td = td;
1761         ep->stopped_stream = stream_id;
1762
1763         xhci_queue_reset_ep(xhci, slot_id, ep_index);
1764         xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1765
1766         ep->stopped_td = NULL;
1767         ep->stopped_stream = 0;
1768
1769         xhci_ring_cmd_db(xhci);
1770 }
1771
1772 /* Check if an error has halted the endpoint ring.  The class driver will
1773  * cleanup the halt for a non-default control endpoint if we indicate a stall.
1774  * However, a babble and other errors also halt the endpoint ring, and the class
1775  * driver won't clear the halt in that case, so we need to issue a Set Transfer
1776  * Ring Dequeue Pointer command manually.
1777  */
1778 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1779                 struct xhci_ep_ctx *ep_ctx,
1780                 unsigned int trb_comp_code)
1781 {
1782         /* TRB completion codes that may require a manual halt cleanup */
1783         if (trb_comp_code == COMP_TX_ERR ||
1784                         trb_comp_code == COMP_BABBLE ||
1785                         trb_comp_code == COMP_SPLIT_ERR)
1786                 /* The 0.96 spec says a babbling control endpoint
1787                  * is not halted. The 0.96 spec says it is.  Some HW
1788                  * claims to be 0.95 compliant, but it halts the control
1789                  * endpoint anyway.  Check if a babble halted the
1790                  * endpoint.
1791                  */
1792                 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1793                     cpu_to_le32(EP_STATE_HALTED))
1794                         return 1;
1795
1796         return 0;
1797 }
1798
1799 int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1800 {
1801         if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1802                 /* Vendor defined "informational" completion code,
1803                  * treat as not-an-error.
1804                  */
1805                 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1806                                 trb_comp_code);
1807                 xhci_dbg(xhci, "Treating code as success.\n");
1808                 return 1;
1809         }
1810         return 0;
1811 }
1812
1813 /*
1814  * Finish the td processing, remove the td from td list;
1815  * Return 1 if the urb can be given back.
1816  */
1817 static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1818         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1819         struct xhci_virt_ep *ep, int *status, bool skip)
1820 {
1821         struct xhci_virt_device *xdev;
1822         struct xhci_ring *ep_ring;
1823         unsigned int slot_id;
1824         int ep_index;
1825         struct urb *urb = NULL;
1826         struct xhci_ep_ctx *ep_ctx;
1827         int ret = 0;
1828         struct urb_priv *urb_priv;
1829         u32 trb_comp_code;
1830
1831         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1832         xdev = xhci->devs[slot_id];
1833         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1834         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1835         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1836         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1837
1838         if (skip)
1839                 goto td_cleanup;
1840
1841         if (trb_comp_code == COMP_STOP_INVAL ||
1842                         trb_comp_code == COMP_STOP) {
1843                 /* The Endpoint Stop Command completion will take care of any
1844                  * stopped TDs.  A stopped TD may be restarted, so don't update
1845                  * the ring dequeue pointer or take this TD off any lists yet.
1846                  */
1847                 ep->stopped_td = td;
1848                 return 0;
1849         } else {
1850                 if (trb_comp_code == COMP_STALL ||
1851                     xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1852                                                       trb_comp_code)) {
1853                         /* Issue a reset endpoint command to clear the host side
1854                          * halt, followed by a set dequeue command to move the
1855                          * dequeue pointer past the TD.
1856                          * The class driver clears the device side halt later.
1857                          */
1858                         xhci_cleanup_halted_endpoint(xhci,
1859                                         slot_id, ep_index, ep_ring->stream_id,
1860                                         td, event_trb);
1861                 } else {
1862                         /* Update ring dequeue pointer */
1863                         while (ep_ring->dequeue != td->last_trb)
1864                                 inc_deq(xhci, ep_ring, false);
1865                         inc_deq(xhci, ep_ring, false);
1866                 }
1867
1868 td_cleanup:
1869                 /* Clean up the endpoint's TD list */
1870                 urb = td->urb;
1871                 urb_priv = urb->hcpriv;
1872
1873                 /* Do one last check of the actual transfer length.
1874                  * If the host controller said we transferred more data than
1875                  * the buffer length, urb->actual_length will be a very big
1876                  * number (since it's unsigned).  Play it safe and say we didn't
1877                  * transfer anything.
1878                  */
1879                 if (urb->actual_length > urb->transfer_buffer_length) {
1880                         xhci_warn(xhci, "URB transfer length is wrong, "
1881                                         "xHC issue? req. len = %u, "
1882                                         "act. len = %u\n",
1883                                         urb->transfer_buffer_length,
1884                                         urb->actual_length);
1885                         urb->actual_length = 0;
1886                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1887                                 *status = -EREMOTEIO;
1888                         else
1889                                 *status = 0;
1890                 }
1891                 list_del_init(&td->td_list);
1892                 /* Was this TD slated to be cancelled but completed anyway? */
1893                 if (!list_empty(&td->cancelled_td_list))
1894                         list_del_init(&td->cancelled_td_list);
1895
1896                 urb_priv->td_cnt++;
1897                 /* Giveback the urb when all the tds are completed */
1898                 if (urb_priv->td_cnt == urb_priv->length) {
1899                         ret = 1;
1900                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1901                                 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1902                                 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1903                                         == 0) {
1904                                         if (xhci->quirks & XHCI_AMD_PLL_FIX)
1905                                                 usb_amd_quirk_pll_enable();
1906                                 }
1907                         }
1908                 }
1909         }
1910
1911         return ret;
1912 }
1913
1914 /*
1915  * Process control tds, update urb status and actual_length.
1916  */
1917 static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1918         union xhci_trb *event_trb, struct xhci_transfer_event *event,
1919         struct xhci_virt_ep *ep, int *status)
1920 {
1921         struct xhci_virt_device *xdev;
1922         struct xhci_ring *ep_ring;
1923         unsigned int slot_id;
1924         int ep_index;
1925         struct xhci_ep_ctx *ep_ctx;
1926         u32 trb_comp_code;
1927
1928         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1929         xdev = xhci->devs[slot_id];
1930         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1931         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1932         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1933         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1934
1935         xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1936         switch (trb_comp_code) {
1937         case COMP_SUCCESS:
1938                 if (event_trb == ep_ring->dequeue) {
1939                         xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1940                                         "without IOC set??\n");
1941                         *status = -ESHUTDOWN;
1942                 } else if (event_trb != td->last_trb) {
1943                         xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1944                                         "without IOC set??\n");
1945                         *status = -ESHUTDOWN;
1946                 } else {
1947                         *status = 0;
1948                 }
1949                 break;
1950         case COMP_SHORT_TX:
1951                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1952                         *status = -EREMOTEIO;
1953                 else
1954                         *status = 0;
1955                 break;
1956         case COMP_STOP_INVAL:
1957         case COMP_STOP:
1958                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1959         default:
1960                 if (!xhci_requires_manual_halt_cleanup(xhci,
1961                                         ep_ctx, trb_comp_code))
1962                         break;
1963                 xhci_dbg(xhci, "TRB error code %u, "
1964                                 "halted endpoint index = %u\n",
1965                                 trb_comp_code, ep_index);
1966                 /* else fall through */
1967         case COMP_STALL:
1968                 /* Did we transfer part of the data (middle) phase? */
1969                 if (event_trb != ep_ring->dequeue &&
1970                                 event_trb != td->last_trb)
1971                         td->urb->actual_length =
1972                                 td->urb->transfer_buffer_length -
1973                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1974                 else
1975                         td->urb->actual_length = 0;
1976
1977                 return finish_td(xhci, td, event_trb, event, ep, status, false);
1978         }
1979         /*
1980          * Did we transfer any data, despite the errors that might have
1981          * happened?  I.e. did we get past the setup stage?
1982          */
1983         if (event_trb != ep_ring->dequeue) {
1984                 /* The event was for the status stage */
1985                 if (event_trb == td->last_trb) {
1986                         if (td->urb_length_set) {
1987                                 /* Don't overwrite a previously set error code
1988                                  */
1989                                 if ((*status == -EINPROGRESS || *status == 0) &&
1990                                                 (td->urb->transfer_flags
1991                                                  & URB_SHORT_NOT_OK))
1992                                         /* Did we already see a short data
1993                                          * stage? */
1994                                         *status = -EREMOTEIO;
1995                         } else {
1996                                 td->urb->actual_length =
1997                                         td->urb->transfer_buffer_length;
1998                         }
1999                 } else {
2000                         /*
2001                          * Maybe the event was for the data stage? If so, update
2002                          * already the actual_length of the URB and flag it as
2003                          * set, so that it is not overwritten in the event for
2004                          * the last TRB.
2005                          */
2006                         td->urb_length_set = true;
2007                         td->urb->actual_length =
2008                                 td->urb->transfer_buffer_length -
2009                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2010                         xhci_dbg(xhci, "Waiting for status "
2011                                         "stage event\n");
2012                         return 0;
2013                 }
2014         }
2015
2016         return finish_td(xhci, td, event_trb, event, ep, status, false);
2017 }
2018
2019 /*
2020  * Process isochronous tds, update urb packet status and actual_length.
2021  */
2022 static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2023         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2024         struct xhci_virt_ep *ep, int *status)
2025 {
2026         struct xhci_ring *ep_ring;
2027         struct urb_priv *urb_priv;
2028         int idx;
2029         int len = 0;
2030         union xhci_trb *cur_trb;
2031         struct xhci_segment *cur_seg;
2032         struct usb_iso_packet_descriptor *frame;
2033         u32 trb_comp_code;
2034         bool skip_td = false;
2035
2036         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2037         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2038         urb_priv = td->urb->hcpriv;
2039         idx = urb_priv->td_cnt;
2040         frame = &td->urb->iso_frame_desc[idx];
2041
2042         /* handle completion code */
2043         switch (trb_comp_code) {
2044         case COMP_SUCCESS:
2045                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2046                         frame->status = 0;
2047                         break;
2048                 }
2049                 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2050                         trb_comp_code = COMP_SHORT_TX;
2051         case COMP_SHORT_TX:
2052                 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2053                                 -EREMOTEIO : 0;
2054                 break;
2055         case COMP_BW_OVER:
2056                 frame->status = -ECOMM;
2057                 skip_td = true;
2058                 break;
2059         case COMP_BUFF_OVER:
2060         case COMP_BABBLE:
2061                 frame->status = -EOVERFLOW;
2062                 skip_td = true;
2063                 break;
2064         case COMP_DEV_ERR:
2065         case COMP_STALL:
2066                 frame->status = -EPROTO;
2067                 skip_td = true;
2068                 break;
2069         case COMP_TX_ERR:
2070                 frame->status = -EPROTO;
2071                 if (event_trb != td->last_trb)
2072                         return 0;
2073                 skip_td = true;
2074                 break;
2075         case COMP_STOP:
2076         case COMP_STOP_INVAL:
2077                 break;
2078         default:
2079                 frame->status = -1;
2080                 break;
2081         }
2082
2083         if (trb_comp_code == COMP_SUCCESS || skip_td) {
2084                 frame->actual_length = frame->length;
2085                 td->urb->actual_length += frame->length;
2086         } else {
2087                 for (cur_trb = ep_ring->dequeue,
2088                      cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2089                      next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2090                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2091                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2092                                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2093                 }
2094                 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2095                         EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2096
2097                 if (trb_comp_code != COMP_STOP_INVAL) {
2098                         frame->actual_length = len;
2099                         td->urb->actual_length += len;
2100                 }
2101         }
2102
2103         return finish_td(xhci, td, event_trb, event, ep, status, false);
2104 }
2105
2106 static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2107                         struct xhci_transfer_event *event,
2108                         struct xhci_virt_ep *ep, int *status)
2109 {
2110         struct xhci_ring *ep_ring;
2111         struct urb_priv *urb_priv;
2112         struct usb_iso_packet_descriptor *frame;
2113         int idx;
2114
2115         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2116         urb_priv = td->urb->hcpriv;
2117         idx = urb_priv->td_cnt;
2118         frame = &td->urb->iso_frame_desc[idx];
2119
2120         /* The transfer is partly done. */
2121         frame->status = -EXDEV;
2122
2123         /* calc actual length */
2124         frame->actual_length = 0;
2125
2126         /* Update ring dequeue pointer */
2127         while (ep_ring->dequeue != td->last_trb)
2128                 inc_deq(xhci, ep_ring, false);
2129         inc_deq(xhci, ep_ring, false);
2130
2131         return finish_td(xhci, td, NULL, event, ep, status, true);
2132 }
2133
2134 /*
2135  * Process bulk and interrupt tds, update urb status and actual_length.
2136  */
2137 static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2138         union xhci_trb *event_trb, struct xhci_transfer_event *event,
2139         struct xhci_virt_ep *ep, int *status)
2140 {
2141         struct xhci_ring *ep_ring;
2142         union xhci_trb *cur_trb;
2143         struct xhci_segment *cur_seg;
2144         u32 trb_comp_code;
2145
2146         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2147         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2148
2149         switch (trb_comp_code) {
2150         case COMP_SUCCESS:
2151                 /* Double check that the HW transferred everything. */
2152                 if (event_trb != td->last_trb ||
2153                     EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2154                         xhci_warn(xhci, "WARN Successful completion "
2155                                         "on short TX\n");
2156                         if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2157                                 *status = -EREMOTEIO;
2158                         else
2159                                 *status = 0;
2160                         if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2161                                 trb_comp_code = COMP_SHORT_TX;
2162                 } else {
2163                         *status = 0;
2164                 }
2165                 break;
2166         case COMP_SHORT_TX:
2167                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2168                         *status = -EREMOTEIO;
2169                 else
2170                         *status = 0;
2171                 break;
2172         default:
2173                 /* Others already handled above */
2174                 break;
2175         }
2176         if (trb_comp_code == COMP_SHORT_TX)
2177                 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2178                                 "%d bytes untransferred\n",
2179                                 td->urb->ep->desc.bEndpointAddress,
2180                                 td->urb->transfer_buffer_length,
2181                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2182         /* Fast path - was this the last TRB in the TD for this URB? */
2183         if (event_trb == td->last_trb) {
2184                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2185                         td->urb->actual_length =
2186                                 td->urb->transfer_buffer_length -
2187                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2188                         if (td->urb->transfer_buffer_length <
2189                                         td->urb->actual_length) {
2190                                 xhci_warn(xhci, "HC gave bad length "
2191                                                 "of %d bytes left\n",
2192                                           EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2193                                 td->urb->actual_length = 0;
2194                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2195                                         *status = -EREMOTEIO;
2196                                 else
2197                                         *status = 0;
2198                         }
2199                         /* Don't overwrite a previously set error code */
2200                         if (*status == -EINPROGRESS) {
2201                                 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2202                                         *status = -EREMOTEIO;
2203                                 else
2204                                         *status = 0;
2205                         }
2206                 } else {
2207                         td->urb->actual_length =
2208                                 td->urb->transfer_buffer_length;
2209                         /* Ignore a short packet completion if the
2210                          * untransferred length was zero.
2211                          */
2212                         if (*status == -EREMOTEIO)
2213                                 *status = 0;
2214                 }
2215         } else {
2216                 /* Slow path - walk the list, starting from the dequeue
2217                  * pointer, to get the actual length transferred.
2218                  */
2219                 td->urb->actual_length = 0;
2220                 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2221                                 cur_trb != event_trb;
2222                                 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2223                         if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2224                             !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2225                                 td->urb->actual_length +=
2226                                         TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2227                 }
2228                 /* If the ring didn't stop on a Link or No-op TRB, add
2229                  * in the actual bytes transferred from the Normal TRB
2230                  */
2231                 if (trb_comp_code != COMP_STOP_INVAL)
2232                         td->urb->actual_length +=
2233                                 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2234                                 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2235         }
2236
2237         return finish_td(xhci, td, event_trb, event, ep, status, false);
2238 }
2239
2240 /*
2241  * If this function returns an error condition, it means it got a Transfer
2242  * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2243  * At this point, the host controller is probably hosed and should be reset.
2244  */
2245 static int handle_tx_event(struct xhci_hcd *xhci,
2246                 struct xhci_transfer_event *event)
2247 {
2248         struct xhci_virt_device *xdev;
2249         struct xhci_virt_ep *ep;
2250         struct xhci_ring *ep_ring;
2251         unsigned int slot_id;
2252         int ep_index;
2253         struct xhci_td *td = NULL;
2254         dma_addr_t event_dma;
2255         struct xhci_segment *event_seg;
2256         union xhci_trb *event_trb;
2257         struct urb *urb = NULL;
2258         int status = -EINPROGRESS;
2259         struct urb_priv *urb_priv;
2260         struct xhci_ep_ctx *ep_ctx;
2261         struct list_head *tmp;
2262         u32 trb_comp_code;
2263         int ret = 0;
2264         int td_num = 0;
2265         bool handling_skipped_tds = false;
2266
2267         slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2268         xdev = xhci->devs[slot_id];
2269         if (!xdev) {
2270                 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2271                 return -ENODEV;
2272         }
2273
2274         /* Endpoint ID is 1 based, our index is zero based */
2275         ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2276         ep = &xdev->eps[ep_index];
2277         ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2278         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2279         if (!ep_ring ||
2280             (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2281             EP_STATE_DISABLED) {
2282                 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2283                                 "or incorrect stream ring\n");
2284                 return -ENODEV;
2285         }
2286
2287         /* Count current td numbers if ep->skip is set */
2288         if (ep->skip) {
2289                 list_for_each(tmp, &ep_ring->td_list)
2290                         td_num++;
2291         }
2292
2293         event_dma = le64_to_cpu(event->buffer);
2294         trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2295         /* Look for common error cases */
2296         switch (trb_comp_code) {
2297         /* Skip codes that require special handling depending on
2298          * transfer type
2299          */
2300         case COMP_SUCCESS:
2301                 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2302                         break;
2303                 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2304                         trb_comp_code = COMP_SHORT_TX;
2305                 else
2306                         xhci_warn(xhci, "WARN Successful completion on short TX: "
2307                                         "needs XHCI_TRUST_TX_LENGTH quirk?\n");
2308         case COMP_SHORT_TX:
2309                 break;
2310         case COMP_STOP:
2311                 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2312                 break;
2313         case COMP_STOP_INVAL:
2314                 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2315                 break;
2316         case COMP_STALL:
2317                 xhci_dbg(xhci, "Stalled endpoint\n");
2318                 ep->ep_state |= EP_HALTED;
2319                 status = -EPIPE;
2320                 break;
2321         case COMP_TRB_ERR:
2322                 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2323                 status = -EILSEQ;
2324                 break;
2325         case COMP_SPLIT_ERR:
2326         case COMP_TX_ERR:
2327                 xhci_dbg(xhci, "Transfer error on endpoint\n");
2328                 status = -EPROTO;
2329                 break;
2330         case COMP_BABBLE:
2331                 xhci_dbg(xhci, "Babble error on endpoint\n");
2332                 status = -EOVERFLOW;
2333                 break;
2334         case COMP_DB_ERR:
2335                 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2336                 status = -ENOSR;
2337                 break;
2338         case COMP_BW_OVER:
2339                 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2340                 break;
2341         case COMP_BUFF_OVER:
2342                 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2343                 break;
2344         case COMP_UNDERRUN:
2345                 /*
2346                  * When the Isoch ring is empty, the xHC will generate
2347                  * a Ring Overrun Event for IN Isoch endpoint or Ring
2348                  * Underrun Event for OUT Isoch endpoint.
2349                  */
2350                 xhci_dbg(xhci, "underrun event on endpoint\n");
2351                 if (!list_empty(&ep_ring->td_list))
2352                         xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2353                                         "still with TDs queued?\n",
2354                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2355                                  ep_index);
2356                 goto cleanup;
2357         case COMP_OVERRUN:
2358                 xhci_dbg(xhci, "overrun event on endpoint\n");
2359                 if (!list_empty(&ep_ring->td_list))
2360                         xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2361                                         "still with TDs queued?\n",
2362                                  TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2363                                  ep_index);
2364                 goto cleanup;
2365         case COMP_DEV_ERR:
2366                 xhci_warn(xhci, "WARN: detect an incompatible device");
2367                 status = -EPROTO;
2368                 break;
2369         case COMP_MISSED_INT:
2370                 /*
2371                  * When encounter missed service error, one or more isoc tds
2372                  * may be missed by xHC.
2373                  * Set skip flag of the ep_ring; Complete the missed tds as
2374                  * short transfer when process the ep_ring next time.
2375                  */
2376                 ep->skip = true;
2377                 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2378                 goto cleanup;
2379         case COMP_PING_ERR:
2380                 ep->skip = true;
2381                 xhci_dbg(xhci, "No Ping response error, Skip one Isoc TD\n");
2382                 goto cleanup;
2383         default:
2384                 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2385                         status = 0;
2386                         break;
2387                 }
2388                 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2389                                 "busted\n");
2390                 goto cleanup;
2391         }
2392
2393         do {
2394                 /* This TRB should be in the TD at the head of this ring's
2395                  * TD list.
2396                  */
2397                 if (list_empty(&ep_ring->td_list)) {
2398                         /*
2399                          * A stopped endpoint may generate an extra completion
2400                          * event if the device was suspended.  Don't print
2401                          * warnings.
2402                          */
2403                         if (!(trb_comp_code == COMP_STOP ||
2404                                                 trb_comp_code == COMP_STOP_INVAL)) {
2405                                 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2406                                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2407                                                 ep_index);
2408                                 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2409                                                 (le32_to_cpu(event->flags) &
2410                                                  TRB_TYPE_BITMASK)>>10);
2411                                 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2412                         }
2413                         if (ep->skip) {
2414                                 ep->skip = false;
2415                                 xhci_dbg(xhci, "td_list is empty while skip "
2416                                                 "flag set. Clear skip flag.\n");
2417                         }
2418                         ret = 0;
2419                         goto cleanup;
2420                 }
2421
2422                 /* We've skipped all the TDs on the ep ring when ep->skip set */
2423                 if (ep->skip && td_num == 0) {
2424                         ep->skip = false;
2425                         xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2426                                                 "Clear skip flag.\n");
2427                         ret = 0;
2428                         goto cleanup;
2429                 }
2430
2431                 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2432                 if (ep->skip)
2433                         td_num--;
2434
2435                 /* Is this a TRB in the currently executing TD? */
2436                 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2437                                 td->last_trb, event_dma);
2438
2439                 /*
2440                  * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2441                  * is not in the current TD pointed by ep_ring->dequeue because
2442                  * that the hardware dequeue pointer still at the previous TRB
2443                  * of the current TD. The previous TRB maybe a Link TD or the
2444                  * last TRB of the previous TD. The command completion handle
2445                  * will take care the rest.
2446                  */
2447                 if (!event_seg && (trb_comp_code == COMP_STOP ||
2448                                    trb_comp_code == COMP_STOP_INVAL)) {
2449                         ret = 0;
2450                         goto cleanup;
2451                 }
2452
2453                 if (!event_seg) {
2454                         if (!ep->skip ||
2455                             !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2456                                 /* Some host controllers give a spurious
2457                                  * successful event after a short transfer.
2458                                  * Ignore it.
2459                                  */
2460                                 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2461                                                 ep_ring->last_td_was_short) {
2462                                         ep_ring->last_td_was_short = false;
2463                                         ret = 0;
2464                                         goto cleanup;
2465                                 }
2466                                 /* HC is busted, give up! */
2467                                 xhci_err(xhci,
2468                                         "ERROR Transfer event TRB DMA ptr not "
2469                                         "part of current TD\n");
2470                                 return -ESHUTDOWN;
2471                         }
2472
2473                         ret = skip_isoc_td(xhci, td, event, ep, &status);
2474                         goto cleanup;
2475                 }
2476                 if (trb_comp_code == COMP_SHORT_TX)
2477                         ep_ring->last_td_was_short = true;
2478                 else
2479                         ep_ring->last_td_was_short = false;
2480
2481                 if (ep->skip) {
2482                         xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2483                         ep->skip = false;
2484                 }
2485
2486                 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2487                                                 sizeof(*event_trb)];
2488                 /*
2489                  * No-op TRB should not trigger interrupts.
2490                  * If event_trb is a no-op TRB, it means the
2491                  * corresponding TD has been cancelled. Just ignore
2492                  * the TD.
2493                  */
2494                 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2495                         xhci_dbg(xhci,
2496                                  "event_trb is a no-op TRB. Skip it\n");
2497                         goto cleanup;
2498                 }
2499
2500                 /* Now update the urb's actual_length and give back to
2501                  * the core
2502                  */
2503                 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2504                         ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2505                                                  &status);
2506                 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2507                         ret = process_isoc_td(xhci, td, event_trb, event, ep,
2508                                                  &status);
2509                 else
2510                         ret = process_bulk_intr_td(xhci, td, event_trb, event,
2511                                                  ep, &status);
2512
2513 cleanup:
2514
2515
2516                 handling_skipped_tds = ep->skip &&
2517                         trb_comp_code != COMP_MISSED_INT &&
2518                         trb_comp_code != COMP_PING_ERR;
2519
2520                 /*
2521                  * Do not update event ring dequeue pointer if we're in a loop
2522                  * processing missed tds.
2523                  */
2524                 if (!handling_skipped_tds)
2525                         inc_deq(xhci, xhci->event_ring, true);
2526
2527                 if (ret) {
2528                         urb = td->urb;
2529                         urb_priv = urb->hcpriv;
2530
2531                         xhci_urb_free_priv(xhci, urb_priv);
2532
2533                         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2534                         if ((urb->actual_length != urb->transfer_buffer_length &&
2535                                                 (urb->transfer_flags &
2536                                                  URB_SHORT_NOT_OK)) ||
2537                                         (status != 0 &&
2538                                          !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2539                                 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2540                                                 "expected = %x, status = %d\n",
2541                                                 urb, urb->actual_length,
2542                                                 urb->transfer_buffer_length,
2543                                                 status);
2544                         spin_unlock(&xhci->lock);
2545                         /* EHCI, UHCI, and OHCI always unconditionally set the
2546                          * urb->status of an isochronous endpoint to 0.
2547                          */
2548                         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2549                                 status = 0;
2550                         usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2551                         spin_lock(&xhci->lock);
2552                 }
2553
2554         /*
2555          * If ep->skip is set, it means there are missed tds on the
2556          * endpoint ring need to take care of.
2557          * Process them as short transfer until reach the td pointed by
2558          * the event.
2559          */
2560         } while (handling_skipped_tds);
2561
2562         return 0;
2563 }
2564
2565 /*
2566  * This function handles all OS-owned events on the event ring.  It may drop
2567  * xhci->lock between event processing (e.g. to pass up port status changes).
2568  * Returns >0 for "possibly more events to process" (caller should call again),
2569  * otherwise 0 if done.  In future, <0 returns should indicate error code.
2570  */
2571 static int xhci_handle_event(struct xhci_hcd *xhci)
2572 {
2573         union xhci_trb *event;
2574         int update_ptrs = 1;
2575         int ret;
2576
2577         if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2578                 xhci->error_bitmask |= 1 << 1;
2579                 return 0;
2580         }
2581
2582         event = xhci->event_ring->dequeue;
2583         /* Does the HC or OS own the TRB? */
2584         if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2585             xhci->event_ring->cycle_state) {
2586                 xhci->error_bitmask |= 1 << 2;
2587                 return 0;
2588         }
2589
2590         /*
2591          * Barrier between reading the TRB_CYCLE (valid) flag above and any
2592          * speculative reads of the event's flags/data below.
2593          */
2594         rmb();
2595         /* FIXME: Handle more event types. */
2596         switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2597         case TRB_TYPE(TRB_COMPLETION):
2598                 handle_cmd_completion(xhci, &event->event_cmd);
2599                 break;
2600         case TRB_TYPE(TRB_PORT_STATUS):
2601                 handle_port_status(xhci, event);
2602                 update_ptrs = 0;
2603                 break;
2604         case TRB_TYPE(TRB_TRANSFER):
2605                 ret = handle_tx_event(xhci, &event->trans_event);
2606                 if (ret < 0)
2607                         xhci->error_bitmask |= 1 << 9;
2608                 else
2609                         update_ptrs = 0;
2610                 break;
2611         default:
2612                 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2613                     TRB_TYPE(48))
2614                         handle_vendor_event(xhci, event);
2615                 else
2616                         xhci->error_bitmask |= 1 << 3;
2617         }
2618         /* Any of the above functions may drop and re-acquire the lock, so check
2619          * to make sure a watchdog timer didn't mark the host as non-responsive.
2620          */
2621         if (xhci->xhc_state & XHCI_STATE_DYING) {
2622                 xhci_dbg(xhci, "xHCI host dying, returning from "
2623                                 "event handler.\n");
2624                 return 0;
2625         }
2626
2627         if (update_ptrs)
2628                 /* Update SW event ring dequeue pointer */
2629                 inc_deq(xhci, xhci->event_ring, true);
2630
2631         /* Are there more items on the event ring?  Caller will call us again to
2632          * check.
2633          */
2634         return 1;
2635 }
2636
2637 /*
2638  * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2639  * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2640  * indicators of an event TRB error, but we check the status *first* to be safe.
2641  */
2642 irqreturn_t xhci_irq(struct usb_hcd *hcd)
2643 {
2644         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2645         union xhci_trb *trb;
2646         union xhci_trb *event_ring_deq;
2647         irqreturn_t ret = IRQ_NONE;
2648         dma_addr_t deq;
2649         u64 temp_64;
2650         u32 status;
2651
2652         spin_lock(&xhci->lock);
2653         trb = xhci->event_ring->dequeue;
2654         /* Check if the xHC generated the interrupt, or the irq is shared */
2655         status = xhci_readl(xhci, &xhci->op_regs->status);
2656         if (status == 0xffffffff) {
2657                 ret = IRQ_HANDLED;
2658                 goto out;
2659         }
2660
2661         if (!(status & STS_EINT))
2662                 goto out;
2663
2664         if (status & STS_FATAL) {
2665                 xhci_warn(xhci, "WARNING: Host System Error\n");
2666                 xhci_halt(xhci);
2667                 ret = IRQ_HANDLED;
2668                 goto out;
2669         }
2670
2671         /*
2672          * Clear the op reg interrupt status first,
2673          * so we can receive interrupts from other MSI-X interrupters.
2674          * Write 1 to clear the interrupt status.
2675          */
2676         status |= STS_EINT;
2677         xhci_writel(xhci, status, &xhci->op_regs->status);
2678         /* FIXME when MSI-X is supported and there are multiple vectors */
2679         /* Clear the MSI-X event interrupt status */
2680
2681         if (hcd->irq != -1) {
2682                 u32 irq_pending;
2683                 /* Acknowledge the PCI interrupt */
2684                 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2685                 irq_pending |= IMAN_IP;
2686                 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2687         }
2688
2689         if (xhci->xhc_state & XHCI_STATE_DYING) {
2690                 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2691                                 "Shouldn't IRQs be disabled?\n");
2692                 /* Clear the event handler busy flag (RW1C);
2693                  * the event ring should be empty.
2694                  */
2695                 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2696                 xhci_write_64(xhci, temp_64 | ERST_EHB,
2697                                 &xhci->ir_set->erst_dequeue);
2698                 ret = IRQ_HANDLED;
2699                 goto out;
2700         }
2701
2702         event_ring_deq = xhci->event_ring->dequeue;
2703         /* FIXME this should be a delayed service routine
2704          * that clears the EHB.
2705          */
2706         while (xhci_handle_event(xhci) > 0) {}
2707
2708         temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2709         /* If necessary, update the HW's version of the event ring deq ptr. */
2710         if (event_ring_deq != xhci->event_ring->dequeue) {
2711                 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2712                                 xhci->event_ring->dequeue);
2713                 if (deq == 0)
2714                         xhci_warn(xhci, "WARN something wrong with SW event "
2715                                         "ring dequeue ptr.\n");
2716                 /* Update HC event ring dequeue pointer */
2717                 temp_64 &= ERST_PTR_MASK;
2718                 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2719         }
2720
2721         /* Clear the event handler busy flag (RW1C); event ring is empty. */
2722         temp_64 |= ERST_EHB;
2723         xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2724         ret = IRQ_HANDLED;
2725
2726 out:
2727         spin_unlock(&xhci->lock);
2728
2729         return ret;
2730 }
2731
2732 irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2733 {
2734         irqreturn_t ret;
2735         struct xhci_hcd *xhci;
2736
2737         xhci = hcd_to_xhci(hcd);
2738         set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
2739         if (xhci->shared_hcd)
2740                 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
2741
2742         ret = xhci_irq(hcd);
2743
2744         return ret;
2745 }
2746
2747 /****           Endpoint Ring Operations        ****/
2748
2749 /*
2750  * Generic function for queueing a TRB on a ring.
2751  * The caller must have checked to make sure there's room on the ring.
2752  *
2753  * @more_trbs_coming:   Will you enqueue more TRBs before calling
2754  *                      prepare_transfer()?
2755  */
2756 static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2757                 bool consumer, bool more_trbs_coming, bool isoc,
2758                 u32 field1, u32 field2, u32 field3, u32 field4)
2759 {
2760         struct xhci_generic_trb *trb;
2761
2762         trb = &ring->enqueue->generic;
2763         trb->field[0] = cpu_to_le32(field1);
2764         trb->field[1] = cpu_to_le32(field2);
2765         trb->field[2] = cpu_to_le32(field3);
2766         trb->field[3] = cpu_to_le32(field4);
2767         inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
2768 }
2769
2770 /*
2771  * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2772  * FIXME allocate segments if the ring is full.
2773  */
2774 static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2775                 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
2776 {
2777         /* Make sure the endpoint has been added to xHC schedule */
2778         switch (ep_state) {
2779         case EP_STATE_DISABLED:
2780                 /*
2781                  * USB core changed config/interfaces without notifying us,
2782                  * or hardware is reporting the wrong state.
2783                  */
2784                 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2785                 return -ENOENT;
2786         case EP_STATE_ERROR:
2787                 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2788                 /* FIXME event handling code for error needs to clear it */
2789                 /* XXX not sure if this should be -ENOENT or not */
2790                 return -EINVAL;
2791         case EP_STATE_HALTED:
2792                 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2793         case EP_STATE_STOPPED:
2794         case EP_STATE_RUNNING:
2795                 break;
2796         default:
2797                 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2798                 /*
2799                  * FIXME issue Configure Endpoint command to try to get the HC
2800                  * back into a known state.
2801                  */
2802                 return -EINVAL;
2803         }
2804         if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2805                 /* FIXME allocate more room */
2806                 xhci_err(xhci, "ERROR no room on ep ring\n");
2807                 return -ENOMEM;
2808         }
2809
2810         if (enqueue_is_link_trb(ep_ring)) {
2811                 struct xhci_ring *ring = ep_ring;
2812                 union xhci_trb *next;
2813
2814                 next = ring->enqueue;
2815
2816                 while (last_trb(xhci, ring, ring->enq_seg, next)) {
2817                         /* If we're not dealing with 0.95 hardware or isoc rings
2818                          * on AMD 0.96 host, clear the chain bit.
2819                          */
2820                         if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2821                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2822                                 next->link.control &= cpu_to_le32(~TRB_CHAIN);
2823                         else
2824                                 next->link.control |= cpu_to_le32(TRB_CHAIN);
2825
2826                         wmb();
2827                         next->link.control ^= cpu_to_le32(TRB_CYCLE);
2828
2829                         /* Toggle the cycle bit after the last ring segment. */
2830                         if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2831                                 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2832                                 if (!in_interrupt()) {
2833                                         xhci_dbg(xhci, "queue_trb: Toggle cycle "
2834                                                 "state for ring %p = %i\n",
2835                                                 ring, (unsigned int)ring->cycle_state);
2836                                 }
2837                         }
2838                         ring->enq_seg = ring->enq_seg->next;
2839                         ring->enqueue = ring->enq_seg->trbs;
2840                         next = ring->enqueue;
2841                 }
2842         }
2843
2844         return 0;
2845 }
2846
2847 static int prepare_transfer(struct xhci_hcd *xhci,
2848                 struct xhci_virt_device *xdev,
2849                 unsigned int ep_index,
2850                 unsigned int stream_id,
2851                 unsigned int num_trbs,
2852                 struct urb *urb,
2853                 unsigned int td_index,
2854                 bool isoc,
2855                 gfp_t mem_flags)
2856 {
2857         int ret;
2858         struct urb_priv *urb_priv;
2859         struct xhci_td  *td;
2860         struct xhci_ring *ep_ring;
2861         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2862
2863         ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2864         if (!ep_ring) {
2865                 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2866                                 stream_id);
2867                 return -EINVAL;
2868         }
2869
2870         ret = prepare_ring(xhci, ep_ring,
2871                            le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2872                            num_trbs, isoc, mem_flags);
2873         if (ret)
2874                 return ret;
2875
2876         urb_priv = urb->hcpriv;
2877         td = urb_priv->td[td_index];
2878
2879         INIT_LIST_HEAD(&td->td_list);
2880         INIT_LIST_HEAD(&td->cancelled_td_list);
2881
2882         if (td_index == 0) {
2883                 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2884                 if (unlikely(ret))
2885                         return ret;
2886         }
2887
2888         td->urb = urb;
2889         /* Add this TD to the tail of the endpoint ring's TD list */
2890         list_add_tail(&td->td_list, &ep_ring->td_list);
2891         td->start_seg = ep_ring->enq_seg;
2892         td->first_trb = ep_ring->enqueue;
2893
2894         urb_priv->td[td_index] = td;
2895
2896         return 0;
2897 }
2898
2899 static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2900 {
2901         int num_sgs, num_trbs, running_total, temp, i;
2902         struct scatterlist *sg;
2903
2904         sg = NULL;
2905         num_sgs = urb->num_mapped_sgs;
2906         temp = urb->transfer_buffer_length;
2907
2908         xhci_dbg(xhci, "count sg list trbs: \n");
2909         num_trbs = 0;
2910         for_each_sg(urb->sg, sg, num_sgs, i) {
2911                 unsigned int previous_total_trbs = num_trbs;
2912                 unsigned int len = sg_dma_len(sg);
2913
2914                 /* Scatter gather list entries may cross 64KB boundaries */
2915                 running_total = TRB_MAX_BUFF_SIZE -
2916                         (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2917                 running_total &= TRB_MAX_BUFF_SIZE - 1;
2918                 if (running_total != 0)
2919                         num_trbs++;
2920
2921                 /* How many more 64KB chunks to transfer, how many more TRBs? */
2922                 while (running_total < sg_dma_len(sg) && running_total < temp) {
2923                         num_trbs++;
2924                         running_total += TRB_MAX_BUFF_SIZE;
2925                 }
2926                 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2927                                 i, (unsigned long long)sg_dma_address(sg),
2928                                 len, len, num_trbs - previous_total_trbs);
2929
2930                 len = min_t(int, len, temp);
2931                 temp -= len;
2932                 if (temp == 0)
2933                         break;
2934         }
2935         xhci_dbg(xhci, "\n");
2936         if (!in_interrupt())
2937                 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2938                                 "num_trbs = %d\n",
2939                                 urb->ep->desc.bEndpointAddress,
2940                                 urb->transfer_buffer_length,
2941                                 num_trbs);
2942         return num_trbs;
2943 }
2944
2945 static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
2946 {
2947         if (num_trbs != 0)
2948                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
2949                                 "TRBs, %d left\n", __func__,
2950                                 urb->ep->desc.bEndpointAddress, num_trbs);
2951         if (running_total != urb->transfer_buffer_length)
2952                 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
2953                                 "queued %#x (%d), asked for %#x (%d)\n",
2954                                 __func__,
2955                                 urb->ep->desc.bEndpointAddress,
2956                                 running_total, running_total,
2957                                 urb->transfer_buffer_length,
2958                                 urb->transfer_buffer_length);
2959 }
2960
2961 static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
2962                 unsigned int ep_index, unsigned int stream_id, int start_cycle,
2963                 struct xhci_generic_trb *start_trb)
2964 {
2965         /*
2966          * Pass all the TRBs to the hardware at once and make sure this write
2967          * isn't reordered.
2968          */
2969         wmb();
2970         if (start_cycle)
2971                 start_trb->field[3] |= cpu_to_le32(start_cycle);
2972         else
2973                 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
2974         xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
2975 }
2976
2977 /*
2978  * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
2979  * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
2980  * (comprised of sg list entries) can take several service intervals to
2981  * transmit.
2982  */
2983 int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2984                 struct urb *urb, int slot_id, unsigned int ep_index)
2985 {
2986         struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2987                         xhci->devs[slot_id]->out_ctx, ep_index);
2988         int xhci_interval;
2989         int ep_interval;
2990
2991         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
2992         ep_interval = urb->interval;
2993         /* Convert to microframes */
2994         if (urb->dev->speed == USB_SPEED_LOW ||
2995                         urb->dev->speed == USB_SPEED_FULL)
2996                 ep_interval *= 8;
2997         /* FIXME change this to a warning and a suggestion to use the new API
2998          * to set the polling interval (once the API is added).
2999          */
3000         if (xhci_interval != ep_interval) {
3001                 if (printk_ratelimit())
3002                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3003                                         " (%d microframe%s) than xHCI "
3004                                         "(%d microframe%s)\n",
3005                                         ep_interval,
3006                                         ep_interval == 1 ? "" : "s",
3007                                         xhci_interval,
3008                                         xhci_interval == 1 ? "" : "s");
3009                 urb->interval = xhci_interval;
3010                 /* Convert back to frames for LS/FS devices */
3011                 if (urb->dev->speed == USB_SPEED_LOW ||
3012                                 urb->dev->speed == USB_SPEED_FULL)
3013                         urb->interval /= 8;
3014         }
3015         return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3016 }
3017
3018 /*
3019  * The TD size is the number of bytes remaining in the TD (including this TRB),
3020  * right shifted by 10.
3021  * It must fit in bits 21:17, so it can't be bigger than 31.
3022  */
3023 static u32 xhci_td_remainder(unsigned int remainder)
3024 {
3025         u32 max = (1 << (21 - 17 + 1)) - 1;
3026
3027         if ((remainder >> 10) >= max)
3028                 return max << 17;
3029         else
3030                 return (remainder >> 10) << 17;
3031 }
3032
3033 /*
3034  * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3035  * packets remaining in the TD (*not* including this TRB).
3036  *
3037  * Total TD packet count = total_packet_count =
3038  *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3039  *
3040  * Packets transferred up to and including this TRB = packets_transferred =
3041  *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3042  *
3043  * TD size = total_packet_count - packets_transferred
3044  *
3045  * It must fit in bits 21:17, so it can't be bigger than 31.
3046  * The last TRB in a TD must have the TD size set to zero.
3047  */
3048 static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3049                 unsigned int total_packet_count, struct urb *urb,
3050                 unsigned int num_trbs_left)
3051 {
3052         int packets_transferred;
3053
3054         /* One TRB with a zero-length data packet. */
3055         if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3056                 return 0;
3057
3058         /* All the TRB queueing functions don't count the current TRB in
3059          * running_total.
3060          */
3061         packets_transferred = (running_total + trb_buff_len) /
3062                 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3063
3064         if ((total_packet_count - packets_transferred) > 31)
3065                 return 31 << 17;
3066         return (total_packet_count - packets_transferred) << 17;
3067 }
3068
3069 static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3070                 struct urb *urb, int slot_id, unsigned int ep_index)
3071 {
3072         struct xhci_ring *ep_ring;
3073         unsigned int num_trbs;
3074         struct urb_priv *urb_priv;
3075         struct xhci_td *td;
3076         struct scatterlist *sg;
3077         int num_sgs;
3078         int trb_buff_len, this_sg_len, running_total;
3079         unsigned int total_packet_count;
3080         bool first_trb;
3081         u64 addr;
3082         bool more_trbs_coming;
3083
3084         struct xhci_generic_trb *start_trb;
3085         int start_cycle;
3086
3087         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3088         if (!ep_ring)
3089                 return -EINVAL;
3090
3091         num_trbs = count_sg_trbs_needed(xhci, urb);
3092         num_sgs = urb->num_mapped_sgs;
3093         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3094                         usb_endpoint_maxp(&urb->ep->desc));
3095
3096         trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3097                         ep_index, urb->stream_id,
3098                         num_trbs, urb, 0, false, mem_flags);
3099         if (trb_buff_len < 0)
3100                 return trb_buff_len;
3101
3102         urb_priv = urb->hcpriv;
3103         td = urb_priv->td[0];
3104
3105         /*
3106          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3107          * until we've finished creating all the other TRBs.  The ring's cycle
3108          * state may change as we enqueue the other TRBs, so save it too.
3109          */
3110         start_trb = &ep_ring->enqueue->generic;
3111         start_cycle = ep_ring->cycle_state;
3112
3113         running_total = 0;
3114         /*
3115          * How much data is in the first TRB?
3116          *
3117          * There are three forces at work for TRB buffer pointers and lengths:
3118          * 1. We don't want to walk off the end of this sg-list entry buffer.
3119          * 2. The transfer length that the driver requested may be smaller than
3120          *    the amount of memory allocated for this scatter-gather list.
3121          * 3. TRBs buffers can't cross 64KB boundaries.
3122          */
3123         sg = urb->sg;
3124         addr = (u64) sg_dma_address(sg);
3125         this_sg_len = sg_dma_len(sg);
3126         trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3127         trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3128         if (trb_buff_len > urb->transfer_buffer_length)
3129                 trb_buff_len = urb->transfer_buffer_length;
3130         xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
3131                         trb_buff_len);
3132
3133         first_trb = true;
3134         /* Queue the first TRB, even if it's zero-length */
3135         do {
3136                 u32 field = 0;
3137                 u32 length_field = 0;
3138                 u32 remainder = 0;
3139
3140                 /* Don't change the cycle bit of the first TRB until later */
3141                 if (first_trb) {
3142                         first_trb = false;
3143                         if (start_cycle == 0)
3144                                 field |= 0x1;
3145                 } else
3146                         field |= ep_ring->cycle_state;
3147
3148                 /* Chain all the TRBs together; clear the chain bit in the last
3149                  * TRB to indicate it's the last TRB in the chain.
3150                  */
3151                 if (num_trbs > 1) {
3152                         field |= TRB_CHAIN;
3153                 } else {
3154                         /* FIXME - add check for ZERO_PACKET flag before this */
3155                         td->last_trb = ep_ring->enqueue;
3156                         field |= TRB_IOC;
3157                 }
3158
3159                 /* Only set interrupt on short packet for IN endpoints */
3160                 if (usb_urb_dir_in(urb))
3161                         field |= TRB_ISP;
3162
3163                 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
3164                                 "64KB boundary at %#x, end dma = %#x\n",
3165                                 (unsigned int) addr, trb_buff_len, trb_buff_len,
3166                                 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3167                                 (unsigned int) addr + trb_buff_len);
3168                 if (TRB_MAX_BUFF_SIZE -
3169                                 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3170                         xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3171                         xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3172                                         (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3173                                         (unsigned int) addr + trb_buff_len);
3174                 }
3175
3176                 /* Set the TRB length, TD size, and interrupter fields. */
3177                 if (xhci->hci_version < 0x100) {
3178                         remainder = xhci_td_remainder(
3179                                         urb->transfer_buffer_length -
3180                                         running_total);
3181                 } else {
3182                         remainder = xhci_v1_0_td_remainder(running_total,
3183                                         trb_buff_len, total_packet_count, urb,
3184                                         num_trbs - 1);
3185                 }
3186                 length_field = TRB_LEN(trb_buff_len) |
3187                         remainder |
3188                         TRB_INTR_TARGET(0);
3189
3190                 if (num_trbs > 1)
3191                         more_trbs_coming = true;
3192                 else
3193                         more_trbs_coming = false;
3194                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3195                                 lower_32_bits(addr),
3196                                 upper_32_bits(addr),
3197                                 length_field,
3198                                 field | TRB_TYPE(TRB_NORMAL));
3199                 --num_trbs;
3200                 running_total += trb_buff_len;
3201
3202                 /* Calculate length for next transfer --
3203                  * Are we done queueing all the TRBs for this sg entry?
3204                  */
3205                 this_sg_len -= trb_buff_len;
3206                 if (this_sg_len == 0) {
3207                         --num_sgs;
3208                         if (num_sgs == 0)
3209                                 break;
3210                         sg = sg_next(sg);
3211                         addr = (u64) sg_dma_address(sg);
3212                         this_sg_len = sg_dma_len(sg);
3213                 } else {
3214                         addr += trb_buff_len;
3215                 }
3216
3217                 trb_buff_len = TRB_MAX_BUFF_SIZE -
3218                         (addr & (TRB_MAX_BUFF_SIZE - 1));
3219                 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3220                 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3221                         trb_buff_len =
3222                                 urb->transfer_buffer_length - running_total;
3223         } while (running_total < urb->transfer_buffer_length);
3224
3225         check_trb_math(urb, num_trbs, running_total);
3226         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3227                         start_cycle, start_trb);
3228         return 0;
3229 }
3230
3231 /* This is very similar to what ehci-q.c qtd_fill() does */
3232 int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3233                 struct urb *urb, int slot_id, unsigned int ep_index)
3234 {
3235         struct xhci_ring *ep_ring;
3236         struct urb_priv *urb_priv;
3237         struct xhci_td *td;
3238         int num_trbs;
3239         struct xhci_generic_trb *start_trb;
3240         bool first_trb;
3241         bool more_trbs_coming;
3242         int start_cycle;
3243         u32 field, length_field;
3244
3245         int running_total, trb_buff_len, ret;
3246         unsigned int total_packet_count;
3247         u64 addr;
3248
3249         if (urb->num_sgs)
3250                 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3251
3252         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3253         if (!ep_ring)
3254                 return -EINVAL;
3255
3256         num_trbs = 0;
3257         /* How much data is (potentially) left before the 64KB boundary? */
3258         running_total = TRB_MAX_BUFF_SIZE -
3259                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3260         running_total &= TRB_MAX_BUFF_SIZE - 1;
3261
3262         /* If there's some data on this 64KB chunk, or we have to send a
3263          * zero-length transfer, we need at least one TRB
3264          */
3265         if (running_total != 0 || urb->transfer_buffer_length == 0)
3266                 num_trbs++;
3267         /* How many more 64KB chunks to transfer, how many more TRBs? */
3268         while (running_total < urb->transfer_buffer_length) {
3269                 num_trbs++;
3270                 running_total += TRB_MAX_BUFF_SIZE;
3271         }
3272         /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3273
3274         if (!in_interrupt())
3275                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
3276                                 "addr = %#llx, num_trbs = %d\n",
3277                                 urb->ep->desc.bEndpointAddress,
3278                                 urb->transfer_buffer_length,
3279                                 urb->transfer_buffer_length,
3280                                 (unsigned long long)urb->transfer_dma,
3281                                 num_trbs);
3282
3283         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3284                         ep_index, urb->stream_id,
3285                         num_trbs, urb, 0, false, mem_flags);
3286         if (ret < 0)
3287                 return ret;
3288
3289         urb_priv = urb->hcpriv;
3290         td = urb_priv->td[0];
3291
3292         /*
3293          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3294          * until we've finished creating all the other TRBs.  The ring's cycle
3295          * state may change as we enqueue the other TRBs, so save it too.
3296          */
3297         start_trb = &ep_ring->enqueue->generic;
3298         start_cycle = ep_ring->cycle_state;
3299
3300         running_total = 0;
3301         total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3302                         usb_endpoint_maxp(&urb->ep->desc));
3303         /* How much data is in the first TRB? */
3304         addr = (u64) urb->transfer_dma;
3305         trb_buff_len = TRB_MAX_BUFF_SIZE -
3306                 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3307         if (trb_buff_len > urb->transfer_buffer_length)
3308                 trb_buff_len = urb->transfer_buffer_length;
3309
3310         first_trb = true;
3311
3312         /* Queue the first TRB, even if it's zero-length */
3313         do {
3314                 u32 remainder = 0;
3315                 field = 0;
3316
3317                 /* Don't change the cycle bit of the first TRB until later */
3318                 if (first_trb) {
3319                         first_trb = false;
3320                         if (start_cycle == 0)
3321                                 field |= 0x1;
3322                 } else
3323                         field |= ep_ring->cycle_state;
3324
3325                 /* Chain all the TRBs together; clear the chain bit in the last
3326                  * TRB to indicate it's the last TRB in the chain.
3327                  */
3328                 if (num_trbs > 1) {
3329                         field |= TRB_CHAIN;
3330                 } else {
3331                         /* FIXME - add check for ZERO_PACKET flag before this */
3332                         td->last_trb = ep_ring->enqueue;
3333                         field |= TRB_IOC;
3334                 }
3335
3336                 /* Only set interrupt on short packet for IN endpoints */
3337                 if (usb_urb_dir_in(urb))
3338                         field |= TRB_ISP;
3339
3340                 /* Set the TRB length, TD size, and interrupter fields. */
3341                 if (xhci->hci_version < 0x100) {
3342                         remainder = xhci_td_remainder(
3343                                         urb->transfer_buffer_length -
3344                                         running_total);
3345                 } else {
3346                         remainder = xhci_v1_0_td_remainder(running_total,
3347                                         trb_buff_len, total_packet_count, urb,
3348                                         num_trbs - 1);
3349                 }
3350                 length_field = TRB_LEN(trb_buff_len) |
3351                         remainder |
3352                         TRB_INTR_TARGET(0);
3353
3354                 if (num_trbs > 1)
3355                         more_trbs_coming = true;
3356                 else
3357                         more_trbs_coming = false;
3358                 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
3359                                 lower_32_bits(addr),
3360                                 upper_32_bits(addr),
3361                                 length_field,
3362                                 field | TRB_TYPE(TRB_NORMAL));
3363                 --num_trbs;
3364                 running_total += trb_buff_len;
3365
3366                 /* Calculate length for next transfer */
3367                 addr += trb_buff_len;
3368                 trb_buff_len = urb->transfer_buffer_length - running_total;
3369                 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3370                         trb_buff_len = TRB_MAX_BUFF_SIZE;
3371         } while (running_total < urb->transfer_buffer_length);
3372
3373         check_trb_math(urb, num_trbs, running_total);
3374         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3375                         start_cycle, start_trb);
3376         return 0;
3377 }
3378
3379 /* Caller must have locked xhci->lock */
3380 int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3381                 struct urb *urb, int slot_id, unsigned int ep_index)
3382 {
3383         struct xhci_ring *ep_ring;
3384         int num_trbs;
3385         int ret;
3386         struct usb_ctrlrequest *setup;
3387         struct xhci_generic_trb *start_trb;
3388         int start_cycle;
3389         u32 field, length_field;
3390         struct urb_priv *urb_priv;
3391         struct xhci_td *td;
3392
3393         ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3394         if (!ep_ring)
3395                 return -EINVAL;
3396
3397         /*
3398          * Need to copy setup packet into setup TRB, so we can't use the setup
3399          * DMA address.
3400          */
3401         if (!urb->setup_packet)
3402                 return -EINVAL;
3403
3404         if (!in_interrupt())
3405                 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3406                                 slot_id, ep_index);
3407         /* 1 TRB for setup, 1 for status */
3408         num_trbs = 2;
3409         /*
3410          * Don't need to check if we need additional event data and normal TRBs,
3411          * since data in control transfers will never get bigger than 16MB
3412          * XXX: can we get a buffer that crosses 64KB boundaries?
3413          */
3414         if (urb->transfer_buffer_length > 0)
3415                 num_trbs++;
3416         ret = prepare_transfer(xhci, xhci->devs[slot_id],
3417                         ep_index, urb->stream_id,
3418                         num_trbs, urb, 0, false, mem_flags);
3419         if (ret < 0)
3420                 return ret;
3421
3422         urb_priv = urb->hcpriv;
3423         td = urb_priv->td[0];
3424
3425         /*
3426          * Don't give the first TRB to the hardware (by toggling the cycle bit)
3427          * until we've finished creating all the other TRBs.  The ring's cycle
3428          * state may change as we enqueue the other TRBs, so save it too.
3429          */
3430         start_trb = &ep_ring->enqueue->generic;
3431         start_cycle = ep_ring->cycle_state;
3432
3433         /* Queue setup TRB - see section 6.4.1.2.1 */
3434         /* FIXME better way to translate setup_packet into two u32 fields? */
3435         setup = (struct usb_ctrlrequest *) urb->setup_packet;
3436         field = 0;
3437         field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3438         if (start_cycle == 0)
3439                 field |= 0x1;
3440
3441         /* xHCI 1.0/1.1 6.4.1.2.1: Transfer Type field */
3442         if (xhci->hci_version >= 0x100) {
3443                 if (urb->transfer_buffer_length > 0) {
3444                         if (setup->bRequestType & USB_DIR_IN)
3445                                 field |= TRB_TX_TYPE(TRB_DATA_IN);
3446                         else
3447                                 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3448                 }
3449         }
3450
3451         queue_trb(xhci, ep_ring, false, true, false,
3452                   setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3453                   le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3454                   TRB_LEN(8) | TRB_INTR_TARGET(0),
3455                   /* Immediate data in pointer */
3456                   field);
3457
3458         /* If there's data, queue data TRBs */
3459         /* Only set interrupt on short packet for IN endpoints */
3460         if (usb_urb_dir_in(urb))
3461                 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3462         else
3463                 field = TRB_TYPE(TRB_DATA);
3464
3465         length_field = TRB_LEN(urb->transfer_buffer_length) |
3466                 xhci_td_remainder(urb->transfer_buffer_length) |
3467                 TRB_INTR_TARGET(0);
3468         if (urb->transfer_buffer_length > 0) {
3469                 if (setup->bRequestType & USB_DIR_IN)
3470                         field |= TRB_DIR_IN;
3471                 queue_trb(xhci, ep_ring, false, true, false,
3472                                 lower_32_bits(urb->transfer_dma),
3473                                 upper_32_bits(urb->transfer_dma),
3474                                 length_field,
3475                                 field | ep_ring->cycle_state);
3476         }
3477
3478         /* Save the DMA address of the last TRB in the TD */
3479         td->last_trb = ep_ring->enqueue;
3480
3481         /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3482         /* If the device sent data, the status stage is an OUT transfer */
3483         if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3484                 field = 0;
3485         else
3486                 field = TRB_DIR_IN;
3487         queue_trb(xhci, ep_ring, false, false, false,
3488                         0,
3489                         0,
3490                         TRB_INTR_TARGET(0),
3491                         /* Event on completion */
3492                         field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3493
3494         giveback_first_trb(xhci, slot_id, ep_index, 0,
3495                         start_cycle, start_trb);
3496         return 0;
3497 }
3498
3499 static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3500                 struct urb *urb, int i)
3501 {
3502         int num_trbs = 0;
3503         u64 addr, td_len;
3504
3505         addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3506         td_len = urb->iso_frame_desc[i].length;
3507
3508         num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3509                         TRB_MAX_BUFF_SIZE);
3510         if (num_trbs == 0)
3511                 num_trbs++;
3512
3513         return num_trbs;
3514 }
3515
3516 /*
3517  * The transfer burst count field of the isochronous TRB defines the number of
3518  * bursts that are required to move all packets in this TD.  Only SuperSpeed
3519  * devices can burst up to bMaxBurst number of packets per service interval.
3520  * This field is zero based, meaning a value of zero in the field means one
3521  * burst.  Basically, for everything but SuperSpeed devices, this field will be
3522  * zero.  Only xHCI 1.0 host controllers support this field.
3523  */
3524 static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3525                 struct usb_device *udev,
3526                 struct urb *urb, unsigned int total_packet_count)
3527 {
3528         unsigned int max_burst;
3529
3530         if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3531                 return 0;
3532
3533         max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3534         return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
3535 }
3536
3537 /*
3538  * Returns the number of packets in the last "burst" of packets.  This field is
3539  * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3540  * the last burst packet count is equal to the total number of packets in the
3541  * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3542  * must contain (bMaxBurst + 1) number of packets, but the last burst can
3543  * contain 1 to (bMaxBurst + 1) packets.
3544  */
3545 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3546                 struct usb_device *udev,
3547                 struct urb *urb, unsigned int total_packet_count)
3548 {
3549         unsigned int max_burst;
3550         unsigned int residue;
3551
3552         if (xhci->hci_version < 0x100)
3553                 return 0;
3554
3555         switch (udev->speed) {
3556         case USB_SPEED_SUPER:
3557                 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3558                 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3559                 residue = total_packet_count % (max_burst + 1);
3560                 /* If residue is zero, the last burst contains (max_burst + 1)
3561                  * number of packets, but the TLBPC field is zero-based.
3562                  */
3563                 if (residue == 0)
3564                         return max_burst;
3565                 return residue - 1;
3566         default:
3567                 if (total_packet_count == 0)
3568                         return 0;
3569                 return total_packet_count - 1;
3570         }
3571 }
3572
3573 /* This is for isoc transfer */
3574 static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3575                 struct urb *urb, int slot_id, unsigned int ep_index)
3576 {
3577         struct xhci_ring *ep_ring;
3578         struct urb_priv *urb_priv;
3579         struct xhci_td *td;
3580         int num_tds, trbs_per_td;
3581         struct xhci_generic_trb *start_trb;
3582         bool first_trb;
3583         int start_cycle;
3584         u32 field, length_field;
3585         int running_total, trb_buff_len, td_len, td_remain_len, ret;
3586         u64 start_addr, addr;
3587         int i, j;
3588         bool more_trbs_coming;
3589
3590         ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3591
3592         num_tds = urb->number_of_packets;
3593         if (num_tds < 1) {
3594                 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3595                 return -EINVAL;
3596         }
3597
3598         if (!in_interrupt())
3599                 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
3600                                 " addr = %#llx, num_tds = %d\n",
3601                                 urb->ep->desc.bEndpointAddress,
3602                                 urb->transfer_buffer_length,
3603                                 urb->transfer_buffer_length,
3604                                 (unsigned long long)urb->transfer_dma,
3605                                 num_tds);
3606
3607         start_addr = (u64) urb->transfer_dma;
3608         start_trb = &ep_ring->enqueue->generic;
3609         start_cycle = ep_ring->cycle_state;
3610
3611         urb_priv = urb->hcpriv;
3612         /* Queue the first TRB, even if it's zero-length */
3613         for (i = 0; i < num_tds; i++) {
3614                 unsigned int total_packet_count;
3615                 unsigned int burst_count;
3616                 unsigned int residue;
3617
3618                 first_trb = true;
3619                 running_total = 0;
3620                 addr = start_addr + urb->iso_frame_desc[i].offset;
3621                 td_len = urb->iso_frame_desc[i].length;
3622                 td_remain_len = td_len;
3623                 total_packet_count = DIV_ROUND_UP(td_len,
3624                                 GET_MAX_PACKET(
3625                                         usb_endpoint_maxp(&urb->ep->desc)));
3626                 /* A zero-length transfer still involves at least one packet. */
3627                 if (total_packet_count == 0)
3628                         total_packet_count++;
3629                 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3630                                 total_packet_count);
3631                 residue = xhci_get_last_burst_packet_count(xhci,
3632                                 urb->dev, urb, total_packet_count);
3633
3634                 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3635
3636                 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3637                                 urb->stream_id, trbs_per_td, urb, i, true,
3638                                 mem_flags);
3639                 if (ret < 0) {
3640                         if (i == 0)
3641                                 return ret;
3642                         goto cleanup;
3643                 }
3644
3645                 td = urb_priv->td[i];
3646                 for (j = 0; j < trbs_per_td; j++) {
3647                         u32 remainder = 0;
3648                         field = 0;
3649
3650                         if (first_trb) {
3651                                 field = TRB_TBC(burst_count) |
3652                                         TRB_TLBPC(residue);
3653                                 /* Queue the isoc TRB */
3654                                 field |= TRB_TYPE(TRB_ISOC);
3655                                 /* Assume URB_ISO_ASAP is set */
3656                                 field |= TRB_SIA;
3657                                 if (i == 0) {
3658                                         if (start_cycle == 0)
3659                                                 field |= 0x1;
3660                                 } else
3661                                         field |= ep_ring->cycle_state;
3662                                 first_trb = false;
3663                         } else {
3664                                 /* Queue other normal TRBs */
3665                                 field |= TRB_TYPE(TRB_NORMAL);
3666                                 field |= ep_ring->cycle_state;
3667                         }
3668
3669                         /* Only set interrupt on short packet for IN EPs */
3670                         if (usb_urb_dir_in(urb))
3671                                 field |= TRB_ISP;
3672
3673                         /* Chain all the TRBs together; clear the chain bit in
3674                          * the last TRB to indicate it's the last TRB in the
3675                          * chain.
3676                          */
3677                         if (j < trbs_per_td - 1) {
3678                                 field |= TRB_CHAIN;
3679                                 more_trbs_coming = true;
3680                         } else {
3681                                 td->last_trb = ep_ring->enqueue;
3682                                 field |= TRB_IOC;
3683                                 if (xhci->hci_version == 0x100 &&
3684                                                 !(xhci->quirks &
3685                                                         XHCI_AVOID_BEI)) {
3686                                         /* Set BEI bit except for the last td */
3687                                         if (i < num_tds - 1)
3688                                                 field |= TRB_BEI;
3689                                 }
3690                                 more_trbs_coming = false;
3691                         }
3692
3693                         /* Calculate TRB length */
3694                         trb_buff_len = TRB_MAX_BUFF_SIZE -
3695                                 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3696                         if (trb_buff_len > td_remain_len)
3697                                 trb_buff_len = td_remain_len;
3698
3699                         /* Set the TRB length, TD size, & interrupter fields. */
3700                         if (xhci->hci_version < 0x100) {
3701                                 remainder = xhci_td_remainder(
3702                                                 td_len - running_total);
3703                         } else {
3704                                 remainder = xhci_v1_0_td_remainder(
3705                                                 running_total, trb_buff_len,
3706                                                 total_packet_count, urb,
3707                                                 (trbs_per_td - j - 1));
3708                         }
3709                         length_field = TRB_LEN(trb_buff_len) |
3710                                 remainder |
3711                                 TRB_INTR_TARGET(0);
3712
3713                         queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
3714                                 lower_32_bits(addr),
3715                                 upper_32_bits(addr),
3716                                 length_field,
3717                                 field);
3718                         running_total += trb_buff_len;
3719
3720                         addr += trb_buff_len;
3721                         td_remain_len -= trb_buff_len;
3722                 }
3723
3724                 /* Check TD length */
3725                 if (running_total != td_len) {
3726                         xhci_err(xhci, "ISOC TD length unmatch\n");
3727                         ret = -EINVAL;
3728                         goto cleanup;
3729                 }
3730         }
3731
3732         if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3733                 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3734                         usb_amd_quirk_pll_disable();
3735         }
3736         xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3737
3738         giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3739                         start_cycle, start_trb);
3740         return 0;
3741 cleanup:
3742         /* Clean up a partially enqueued isoc transfer. */
3743
3744         for (i--; i >= 0; i--)
3745                 list_del_init(&urb_priv->td[i]->td_list);
3746
3747         /* Use the first TD as a temporary variable to turn the TDs we've queued
3748          * into No-ops with a software-owned cycle bit. That way the hardware
3749          * won't accidentally start executing bogus TDs when we partially
3750          * overwrite them.  td->first_trb and td->start_seg are already set.
3751          */
3752         urb_priv->td[0]->last_trb = ep_ring->enqueue;
3753         /* Every TRB except the first & last will have its cycle bit flipped. */
3754         td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3755
3756         /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3757         ep_ring->enqueue = urb_priv->td[0]->first_trb;
3758         ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3759         ep_ring->cycle_state = start_cycle;
3760         usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3761         return ret;
3762 }
3763
3764 /*
3765  * Check transfer ring to guarantee there is enough room for the urb.
3766  * Update ISO URB start_frame and interval.
3767  * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3768  * update the urb->start_frame by now.
3769  * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3770  */
3771 int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3772                 struct urb *urb, int slot_id, unsigned int ep_index)
3773 {
3774         struct xhci_virt_device *xdev;
3775         struct xhci_ring *ep_ring;
3776         struct xhci_ep_ctx *ep_ctx;
3777         int start_frame;
3778         int xhci_interval;
3779         int ep_interval;
3780         int num_tds, num_trbs, i;
3781         int ret;
3782
3783         xdev = xhci->devs[slot_id];
3784         ep_ring = xdev->eps[ep_index].ring;
3785         ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3786
3787         num_trbs = 0;
3788         num_tds = urb->number_of_packets;
3789         for (i = 0; i < num_tds; i++)
3790                 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3791
3792         /* Check the ring to guarantee there is enough room for the whole urb.
3793          * Do not insert any td of the urb to the ring if the check failed.
3794          */
3795         ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3796                            num_trbs, true, mem_flags);
3797         if (ret)
3798                 return ret;
3799
3800         start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3801         start_frame &= 0x3fff;
3802
3803         urb->start_frame = start_frame;
3804         if (urb->dev->speed == USB_SPEED_LOW ||
3805                         urb->dev->speed == USB_SPEED_FULL)
3806                 urb->start_frame >>= 3;
3807
3808         xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3809         ep_interval = urb->interval;
3810         /* Convert to microframes */
3811         if (urb->dev->speed == USB_SPEED_LOW ||
3812                         urb->dev->speed == USB_SPEED_FULL)
3813                 ep_interval *= 8;
3814         /* FIXME change this to a warning and a suggestion to use the new API
3815          * to set the polling interval (once the API is added).
3816          */
3817         if (xhci_interval != ep_interval) {
3818                 if (printk_ratelimit())
3819                         dev_dbg(&urb->dev->dev, "Driver uses different interval"
3820                                         " (%d microframe%s) than xHCI "
3821                                         "(%d microframe%s)\n",
3822                                         ep_interval,
3823                                         ep_interval == 1 ? "" : "s",
3824                                         xhci_interval,
3825                                         xhci_interval == 1 ? "" : "s");
3826                 urb->interval = xhci_interval;
3827                 /* Convert back to frames for LS/FS devices */
3828                 if (urb->dev->speed == USB_SPEED_LOW ||
3829                                 urb->dev->speed == USB_SPEED_FULL)
3830                         urb->interval /= 8;
3831         }
3832         return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3833 }
3834
3835 /****           Command Ring Operations         ****/
3836
3837 /* Generic function for queueing a command TRB on the command ring.
3838  * Check to make sure there's room on the command ring for one command TRB.
3839  * Also check that there's room reserved for commands that must not fail.
3840  * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3841  * then only check for the number of reserved spots.
3842  * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3843  * because the command event handler may want to resubmit a failed command.
3844  */
3845 static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3846                 u32 field3, u32 field4, bool command_must_succeed)
3847 {
3848         int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3849         int ret;
3850
3851         if (!command_must_succeed)
3852                 reserved_trbs++;
3853
3854         ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3855                         reserved_trbs, false, GFP_ATOMIC);
3856         if (ret < 0) {
3857                 xhci_err(xhci, "ERR: No room for command on command ring\n");
3858                 if (command_must_succeed)
3859                         xhci_err(xhci, "ERR: Reserved TRB counting for "
3860                                         "unfailable commands failed.\n");
3861                 return ret;
3862         }
3863         queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3864                         field3, field4 | xhci->cmd_ring->cycle_state);
3865         return 0;
3866 }
3867
3868 /* Queue a slot enable or disable request on the command ring */
3869 int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3870 {
3871         return queue_command(xhci, 0, 0, 0,
3872                         TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3873 }
3874
3875 /* Queue an address device command TRB */
3876 int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3877                 u32 slot_id)
3878 {
3879         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3880                         upper_32_bits(in_ctx_ptr), 0,
3881                         TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3882                         false);
3883 }
3884
3885 int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3886                 u32 field1, u32 field2, u32 field3, u32 field4)
3887 {
3888         return queue_command(xhci, field1, field2, field3, field4, false);
3889 }
3890
3891 /* Queue a reset device command TRB */
3892 int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3893 {
3894         return queue_command(xhci, 0, 0, 0,
3895                         TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3896                         false);
3897 }
3898
3899 /* Queue a configure endpoint command TRB */
3900 int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3901                 u32 slot_id, bool command_must_succeed)
3902 {
3903         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3904                         upper_32_bits(in_ctx_ptr), 0,
3905                         TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3906                         command_must_succeed);
3907 }
3908
3909 /* Queue an evaluate context command TRB */
3910 int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3911                 u32 slot_id)
3912 {
3913         return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3914                         upper_32_bits(in_ctx_ptr), 0,
3915                         TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3916                         false);
3917 }
3918
3919 /*
3920  * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3921  * activity on an endpoint that is about to be suspended.
3922  */
3923 int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3924                 unsigned int ep_index, int suspend)
3925 {
3926         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3927         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3928         u32 type = TRB_TYPE(TRB_STOP_RING);
3929         u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3930
3931         return queue_command(xhci, 0, 0, 0,
3932                         trb_slot_id | trb_ep_index | type | trb_suspend, false);
3933 }
3934
3935 /* Set Transfer Ring Dequeue Pointer command.
3936  * This should not be used for endpoints that have streams enabled.
3937  */
3938 static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3939                 unsigned int ep_index, unsigned int stream_id,
3940                 struct xhci_segment *deq_seg,
3941                 union xhci_trb *deq_ptr, u32 cycle_state)
3942 {
3943         dma_addr_t addr;
3944         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3945         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3946         u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3947         u32 type = TRB_TYPE(TRB_SET_DEQ);
3948         struct xhci_virt_ep *ep;
3949
3950         addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3951         if (addr == 0) {
3952                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3953                 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3954                                 deq_seg, deq_ptr);
3955                 return 0;
3956         }
3957         ep = &xhci->devs[slot_id]->eps[ep_index];
3958         if ((ep->ep_state & SET_DEQ_PENDING)) {
3959                 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3960                 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3961                 return 0;
3962         }
3963         ep->queued_deq_seg = deq_seg;
3964         ep->queued_deq_ptr = deq_ptr;
3965         return queue_command(xhci, lower_32_bits(addr) | cycle_state,
3966                         upper_32_bits(addr), trb_stream_id,
3967                         trb_slot_id | trb_ep_index | type, false);
3968 }
3969
3970 int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3971                 unsigned int ep_index)
3972 {
3973         u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3974         u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3975         u32 type = TRB_TYPE(TRB_RESET_EP);
3976
3977         return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3978                         false);
3979 }