drivers/usb/host/xhci-hub.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23
  24 #include <linux/slab.h>
  25 #include <linux/device.h>
  26 #include <asm/unaligned.h>
  27
  28 #include "xhci.h"
  29 #include "xhci-trace.h"
  30
  31 #define PORT_WAKE_BITS  (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  32 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  33                          PORT_RC | PORT_PLC | PORT_PE)
  34
  35 /* USB 3.0 BOS descriptor and a capability descriptor, combined */
  36 static u8 usb_bos_descriptor [] = {
  37         USB_DT_BOS_SIZE,                /*  __u8 bLength, 5 bytes */
  38         USB_DT_BOS,                     /*  __u8 bDescriptorType */
  39         0x0F, 0x00,                     /*  __le16 wTotalLength, 15 bytes */
  40         0x1,                            /*  __u8 bNumDeviceCaps */
  41         /* First device capability */
  42         USB_DT_USB_SS_CAP_SIZE,         /*  __u8 bLength, 10 bytes */
  43         USB_DT_DEVICE_CAPABILITY,       /* Device Capability */
  44         USB_SS_CAP_TYPE,                /* bDevCapabilityType, SUPERSPEED_USB */
  45         0x00,                           /* bmAttributes, LTM off by default */
  46         USB_5GBPS_OPERATION, 0x00,      /* wSpeedsSupported, 5Gbps only */
  47         0x03,                           /* bFunctionalitySupport,
  48                                            USB 3.0 speed only */
  49         0x00,                           /* bU1DevExitLat, set later. */
  50         0x00, 0x00                      /* __le16 bU2DevExitLat, set later. */
  51 };
  52
  53
  54 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  55                 struct usb_hub_descriptor *desc, int ports)
  56 {
  57         u16 temp;
  58
  59         desc->bPwrOn2PwrGood = 10;      /* xhci section 5.4.9 says 20ms max */
  60         desc->bHubContrCurrent = 0;
  61
  62         desc->bNbrPorts = ports;
  63         temp = 0;
  64         /* Bits 1:0 - support per-port power switching, or power always on */
  65         if (HCC_PPC(xhci->hcc_params))
  66                 temp |= HUB_CHAR_INDV_PORT_LPSM;
  67         else
  68                 temp |= HUB_CHAR_NO_LPSM;
  69         /* Bit  2 - root hubs are not part of a compound device */
  70         /* Bits 4:3 - individual port over current protection */
  71         temp |= HUB_CHAR_INDV_PORT_OCPM;
  72         /* Bits 6:5 - no TTs in root ports */
  73         /* Bit  7 - no port indicators */
  74         desc->wHubCharacteristics = cpu_to_le16(temp);
  75 }
  76
  77 /* Fill in the USB 2.0 roothub descriptor */
  78 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  79                 struct usb_hub_descriptor *desc)
  80 {
  81         int ports;
  82         u16 temp;
  83         __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  84         u32 portsc;
  85         unsigned int i;
  86
  87         ports = xhci->num_usb2_ports;
  88
  89         xhci_common_hub_descriptor(xhci, desc, ports);
  90         desc->bDescriptorType = USB_DT_HUB;
  91         temp = 1 + (ports / 8);
  92         desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  93
  94         /* The Device Removable bits are reported on a byte granularity.
  95          * If the port doesn't exist within that byte, the bit is set to 0.
  96          */
  97         memset(port_removable, 0, sizeof(port_removable));
  98         for (i = 0; i < ports; i++) {
  99                 portsc = readl(xhci->usb2_ports[i]);
 100                 /* If a device is removable, PORTSC reports a 0, same as in the
 101                  * hub descriptor DeviceRemovable bits.
 102                  */
 103                 if (portsc & PORT_DEV_REMOVE)
 104                         /* This math is hairy because bit 0 of DeviceRemovable
 105                          * is reserved, and bit 1 is for port 1, etc.
 106                          */
 107                         port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
 108         }
 109
 110         /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
 111          * ports on it.  The USB 2.0 specification says that there are two
 112          * variable length fields at the end of the hub descriptor:
 113          * DeviceRemovable and PortPwrCtrlMask.  But since we can have less than
 114          * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
 115          * to set PortPwrCtrlMask bits.  PortPwrCtrlMask must always be set to
 116          * 0xFF, so we initialize the both arrays (DeviceRemovable and
 117          * PortPwrCtrlMask) to 0xFF.  Then we set the DeviceRemovable for each
 118          * set of ports that actually exist.
 119          */
 120         memset(desc->u.hs.DeviceRemovable, 0xff,
 121                         sizeof(desc->u.hs.DeviceRemovable));
 122         memset(desc->u.hs.PortPwrCtrlMask, 0xff,
 123                         sizeof(desc->u.hs.PortPwrCtrlMask));
 124
 125         for (i = 0; i < (ports + 1 + 7) / 8; i++)
 126                 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
 127                                 sizeof(__u8));
 128 }
 129
 130 /* Fill in the USB 3.0 roothub descriptor */
 131 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 132                 struct usb_hub_descriptor *desc)
 133 {
 134         int ports;
 135         u16 port_removable;
 136         u32 portsc;
 137         unsigned int i;
 138
 139         ports = xhci->num_usb3_ports;
 140         xhci_common_hub_descriptor(xhci, desc, ports);
 141         desc->bDescriptorType = USB_DT_SS_HUB;
 142         desc->bDescLength = USB_DT_SS_HUB_SIZE;
 143
 144         /* header decode latency should be zero for roothubs,
 145          * see section 4.23.5.2.
 146          */
 147         desc->u.ss.bHubHdrDecLat = 0;
 148         desc->u.ss.wHubDelay = 0;
 149
 150         port_removable = 0;
 151         /* bit 0 is reserved, bit 1 is for port 1, etc. */
 152         for (i = 0; i < ports; i++) {
 153                 portsc = readl(xhci->usb3_ports[i]);
 154                 if (portsc & PORT_DEV_REMOVE)
 155                         port_removable |= 1 << (i + 1);
 156         }
 157
 158         desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
 159 }
 160
 161 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 162                 struct usb_hub_descriptor *desc)
 163 {
 164
 165         if (hcd->speed == HCD_USB3)
 166                 xhci_usb3_hub_descriptor(hcd, xhci, desc);
 167         else
 168                 xhci_usb2_hub_descriptor(hcd, xhci, desc);
 169
 170 }
 171
 172 static unsigned int xhci_port_speed(unsigned int port_status)
 173 {
 174         if (DEV_LOWSPEED(port_status))
 175                 return USB_PORT_STAT_LOW_SPEED;
 176         if (DEV_HIGHSPEED(port_status))
 177                 return USB_PORT_STAT_HIGH_SPEED;
 178         /*
 179          * FIXME: Yes, we should check for full speed, but the core uses that as
 180          * a default in portspeed() in usb/core/hub.c (which is the only place
 181          * USB_PORT_STAT_*_SPEED is used).
 182          */
 183         return 0;
 184 }
 185
 186 /*
 187  * These bits are Read Only (RO) and should be saved and written to the
 188  * registers: 0, 3, 10:13, 30
 189  * connect status, over-current status, port speed, and device removable.
 190  * connect status and port speed are also sticky - meaning they're in
 191  * the AUX well and they aren't changed by a hot, warm, or cold reset.
 192  */
 193 #define XHCI_PORT_RO    ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
 194 /*
 195  * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
 196  * bits 5:8, 9, 14:15, 25:27
 197  * link state, port power, port indicator state, "wake on" enable state
 198  */
 199 #define XHCI_PORT_RWS   ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
 200 /*
 201  * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
 202  * bit 4 (port reset)
 203  */
 204 #define XHCI_PORT_RW1S  ((1<<4))
 205 /*
 206  * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
 207  * bits 1, 17, 18, 19, 20, 21, 22, 23
 208  * port enable/disable, and
 209  * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
 210  * over-current, reset, link state, and L1 change
 211  */
 212 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
 213 /*
 214  * Bit 16 is RW, and writing a '1' to it causes the link state control to be
 215  * latched in
 216  */
 217 #define XHCI_PORT_RW    ((1<<16))
 218 /*
 219  * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
 220  * bits 2, 24, 28:31
 221  */
 222 #define XHCI_PORT_RZ    ((1<<2) | (1<<24) | (0xf<<28))
 223
 224 /*
 225  * Given a port state, this function returns a value that would result in the
 226  * port being in the same state, if the value was written to the port status
 227  * control register.
 228  * Save Read Only (RO) bits and save read/write bits where
 229  * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
 230  * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
 231  */
 232 u32 xhci_port_state_to_neutral(u32 state)
 233 {
 234         /* Save read-only status and port state */
 235         return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
 236 }
 237
 238 /*
 239  * find slot id based on port number.
 240  * @port: The one-based port number from one of the two split roothubs.
 241  */
 242 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 243                 u16 port)
 244 {
 245         int slot_id;
 246         int i;
 247         enum usb_device_speed speed;
 248
 249         slot_id = 0;
 250         for (i = 0; i < MAX_HC_SLOTS; i++) {
 251                 if (!xhci->devs[i])
 252                         continue;
 253                 speed = xhci->devs[i]->udev->speed;
 254                 if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
 255                                 && xhci->devs[i]->fake_port == port) {
 256                         slot_id = i;
 257                         break;
 258                 }
 259         }
 260
 261         return slot_id;
 262 }
 263
 264 /*
 265  * Stop device
 266  * It issues stop endpoint command for EP 0 to 30. And wait the last command
 267  * to complete.
 268  * suspend will set to 1, if suspend bit need to set in command.
 269  */
 270 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
 271 {
 272         struct xhci_virt_device *virt_dev;
 273         struct xhci_command *cmd;
 274         unsigned long flags;
 275         int ret;
 276         int i;
 277
 278         ret = 0;
 279         virt_dev = xhci->devs[slot_id];
 280         cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
 281         if (!cmd) {
 282                 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
 283                 return -ENOMEM;
 284         }
 285
 286         spin_lock_irqsave(&xhci->lock, flags);
 287         for (i = LAST_EP_INDEX; i > 0; i--) {
 288                 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
 289                         struct xhci_command *command;
 290                         command = xhci_alloc_command(xhci, false, false,
 291                                                      GFP_NOWAIT);
 292                         if (!command) {
 293                                 spin_unlock_irqrestore(&xhci->lock, flags);
 294                                 xhci_free_command(xhci, cmd);
 295                                 return -ENOMEM;
 296
 297                         }
 298                         xhci_queue_stop_endpoint(xhci, command, slot_id, i,
 299                                                  suspend);
 300                 }
 301         }
 302         xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
 303         xhci_ring_cmd_db(xhci);
 304         spin_unlock_irqrestore(&xhci->lock, flags);
 305
 306         /* Wait for last stop endpoint command to finish */
 307         wait_for_completion(cmd->completion);
 308
 309         if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
 310                 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
 311                 ret = -ETIME;
 312         }
 313         xhci_free_command(xhci, cmd);
 314         return ret;
 315 }
 316
 317 /*
 318  * Ring device, it rings the all doorbells unconditionally.
 319  */
 320 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
 321 {
 322         int i;
 323
 324         for (i = 0; i < LAST_EP_INDEX + 1; i++)
 325                 if (xhci->devs[slot_id]->eps[i].ring &&
 326                     xhci->devs[slot_id]->eps[i].ring->dequeue)
 327                         xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
 328
 329         return;
 330 }
 331
 332 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
 333                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 334 {
 335         /* Don't allow the USB core to disable SuperSpeed ports. */
 336         if (hcd->speed == HCD_USB3) {
 337                 xhci_dbg(xhci, "Ignoring request to disable "
 338                                 "SuperSpeed port.\n");
 339                 return;
 340         }
 341
 342         /* Write 1 to disable the port */
 343         writel(port_status | PORT_PE, addr);
 344         port_status = readl(addr);
 345         xhci_dbg(xhci, "disable port, actual port %d status  = 0x%x\n",
 346                         wIndex, port_status);
 347 }
 348
 349 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
 350                 u16 wIndex, __le32 __iomem *addr, u32 port_status)
 351 {
 352         char *port_change_bit;
 353         u32 status;
 354
 355         switch (wValue) {
 356         case USB_PORT_FEAT_C_RESET:
 357                 status = PORT_RC;
 358                 port_change_bit = "reset";
 359                 break;
 360         case USB_PORT_FEAT_C_BH_PORT_RESET:
 361                 status = PORT_WRC;
 362                 port_change_bit = "warm(BH) reset";
 363                 break;
 364         case USB_PORT_FEAT_C_CONNECTION:
 365                 status = PORT_CSC;
 366                 port_change_bit = "connect";
 367                 break;
 368         case USB_PORT_FEAT_C_OVER_CURRENT:
 369                 status = PORT_OCC;
 370                 port_change_bit = "over-current";
 371                 break;
 372         case USB_PORT_FEAT_C_ENABLE:
 373                 status = PORT_PEC;
 374                 port_change_bit = "enable/disable";
 375                 break;
 376         case USB_PORT_FEAT_C_SUSPEND:
 377                 status = PORT_PLC;
 378                 port_change_bit = "suspend/resume";
 379                 break;
 380         case USB_PORT_FEAT_C_PORT_LINK_STATE:
 381                 status = PORT_PLC;
 382                 port_change_bit = "link state";
 383                 break;
 384         default:
 385                 /* Should never happen */
 386                 return;
 387         }
 388         /* Change bits are all write 1 to clear */
 389         writel(port_status | status, addr);
 390         port_status = readl(addr);
 391         xhci_dbg(xhci, "clear port %s change, actual port %d status  = 0x%x\n",
 392                         port_change_bit, wIndex, port_status);
 393 }
 394
 395 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
 396 {
 397         int max_ports;
 398         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 399
 400         if (hcd->speed == HCD_USB3) {
 401                 max_ports = xhci->num_usb3_ports;
 402                 *port_array = xhci->usb3_ports;
 403         } else {
 404                 max_ports = xhci->num_usb2_ports;
 405                 *port_array = xhci->usb2_ports;
 406         }
 407
 408         return max_ports;
 409 }
 410
 411 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 412                                 int port_id, u32 link_state)
 413 {
 414         u32 temp;
 415
 416         temp = readl(port_array[port_id]);
 417         temp = xhci_port_state_to_neutral(temp);
 418         temp &= ~PORT_PLS_MASK;
 419         temp |= PORT_LINK_STROBE | link_state;
 420         writel(temp, port_array[port_id]);
 421 }
 422
 423 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
 424                 __le32 __iomem **port_array, int port_id, u16 wake_mask)
 425 {
 426         u32 temp;
 427
 428         temp = readl(port_array[port_id]);
 429         temp = xhci_port_state_to_neutral(temp);
 430
 431         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
 432                 temp |= PORT_WKCONN_E;
 433         else
 434                 temp &= ~PORT_WKCONN_E;
 435
 436         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
 437                 temp |= PORT_WKDISC_E;
 438         else
 439                 temp &= ~PORT_WKDISC_E;
 440
 441         if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
 442                 temp |= PORT_WKOC_E;
 443         else
 444                 temp &= ~PORT_WKOC_E;
 445
 446         writel(temp, port_array[port_id]);
 447 }
 448
 449 /* Test and clear port RWC bit */
 450 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
 451                                 int port_id, u32 port_bit)
 452 {
 453         u32 temp;
 454
 455         temp = readl(port_array[port_id]);
 456         if (temp & port_bit) {
 457                 temp = xhci_port_state_to_neutral(temp);
 458                 temp |= port_bit;
 459                 writel(temp, port_array[port_id]);
 460         }
 461 }
 462
 463 /* Updates Link Status for USB 2.1 port */
 464 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
 465 {
 466         if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
 467                 *status |= USB_PORT_STAT_L1;
 468 }
 469
 470 /* Updates Link Status for super Speed port */
 471 static void xhci_hub_report_usb3_link_state(u32 *status, u32 status_reg)
 472 {
 473         u32 pls = status_reg & PORT_PLS_MASK;
 474
 475         /* resume state is a xHCI internal state.
 476          * Do not report it to usb core.
 477          */
 478         if (pls == XDEV_RESUME)
 479                 return;
 480
 481         /* When the CAS bit is set then warm reset
 482          * should be performed on port
 483          */
 484         if (status_reg & PORT_CAS) {
 485                 /* The CAS bit can be set while the port is
 486                  * in any link state.
 487                  * Only roothubs have CAS bit, so we
 488                  * pretend to be in compliance mode
 489                  * unless we're already in compliance
 490                  * or the inactive state.
 491                  */
 492                 if (pls != USB_SS_PORT_LS_COMP_MOD &&
 493                     pls != USB_SS_PORT_LS_SS_INACTIVE) {
 494                         pls = USB_SS_PORT_LS_COMP_MOD;
 495                 }
 496                 /* Return also connection bit -
 497                  * hub state machine resets port
 498                  * when this bit is set.
 499                  */
 500                 pls |= USB_PORT_STAT_CONNECTION;
 501         } else {
 502                 /*
 503                  * If CAS bit isn't set but the Port is already at
 504                  * Compliance Mode, fake a connection so the USB core
 505                  * notices the Compliance state and resets the port.
 506                  * This resolves an issue generated by the SN65LVPE502CP
 507                  * in which sometimes the port enters compliance mode
 508                  * caused by a delay on the host-device negotiation.
 509                  */
 510                 if (pls == USB_SS_PORT_LS_COMP_MOD)
 511                         pls |= USB_PORT_STAT_CONNECTION;
 512         }
 513
 514         /* update status field */
 515         *status |= pls;
 516 }
 517
 518 /*
 519  * Function for Compliance Mode Quirk.
 520  *
 521  * This Function verifies if all xhc USB3 ports have entered U0, if so,
 522  * the compliance mode timer is deleted. A port won't enter
 523  * compliance mode if it has previously entered U0.
 524  */
 525 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
 526                                     u16 wIndex)
 527 {
 528         u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
 529         bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
 530
 531         if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
 532                 return;
 533
 534         if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
 535                 xhci->port_status_u0 |= 1 << wIndex;
 536                 if (xhci->port_status_u0 == all_ports_seen_u0) {
 537                         del_timer_sync(&xhci->comp_mode_recovery_timer);
 538                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 539                                 "All USB3 ports have entered U0 already!");
 540                         xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
 541                                 "Compliance Mode Recovery Timer Deleted.");
 542                 }
 543         }
 544 }
 545
 546 /*
 547  * Converts a raw xHCI port status into the format that external USB 2.0 or USB
 548  * 3.0 hubs use.
 549  *
 550  * Possible side effects:
 551  *  - Mark a port as being done with device resume,
 552  *    and ring the endpoint doorbells.
 553  *  - Stop the Synopsys redriver Compliance Mode polling.
 554  *  - Drop and reacquire the xHCI lock, in order to wait for port resume.
 555  */
 556 static u32 xhci_get_port_status(struct usb_hcd *hcd,
 557                 struct xhci_bus_state *bus_state,
 558                 __le32 __iomem **port_array,
 559                 u16 wIndex, u32 raw_port_status,
 560                 unsigned long flags)
 561         __releases(&xhci->lock)
 562         __acquires(&xhci->lock)
 563 {
 564         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 565         u32 status = 0;
 566         int slot_id;
 567
 568         /* wPortChange bits */
 569         if (raw_port_status & PORT_CSC)
 570                 status |= USB_PORT_STAT_C_CONNECTION << 16;
 571         if (raw_port_status & PORT_PEC)
 572                 status |= USB_PORT_STAT_C_ENABLE << 16;
 573         if ((raw_port_status & PORT_OCC))
 574                 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
 575         if ((raw_port_status & PORT_RC))
 576                 status |= USB_PORT_STAT_C_RESET << 16;
 577         /* USB3.0 only */
 578         if (hcd->speed == HCD_USB3) {
 579                 if ((raw_port_status & PORT_PLC))
 580                         status |= USB_PORT_STAT_C_LINK_STATE << 16;
 581                 if ((raw_port_status & PORT_WRC))
 582                         status |= USB_PORT_STAT_C_BH_RESET << 16;
 583         }
 584
 585         if (hcd->speed != HCD_USB3) {
 586                 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
 587                                 && (raw_port_status & PORT_POWER))
 588                         status |= USB_PORT_STAT_SUSPEND;
 589         }
 590         if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
 591                         !DEV_SUPERSPEED(raw_port_status)) {
 592                 if ((raw_port_status & PORT_RESET) ||
 593                                 !(raw_port_status & PORT_PE))
 594                         return 0xffffffff;
 595                 if (time_after_eq(jiffies,
 596                                         bus_state->resume_done[wIndex])) {
 597                         int time_left;
 598
 599                         xhci_dbg(xhci, "Resume USB2 port %d\n",
 600                                         wIndex + 1);
 601                         bus_state->resume_done[wIndex] = 0;
 602                         clear_bit(wIndex, &bus_state->resuming_ports);
 603
 604                         set_bit(wIndex, &bus_state->rexit_ports);
 605                         xhci_set_link_state(xhci, port_array, wIndex,
 606                                         XDEV_U0);
 607
 608                         spin_unlock_irqrestore(&xhci->lock, flags);
 609                         time_left = wait_for_completion_timeout(
 610                                         &bus_state->rexit_done[wIndex],
 611                                         msecs_to_jiffies(
 612                                                 XHCI_MAX_REXIT_TIMEOUT));
 613                         spin_lock_irqsave(&xhci->lock, flags);
 614
 615                         if (time_left) {
 616                                 slot_id = xhci_find_slot_id_by_port(hcd,
 617                                                 xhci, wIndex + 1);
 618                                 if (!slot_id) {
 619                                         xhci_dbg(xhci, "slot_id is zero\n");
 620                                         return 0xffffffff;
 621                                 }
 622                                 xhci_ring_device(xhci, slot_id);
 623                         } else {
 624                                 int port_status = readl(port_array[wIndex]);
 625                                 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
 626                                                 XHCI_MAX_REXIT_TIMEOUT,
 627                                                 port_status);
 628                                 status |= USB_PORT_STAT_SUSPEND;
 629                                 clear_bit(wIndex, &bus_state->rexit_ports);
 630                         }
 631
 632                         bus_state->port_c_suspend |= 1 << wIndex;
 633                         bus_state->suspended_ports &= ~(1 << wIndex);
 634                 } else {
 635                         /*
 636                          * The resume has been signaling for less than
 637                          * 20ms. Report the port status as SUSPEND,
 638                          * let the usbcore check port status again
 639                          * and clear resume signaling later.
 640                          */
 641                         status |= USB_PORT_STAT_SUSPEND;
 642                 }
 643         }
 644         if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
 645                         && (raw_port_status & PORT_POWER)
 646                         && (bus_state->suspended_ports & (1 << wIndex))) {
 647                 bus_state->suspended_ports &= ~(1 << wIndex);
 648                 if (hcd->speed != HCD_USB3)
 649                         bus_state->port_c_suspend |= 1 << wIndex;
 650         }
 651         if (raw_port_status & PORT_CONNECT) {
 652                 status |= USB_PORT_STAT_CONNECTION;
 653                 status |= xhci_port_speed(raw_port_status);
 654         }
 655         if (raw_port_status & PORT_PE)
 656                 status |= USB_PORT_STAT_ENABLE;
 657         if (raw_port_status & PORT_OC)
 658                 status |= USB_PORT_STAT_OVERCURRENT;
 659         if (raw_port_status & PORT_RESET)
 660                 status |= USB_PORT_STAT_RESET;
 661         if (raw_port_status & PORT_POWER) {
 662                 if (hcd->speed == HCD_USB3)
 663                         status |= USB_SS_PORT_STAT_POWER;
 664                 else
 665                         status |= USB_PORT_STAT_POWER;
 666         }
 667         /* Update Port Link State */
 668         if (hcd->speed == HCD_USB3) {
 669                 xhci_hub_report_usb3_link_state(&status, raw_port_status);
 670                 /*
 671                  * Verify if all USB3 Ports Have entered U0 already.
 672                  * Delete Compliance Mode Timer if so.
 673                  */
 674                 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
 675         } else {
 676                 xhci_hub_report_usb2_link_state(&status, raw_port_status);
 677         }
 678         if (bus_state->port_c_suspend & (1 << wIndex))
 679                 status |= 1 << USB_PORT_FEAT_C_SUSPEND;
 680
 681         return status;
 682 }
 683
 684 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
 685                 u16 wIndex, char *buf, u16 wLength)
 686 {
 687         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
 688         int max_ports;
 689         unsigned long flags;
 690         u32 temp, status;
 691         int retval = 0;
 692         __le32 __iomem **port_array;
 693         int slot_id;
 694         struct xhci_bus_state *bus_state;
 695         u16 link_state = 0;
 696         u16 wake_mask = 0;
 697         u16 timeout = 0;
 698
 699         max_ports = xhci_get_ports(hcd, &port_array);
 700         bus_state = &xhci->bus_state[hcd_index(hcd)];
 701
 702         spin_lock_irqsave(&xhci->lock, flags);
 703         switch (typeReq) {
 704         case GetHubStatus:
 705                 /* No power source, over-current reported per port */
 706                 memset(buf, 0, 4);
 707                 break;
 708         case GetHubDescriptor:
 709                 /* Check to make sure userspace is asking for the USB 3.0 hub
 710                  * descriptor for the USB 3.0 roothub.  If not, we stall the
 711                  * endpoint, like external hubs do.
 712                  */
 713                 if (hcd->speed == HCD_USB3 &&
 714                                 (wLength < USB_DT_SS_HUB_SIZE ||
 715                                  wValue != (USB_DT_SS_HUB << 8))) {
 716                         xhci_dbg(xhci, "Wrong hub descriptor type for "
 717                                         "USB 3.0 roothub.\n");
 718                         goto error;
 719                 }
 720                 xhci_hub_descriptor(hcd, xhci,
 721                                 (struct usb_hub_descriptor *) buf);
 722                 break;
 723         case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
 724                 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
 725                         goto error;
 726
 727                 if (hcd->speed != HCD_USB3)
 728                         goto error;
 729
 730                 /* Set the U1 and U2 exit latencies. */
 731                 memcpy(buf, &usb_bos_descriptor,
 732                                 USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
 733                 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
 734                         temp = readl(&xhci->cap_regs->hcs_params3);
 735                         buf[12] = HCS_U1_LATENCY(temp);
 736                         put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
 737                 }
 738
 739                 /* Indicate whether the host has LTM support. */
 740                 temp = readl(&xhci->cap_regs->hcc_params);
 741                 if (HCC_LTC(temp))
 742                         buf[8] |= USB_LTM_SUPPORT;
 743
 744                 spin_unlock_irqrestore(&xhci->lock, flags);
 745                 return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
 746         case GetPortStatus:
 747                 if (!wIndex || wIndex > max_ports)
 748                         goto error;
 749                 wIndex--;
 750                 temp = readl(port_array[wIndex]);
 751                 if (temp == 0xffffffff) {
 752                         retval = -ENODEV;
 753                         break;
 754                 }
 755                 status = xhci_get_port_status(hcd, bus_state, port_array,
 756                                 wIndex, temp, flags);
 757                 if (status == 0xffffffff)
 758                         goto error;
 759
 760                 xhci_dbg(xhci, "get port status, actual port %d status  = 0x%x\n",
 761                                 wIndex, temp);
 762                 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
 763
 764                 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
 765                 break;
 766         case SetPortFeature:
 767                 if (wValue == USB_PORT_FEAT_LINK_STATE)
 768                         link_state = (wIndex & 0xff00) >> 3;
 769                 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
 770                         wake_mask = wIndex & 0xff00;
 771                 /* The MSB of wIndex is the U1/U2 timeout */
 772                 timeout = (wIndex & 0xff00) >> 8;
 773                 wIndex &= 0xff;
 774                 if (!wIndex || wIndex > max_ports)
 775                         goto error;
 776                 wIndex--;
 777                 temp = readl(port_array[wIndex]);
 778                 if (temp == 0xffffffff) {
 779                         retval = -ENODEV;
 780                         break;
 781                 }
 782                 temp = xhci_port_state_to_neutral(temp);
 783                 /* FIXME: What new port features do we need to support? */
 784                 switch (wValue) {
 785                 case USB_PORT_FEAT_SUSPEND:
 786                         temp = readl(port_array[wIndex]);
 787                         if ((temp & PORT_PLS_MASK) != XDEV_U0) {
 788                                 /* Resume the port to U0 first */
 789                                 xhci_set_link_state(xhci, port_array, wIndex,
 790                                                         XDEV_U0);
 791                                 spin_unlock_irqrestore(&xhci->lock, flags);
 792                                 msleep(10);
 793                                 spin_lock_irqsave(&xhci->lock, flags);
 794                         }
 795                         /* In spec software should not attempt to suspend
 796                          * a port unless the port reports that it is in the
 797                          * enabled (PED = ‘1’,PLS < ‘3’) state.
 798                          */
 799                         temp = readl(port_array[wIndex]);
 800                         if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
 801                                 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
 802                                 xhci_warn(xhci, "USB core suspending device "
 803                                           "not in U0/U1/U2.\n");
 804                                 goto error;
 805                         }
 806
 807                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 808                                         wIndex + 1);
 809                         if (!slot_id) {
 810                                 xhci_warn(xhci, "slot_id is zero\n");
 811                                 goto error;
 812                         }
 813                         /* unlock to execute stop endpoint commands */
 814                         spin_unlock_irqrestore(&xhci->lock, flags);
 815                         xhci_stop_device(xhci, slot_id, 1);
 816                         spin_lock_irqsave(&xhci->lock, flags);
 817
 818                         xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
 819
 820                         spin_unlock_irqrestore(&xhci->lock, flags);
 821                         msleep(10); /* wait device to enter */
 822                         spin_lock_irqsave(&xhci->lock, flags);
 823
 824                         temp = readl(port_array[wIndex]);
 825                         bus_state->suspended_ports |= 1 << wIndex;
 826                         break;
 827                 case USB_PORT_FEAT_LINK_STATE:
 828                         temp = readl(port_array[wIndex]);
 829
 830                         /* Disable port */
 831                         if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
 832                                 xhci_dbg(xhci, "Disable port %d\n", wIndex);
 833                                 temp = xhci_port_state_to_neutral(temp);
 834                                 /*
 835                                  * Clear all change bits, so that we get a new
 836                                  * connection event.
 837                                  */
 838                                 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
 839                                         PORT_OCC | PORT_RC | PORT_PLC |
 840                                         PORT_CEC;
 841                                 writel(temp | PORT_PE, port_array[wIndex]);
 842                                 temp = readl(port_array[wIndex]);
 843                                 break;
 844                         }
 845
 846                         /* Put link in RxDetect (enable port) */
 847                         if (link_state == USB_SS_PORT_LS_RX_DETECT) {
 848                                 xhci_dbg(xhci, "Enable port %d\n", wIndex);
 849                                 xhci_set_link_state(xhci, port_array, wIndex,
 850                                                 link_state);
 851                                 temp = readl(port_array[wIndex]);
 852                                 break;
 853                         }
 854
 855                         /* Software should not attempt to set
 856                          * port link state above '3' (U3) and the port
 857                          * must be enabled.
 858                          */
 859                         if ((temp & PORT_PE) == 0 ||
 860                                 (link_state > USB_SS_PORT_LS_U3)) {
 861                                 xhci_warn(xhci, "Cannot set link state.\n");
 862                                 goto error;
 863                         }
 864
 865                         if (link_state == USB_SS_PORT_LS_U3) {
 866                                 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 867                                                 wIndex + 1);
 868                                 if (slot_id) {
 869                                         /* unlock to execute stop endpoint
 870                                          * commands */
 871                                         spin_unlock_irqrestore(&xhci->lock,
 872                                                                 flags);
 873                                         xhci_stop_device(xhci, slot_id, 1);
 874                                         spin_lock_irqsave(&xhci->lock, flags);
 875                                 }
 876                         }
 877
 878                         xhci_set_link_state(xhci, port_array, wIndex,
 879                                                 link_state);
 880
 881                         spin_unlock_irqrestore(&xhci->lock, flags);
 882                         msleep(20); /* wait device to enter */
 883                         spin_lock_irqsave(&xhci->lock, flags);
 884
 885                         temp = readl(port_array[wIndex]);
 886                         if (link_state == USB_SS_PORT_LS_U3)
 887                                 bus_state->suspended_ports |= 1 << wIndex;
 888                         break;
 889                 case USB_PORT_FEAT_POWER:
 890                         /*
 891                          * Turn on ports, even if there isn't per-port switching.
 892                          * HC will report connect events even before this is set.
 893                          * However, khubd will ignore the roothub events until
 894                          * the roothub is registered.
 895                          */
 896                         writel(temp | PORT_POWER, port_array[wIndex]);
 897
 898                         temp = readl(port_array[wIndex]);
 899                         xhci_dbg(xhci, "set port power, actual port %d status  = 0x%x\n", wIndex, temp);
 900
 901                         spin_unlock_irqrestore(&xhci->lock, flags);
 902                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
 903                                         wIndex);
 904                         if (temp)
 905                                 usb_acpi_set_power_state(hcd->self.root_hub,
 906                                                 wIndex, true);
 907                         spin_lock_irqsave(&xhci->lock, flags);
 908                         break;
 909                 case USB_PORT_FEAT_RESET:
 910                         temp = (temp | PORT_RESET);
 911                         writel(temp, port_array[wIndex]);
 912
 913                         temp = readl(port_array[wIndex]);
 914                         xhci_dbg(xhci, "set port reset, actual port %d status  = 0x%x\n", wIndex, temp);
 915                         break;
 916                 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
 917                         xhci_set_remote_wake_mask(xhci, port_array,
 918                                         wIndex, wake_mask);
 919                         temp = readl(port_array[wIndex]);
 920                         xhci_dbg(xhci, "set port remote wake mask, "
 921                                         "actual port %d status  = 0x%x\n",
 922                                         wIndex, temp);
 923                         break;
 924                 case USB_PORT_FEAT_BH_PORT_RESET:
 925                         temp |= PORT_WR;
 926                         writel(temp, port_array[wIndex]);
 927
 928                         temp = readl(port_array[wIndex]);
 929                         break;
 930                 case USB_PORT_FEAT_U1_TIMEOUT:
 931                         if (hcd->speed != HCD_USB3)
 932                                 goto error;
 933                         temp = readl(port_array[wIndex] + PORTPMSC);
 934                         temp &= ~PORT_U1_TIMEOUT_MASK;
 935                         temp |= PORT_U1_TIMEOUT(timeout);
 936                         writel(temp, port_array[wIndex] + PORTPMSC);
 937                         break;
 938                 case USB_PORT_FEAT_U2_TIMEOUT:
 939                         if (hcd->speed != HCD_USB3)
 940                                 goto error;
 941                         temp = readl(port_array[wIndex] + PORTPMSC);
 942                         temp &= ~PORT_U2_TIMEOUT_MASK;
 943                         temp |= PORT_U2_TIMEOUT(timeout);
 944                         writel(temp, port_array[wIndex] + PORTPMSC);
 945                         break;
 946                 default:
 947                         goto error;
 948                 }
 949                 /* unblock any posted writes */
 950                 temp = readl(port_array[wIndex]);
 951                 break;
 952         case ClearPortFeature:
 953                 if (!wIndex || wIndex > max_ports)
 954                         goto error;
 955                 wIndex--;
 956                 temp = readl(port_array[wIndex]);
 957                 if (temp == 0xffffffff) {
 958                         retval = -ENODEV;
 959                         break;
 960                 }
 961                 /* FIXME: What new port features do we need to support? */
 962                 temp = xhci_port_state_to_neutral(temp);
 963                 switch (wValue) {
 964                 case USB_PORT_FEAT_SUSPEND:
 965                         temp = readl(port_array[wIndex]);
 966                         xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
 967                         xhci_dbg(xhci, "PORTSC %04x\n", temp);
 968                         if (temp & PORT_RESET)
 969                                 goto error;
 970                         if ((temp & PORT_PLS_MASK) == XDEV_U3) {
 971                                 if ((temp & PORT_PE) == 0)
 972                                         goto error;
 973
 974                                 xhci_set_link_state(xhci, port_array, wIndex,
 975                                                         XDEV_RESUME);
 976                                 spin_unlock_irqrestore(&xhci->lock, flags);
 977                                 msleep(20);
 978                                 spin_lock_irqsave(&xhci->lock, flags);
 979                                 xhci_set_link_state(xhci, port_array, wIndex,
 980                                                         XDEV_U0);
 981                         }
 982                         bus_state->port_c_suspend |= 1 << wIndex;
 983
 984                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
 985                                         wIndex + 1);
 986                         if (!slot_id) {
 987                                 xhci_dbg(xhci, "slot_id is zero\n");
 988                                 goto error;
 989                         }
 990                         xhci_ring_device(xhci, slot_id);
 991                         break;
 992                 case USB_PORT_FEAT_C_SUSPEND:
 993                         bus_state->port_c_suspend &= ~(1 << wIndex);
 994                 case USB_PORT_FEAT_C_RESET:
 995                 case USB_PORT_FEAT_C_BH_PORT_RESET:
 996                 case USB_PORT_FEAT_C_CONNECTION:
 997                 case USB_PORT_FEAT_C_OVER_CURRENT:
 998                 case USB_PORT_FEAT_C_ENABLE:
 999                 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1000                         xhci_clear_port_change_bit(xhci, wValue, wIndex,
1001                                         port_array[wIndex], temp);
1002                         break;
1003                 case USB_PORT_FEAT_ENABLE:
1004                         xhci_disable_port(hcd, xhci, wIndex,
1005                                         port_array[wIndex], temp);
1006                         break;
1007                 case USB_PORT_FEAT_POWER:
1008                         writel(temp & ~PORT_POWER, port_array[wIndex]);
1009
1010                         spin_unlock_irqrestore(&xhci->lock, flags);
1011                         temp = usb_acpi_power_manageable(hcd->self.root_hub,
1012                                         wIndex);
1013                         if (temp)
1014                                 usb_acpi_set_power_state(hcd->self.root_hub,
1015                                                 wIndex, false);
1016                         spin_lock_irqsave(&xhci->lock, flags);
1017                         break;
1018                 default:
1019                         goto error;
1020                 }
1021                 break;
1022         default:
1023 error:
1024                 /* "stall" on error */
1025                 retval = -EPIPE;
1026         }
1027         spin_unlock_irqrestore(&xhci->lock, flags);
1028         return retval;
1029 }
1030
1031 /*
1032  * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1033  * Ports are 0-indexed from the HCD point of view,
1034  * and 1-indexed from the USB core pointer of view.
1035  *
1036  * Note that the status change bits will be cleared as soon as a port status
1037  * change event is generated, so we use the saved status from that event.
1038  */
1039 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1040 {
1041         unsigned long flags;
1042         u32 temp, status;
1043         u32 mask;
1044         int i, retval;
1045         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1046         int max_ports;
1047         __le32 __iomem **port_array;
1048         struct xhci_bus_state *bus_state;
1049         bool reset_change = false;
1050
1051         max_ports = xhci_get_ports(hcd, &port_array);
1052         bus_state = &xhci->bus_state[hcd_index(hcd)];
1053
1054         /* Initial status is no changes */
1055         retval = (max_ports + 8) / 8;
1056         memset(buf, 0, retval);
1057
1058         /*
1059          * Inform the usbcore about resume-in-progress by returning
1060          * a non-zero value even if there are no status changes.
1061          */
1062         status = bus_state->resuming_ports;
1063
1064         mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC;
1065
1066         spin_lock_irqsave(&xhci->lock, flags);
1067         /* For each port, did anything change?  If so, set that bit in buf. */
1068         for (i = 0; i < max_ports; i++) {
1069                 temp = readl(port_array[i]);
1070                 if (temp == 0xffffffff) {
1071                         retval = -ENODEV;
1072                         break;
1073                 }
1074                 if ((temp & mask) != 0 ||
1075                         (bus_state->port_c_suspend & 1 << i) ||
1076                         (bus_state->resume_done[i] && time_after_eq(
1077                             jiffies, bus_state->resume_done[i]))) {
1078                         buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1079                         status = 1;
1080                 }
1081                 if ((temp & PORT_RC))
1082                         reset_change = true;
1083         }
1084         if (!status && !reset_change) {
1085                 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1086                 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1087         }
1088         spin_unlock_irqrestore(&xhci->lock, flags);
1089         return status ? retval : 0;
1090 }
1091
1092 #ifdef CONFIG_PM
1093
1094 int xhci_bus_suspend(struct usb_hcd *hcd)
1095 {
1096         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1097         int max_ports, port_index;
1098         __le32 __iomem **port_array;
1099         struct xhci_bus_state *bus_state;
1100         unsigned long flags;
1101
1102         max_ports = xhci_get_ports(hcd, &port_array);
1103         bus_state = &xhci->bus_state[hcd_index(hcd)];
1104
1105         spin_lock_irqsave(&xhci->lock, flags);
1106
1107         if (hcd->self.root_hub->do_remote_wakeup) {
1108                 if (bus_state->resuming_ports) {
1109                         spin_unlock_irqrestore(&xhci->lock, flags);
1110                         xhci_dbg(xhci, "suspend failed because "
1111                                                 "a port is resuming\n");
1112                         return -EBUSY;
1113                 }
1114         }
1115
1116         port_index = max_ports;
1117         bus_state->bus_suspended = 0;
1118         while (port_index--) {
1119                 /* suspend the port if the port is not suspended */
1120                 u32 t1, t2;
1121                 int slot_id;
1122
1123                 t1 = readl(port_array[port_index]);
1124                 t2 = xhci_port_state_to_neutral(t1);
1125
1126                 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1127                         xhci_dbg(xhci, "port %d not suspended\n", port_index);
1128                         slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1129                                         port_index + 1);
1130                         if (slot_id) {
1131                                 spin_unlock_irqrestore(&xhci->lock, flags);
1132                                 xhci_stop_device(xhci, slot_id, 1);
1133                                 spin_lock_irqsave(&xhci->lock, flags);
1134                         }
1135                         t2 &= ~PORT_PLS_MASK;
1136                         t2 |= PORT_LINK_STROBE | XDEV_U3;
1137                         set_bit(port_index, &bus_state->bus_suspended);
1138                 }
1139                 /* USB core sets remote wake mask for USB 3.0 hubs,
1140                  * including the USB 3.0 roothub, but only if CONFIG_PM_RUNTIME
1141                  * is enabled, so also enable remote wake here.
1142                  */
1143                 if (hcd->self.root_hub->do_remote_wakeup
1144                                 && device_may_wakeup(hcd->self.controller)) {
1145
1146                         if (t1 & PORT_CONNECT) {
1147                                 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1148                                 t2 &= ~PORT_WKCONN_E;
1149                         } else {
1150                                 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1151                                 t2 &= ~PORT_WKDISC_E;
1152                         }
1153                 } else
1154                         t2 &= ~PORT_WAKE_BITS;
1155
1156                 t1 = xhci_port_state_to_neutral(t1);
1157                 if (t1 != t2)
1158                         writel(t2, port_array[port_index]);
1159         }
1160         hcd->state = HC_STATE_SUSPENDED;
1161         bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1162         spin_unlock_irqrestore(&xhci->lock, flags);
1163         return 0;
1164 }
1165
1166 int xhci_bus_resume(struct usb_hcd *hcd)
1167 {
1168         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1169         int max_ports, port_index;
1170         __le32 __iomem **port_array;
1171         struct xhci_bus_state *bus_state;
1172         u32 temp;
1173         unsigned long flags;
1174
1175         max_ports = xhci_get_ports(hcd, &port_array);
1176         bus_state = &xhci->bus_state[hcd_index(hcd)];
1177
1178         if (time_before(jiffies, bus_state->next_statechange))
1179                 msleep(5);
1180
1181         spin_lock_irqsave(&xhci->lock, flags);
1182         if (!HCD_HW_ACCESSIBLE(hcd)) {
1183                 spin_unlock_irqrestore(&xhci->lock, flags);
1184                 return -ESHUTDOWN;
1185         }
1186
1187         /* delay the irqs */
1188         temp = readl(&xhci->op_regs->command);
1189         temp &= ~CMD_EIE;
1190         writel(temp, &xhci->op_regs->command);
1191
1192         port_index = max_ports;
1193         while (port_index--) {
1194                 /* Check whether need resume ports. If needed
1195                    resume port and disable remote wakeup */
1196                 u32 temp;
1197                 int slot_id;
1198
1199                 temp = readl(port_array[port_index]);
1200                 if (DEV_SUPERSPEED(temp))
1201                         temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1202                 else
1203                         temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1204                 if (test_bit(port_index, &bus_state->bus_suspended) &&
1205                     (temp & PORT_PLS_MASK)) {
1206                         if (DEV_SUPERSPEED(temp)) {
1207                                 xhci_set_link_state(xhci, port_array,
1208                                                         port_index, XDEV_U0);
1209                         } else {
1210                                 xhci_set_link_state(xhci, port_array,
1211                                                 port_index, XDEV_RESUME);
1212
1213                                 spin_unlock_irqrestore(&xhci->lock, flags);
1214                                 msleep(20);
1215                                 spin_lock_irqsave(&xhci->lock, flags);
1216
1217                                 xhci_set_link_state(xhci, port_array,
1218                                                         port_index, XDEV_U0);
1219                         }
1220                         /* wait for the port to enter U0 and report port link
1221                          * state change.
1222                          */
1223                         spin_unlock_irqrestore(&xhci->lock, flags);
1224                         msleep(20);
1225                         spin_lock_irqsave(&xhci->lock, flags);
1226
1227                         /* Clear PLC */
1228                         xhci_test_and_clear_bit(xhci, port_array, port_index,
1229                                                 PORT_PLC);
1230
1231                         slot_id = xhci_find_slot_id_by_port(hcd,
1232                                         xhci, port_index + 1);
1233                         if (slot_id)
1234                                 xhci_ring_device(xhci, slot_id);
1235                 } else
1236                         writel(temp, port_array[port_index]);
1237         }
1238
1239         (void) readl(&xhci->op_regs->command);
1240
1241         bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1242         /* re-enable irqs */
1243         temp = readl(&xhci->op_regs->command);
1244         temp |= CMD_EIE;
1245         writel(temp, &xhci->op_regs->command);
1246         temp = readl(&xhci->op_regs->command);
1247
1248         spin_unlock_irqrestore(&xhci->lock, flags);
1249         return 0;
1250 }
1251
1252 #endif  /* CONFIG_PM */