2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/interrupt.h>
27 #include <linux/dmi.h>
29 #include <linux/dmaengine.h>
30 #include <linux/pch_dma.h>
33 PCH_UART_HANDLED_RX_INT_SHIFT,
34 PCH_UART_HANDLED_TX_INT_SHIFT,
35 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
36 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
37 PCH_UART_HANDLED_MS_INT_SHIFT,
45 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
47 /* Set the max number of UART port
48 * Intel EG20T PCH: 4 port
49 * LAPIS Semiconductor ML7213 IOH: 3 port
50 * LAPIS Semiconductor ML7223 IOH: 2 port
54 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
55 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
56 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
57 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
58 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
59 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
60 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
62 #define PCH_UART_RBR 0x00
63 #define PCH_UART_THR 0x00
65 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
66 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
67 #define PCH_UART_IER_ERBFI 0x00000001
68 #define PCH_UART_IER_ETBEI 0x00000002
69 #define PCH_UART_IER_ELSI 0x00000004
70 #define PCH_UART_IER_EDSSI 0x00000008
72 #define PCH_UART_IIR_IP 0x00000001
73 #define PCH_UART_IIR_IID 0x00000006
74 #define PCH_UART_IIR_MSI 0x00000000
75 #define PCH_UART_IIR_TRI 0x00000002
76 #define PCH_UART_IIR_RRI 0x00000004
77 #define PCH_UART_IIR_REI 0x00000006
78 #define PCH_UART_IIR_TOI 0x00000008
79 #define PCH_UART_IIR_FIFO256 0x00000020
80 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
81 #define PCH_UART_IIR_FE 0x000000C0
83 #define PCH_UART_FCR_FIFOE 0x00000001
84 #define PCH_UART_FCR_RFR 0x00000002
85 #define PCH_UART_FCR_TFR 0x00000004
86 #define PCH_UART_FCR_DMS 0x00000008
87 #define PCH_UART_FCR_FIFO256 0x00000020
88 #define PCH_UART_FCR_RFTL 0x000000C0
90 #define PCH_UART_FCR_RFTL1 0x00000000
91 #define PCH_UART_FCR_RFTL64 0x00000040
92 #define PCH_UART_FCR_RFTL128 0x00000080
93 #define PCH_UART_FCR_RFTL224 0x000000C0
94 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
95 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
96 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
97 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
98 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
99 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
100 #define PCH_UART_FCR_RFTL_SHIFT 6
102 #define PCH_UART_LCR_WLS 0x00000003
103 #define PCH_UART_LCR_STB 0x00000004
104 #define PCH_UART_LCR_PEN 0x00000008
105 #define PCH_UART_LCR_EPS 0x00000010
106 #define PCH_UART_LCR_SP 0x00000020
107 #define PCH_UART_LCR_SB 0x00000040
108 #define PCH_UART_LCR_DLAB 0x00000080
109 #define PCH_UART_LCR_NP 0x00000000
110 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
111 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
112 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
113 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
116 #define PCH_UART_LCR_5BIT 0x00000000
117 #define PCH_UART_LCR_6BIT 0x00000001
118 #define PCH_UART_LCR_7BIT 0x00000002
119 #define PCH_UART_LCR_8BIT 0x00000003
121 #define PCH_UART_MCR_DTR 0x00000001
122 #define PCH_UART_MCR_RTS 0x00000002
123 #define PCH_UART_MCR_OUT 0x0000000C
124 #define PCH_UART_MCR_LOOP 0x00000010
125 #define PCH_UART_MCR_AFE 0x00000020
127 #define PCH_UART_LSR_DR 0x00000001
128 #define PCH_UART_LSR_ERR (1<<7)
130 #define PCH_UART_MSR_DCTS 0x00000001
131 #define PCH_UART_MSR_DDSR 0x00000002
132 #define PCH_UART_MSR_TERI 0x00000004
133 #define PCH_UART_MSR_DDCD 0x00000008
134 #define PCH_UART_MSR_CTS 0x00000010
135 #define PCH_UART_MSR_DSR 0x00000020
136 #define PCH_UART_MSR_RI 0x00000040
137 #define PCH_UART_MSR_DCD 0x00000080
138 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
139 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
141 #define PCH_UART_DLL 0x00
142 #define PCH_UART_DLM 0x01
144 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
145 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
146 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
147 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
148 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
150 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
151 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
152 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
153 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
154 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
155 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
156 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
157 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
158 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
159 #define PCH_UART_HAL_STB1 0
160 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
162 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
163 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
164 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
165 PCH_UART_HAL_CLR_RX_FIFO)
167 #define PCH_UART_HAL_DMA_MODE0 0
168 #define PCH_UART_HAL_FIFO_DIS 0
169 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
170 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
171 PCH_UART_FCR_FIFO256)
172 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
173 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
174 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
175 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
176 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
177 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
178 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
179 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
180 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
181 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
182 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
183 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
184 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
185 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
187 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
188 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
189 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
190 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
191 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
193 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
194 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
195 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
196 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
197 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
199 #define PCI_VENDOR_ID_ROHM 0x10DB
201 struct pch_uart_buffer {
207 struct uart_port port;
209 void __iomem *membase;
210 resource_size_t mapbase;
212 struct pci_dev *pdev;
221 struct pch_uart_buffer rxbuf;
225 unsigned int use_dma;
226 unsigned int use_dma_flag;
227 struct dma_async_tx_descriptor *desc_tx;
228 struct dma_async_tx_descriptor *desc_rx;
229 struct pch_dma_slave param_tx;
230 struct pch_dma_slave param_rx;
231 struct dma_chan *chan_tx;
232 struct dma_chan *chan_rx;
233 struct scatterlist *sg_tx_p;
235 struct scatterlist sg_rx;
238 dma_addr_t rx_buf_dma;
240 /* protect the eg20t_port private structure and io access to membase */
245 * struct pch_uart_driver_data - private data structure for UART-DMA
246 * @port_type: The number of DMA channel
247 * @line_no: UART port line number (0, 1, 2...)
249 struct pch_uart_driver_data {
254 enum pch_uart_num_t {
268 static struct pch_uart_driver_data drv_dat[] = {
269 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
270 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
271 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
272 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
273 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
274 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
275 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
276 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
277 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
278 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
279 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
282 static unsigned int default_baud = 9600;
283 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
284 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
285 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
286 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
288 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
291 struct eg20t_port *priv = pci_get_drvdata(pdev);
293 priv->trigger_level = 1;
297 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
299 unsigned int msr = ioread8(base + UART_MSR);
300 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
305 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
308 u8 ier = ioread8(priv->membase + UART_IER);
309 ier |= flag & PCH_UART_IER_MASK;
310 iowrite8(ier, priv->membase + UART_IER);
313 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
316 u8 ier = ioread8(priv->membase + UART_IER);
317 ier &= ~(flag & PCH_UART_IER_MASK);
318 iowrite8(ier, priv->membase + UART_IER);
321 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
322 unsigned int parity, unsigned int bits,
325 unsigned int dll, dlm, lcr;
328 div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
329 if (div < 0 || USHRT_MAX <= div) {
330 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
334 dll = (unsigned int)div & 0x00FFU;
335 dlm = ((unsigned int)div >> 8) & 0x00FFU;
337 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
338 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
342 if (bits & ~PCH_UART_LCR_WLS) {
343 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
347 if (stb & ~PCH_UART_LCR_STB) {
348 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
356 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
357 __func__, baud, div, lcr, jiffies);
358 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
359 iowrite8(dll, priv->membase + PCH_UART_DLL);
360 iowrite8(dlm, priv->membase + PCH_UART_DLM);
361 iowrite8(lcr, priv->membase + UART_LCR);
366 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
369 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
370 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
375 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
376 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
377 priv->membase + UART_FCR);
378 iowrite8(priv->fcr, priv->membase + UART_FCR);
383 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
384 unsigned int dmamode,
385 unsigned int fifo_size, unsigned int trigger)
389 if (dmamode & ~PCH_UART_FCR_DMS) {
390 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
395 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
396 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
397 __func__, fifo_size);
401 if (trigger & ~PCH_UART_FCR_RFTL) {
402 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
407 switch (priv->fifo_size) {
409 priv->trigger_level =
410 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
413 priv->trigger_level =
414 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
417 priv->trigger_level =
418 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
421 priv->trigger_level =
422 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
426 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
427 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
428 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
429 priv->membase + UART_FCR);
430 iowrite8(fcr, priv->membase + UART_FCR);
436 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
439 return get_msr(priv, priv->membase);
442 static void pch_uart_hal_write(struct eg20t_port *priv,
443 const unsigned char *buf, int tx_size)
448 for (i = 0; i < tx_size;) {
450 iowrite8(thr, priv->membase + PCH_UART_THR);
454 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
460 lsr = ioread8(priv->membase + UART_LSR);
461 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
462 i < rx_size && lsr & UART_LSR_DR;
463 lsr = ioread8(priv->membase + UART_LSR)) {
464 rbr = ioread8(priv->membase + PCH_UART_RBR);
470 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
475 iir = ioread8(priv->membase + UART_IIR);
476 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
480 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
482 return ioread8(priv->membase + UART_LSR);
485 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
489 lcr = ioread8(priv->membase + UART_LCR);
491 lcr |= PCH_UART_LCR_SB;
493 lcr &= ~PCH_UART_LCR_SB;
495 iowrite8(lcr, priv->membase + UART_LCR);
498 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
501 struct uart_port *port;
502 struct tty_struct *tty;
505 tty = tty_port_tty_get(&port->state->port);
507 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
511 tty_insert_flip_string(tty, buf, size);
512 tty_flip_buffer_push(tty);
518 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
521 struct uart_port *port = &priv->port;
524 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
525 __func__, port->x_char, jiffies);
526 buf[0] = port->x_char;
536 static int dma_push_rx(struct eg20t_port *priv, int size)
538 struct tty_struct *tty;
540 struct uart_port *port = &priv->port;
543 tty = tty_port_tty_get(&port->state->port);
545 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
549 room = tty_buffer_request_room(tty, size);
552 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
557 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
559 port->icount.rx += room;
565 static void pch_free_dma(struct uart_port *port)
567 struct eg20t_port *priv;
568 priv = container_of(port, struct eg20t_port, port);
571 dma_release_channel(priv->chan_tx);
572 priv->chan_tx = NULL;
575 dma_release_channel(priv->chan_rx);
576 priv->chan_rx = NULL;
578 if (sg_dma_address(&priv->sg_rx))
579 dma_free_coherent(port->dev, port->fifosize,
580 sg_virt(&priv->sg_rx),
581 sg_dma_address(&priv->sg_rx));
586 static bool filter(struct dma_chan *chan, void *slave)
588 struct pch_dma_slave *param = slave;
590 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
591 chan->device->dev)) {
592 chan->private = param;
599 static void pch_request_dma(struct uart_port *port)
602 struct dma_chan *chan;
603 struct pci_dev *dma_dev;
604 struct pch_dma_slave *param;
605 struct eg20t_port *priv =
606 container_of(port, struct eg20t_port, port);
608 dma_cap_set(DMA_SLAVE, mask);
610 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
611 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
614 param = &priv->param_tx;
615 param->dma_dev = &dma_dev->dev;
616 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
618 param->tx_reg = port->mapbase + UART_TX;
619 chan = dma_request_channel(mask, filter, param);
621 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
625 priv->chan_tx = chan;
628 param = &priv->param_rx;
629 param->dma_dev = &dma_dev->dev;
630 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
632 param->rx_reg = port->mapbase + UART_RX;
633 chan = dma_request_channel(mask, filter, param);
635 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
637 dma_release_channel(priv->chan_tx);
638 priv->chan_tx = NULL;
642 /* Get Consistent memory for DMA */
643 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
644 &priv->rx_buf_dma, GFP_KERNEL);
645 priv->chan_rx = chan;
648 static void pch_dma_rx_complete(void *arg)
650 struct eg20t_port *priv = arg;
651 struct uart_port *port = &priv->port;
652 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
656 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
660 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
661 count = dma_push_rx(priv, priv->trigger_level);
663 tty_flip_buffer_push(tty);
665 async_tx_ack(priv->desc_rx);
666 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
667 PCH_UART_HAL_RX_ERR_INT);
670 static void pch_dma_tx_complete(void *arg)
672 struct eg20t_port *priv = arg;
673 struct uart_port *port = &priv->port;
674 struct circ_buf *xmit = &port->state->xmit;
675 struct scatterlist *sg = priv->sg_tx_p;
678 for (i = 0; i < priv->nent; i++, sg++) {
679 xmit->tail += sg_dma_len(sg);
680 port->icount.tx += sg_dma_len(sg);
682 xmit->tail &= UART_XMIT_SIZE - 1;
683 async_tx_ack(priv->desc_tx);
684 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
685 priv->tx_dma_use = 0;
687 kfree(priv->sg_tx_p);
688 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
691 static int pop_tx(struct eg20t_port *priv, int size)
694 struct uart_port *port = &priv->port;
695 struct circ_buf *xmit = &port->state->xmit;
697 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
702 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
703 int sz = min(size - count, cnt_to_end);
704 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
705 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
707 } while (!uart_circ_empty(xmit) && count < size);
710 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
711 count, size - count, jiffies);
716 static int handle_rx_to(struct eg20t_port *priv)
718 struct pch_uart_buffer *buf;
721 if (!priv->start_rx) {
722 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
723 PCH_UART_HAL_RX_ERR_INT);
728 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
729 ret = push_rx(priv, buf->buf, rx_size);
732 } while (rx_size == buf->size);
734 return PCH_UART_HANDLED_RX_INT;
737 static int handle_rx(struct eg20t_port *priv)
739 return handle_rx_to(priv);
742 static int dma_handle_rx(struct eg20t_port *priv)
744 struct uart_port *port = &priv->port;
745 struct dma_async_tx_descriptor *desc;
746 struct scatterlist *sg;
748 priv = container_of(port, struct eg20t_port, port);
751 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
753 sg_dma_len(sg) = priv->trigger_level;
755 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
756 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
759 sg_dma_address(sg) = priv->rx_buf_dma;
761 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
762 sg, 1, DMA_FROM_DEVICE,
763 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
768 priv->desc_rx = desc;
769 desc->callback = pch_dma_rx_complete;
770 desc->callback_param = priv;
771 desc->tx_submit(desc);
772 dma_async_issue_pending(priv->chan_rx);
774 return PCH_UART_HANDLED_RX_INT;
777 static unsigned int handle_tx(struct eg20t_port *priv)
779 struct uart_port *port = &priv->port;
780 struct circ_buf *xmit = &port->state->xmit;
786 if (!priv->start_tx) {
787 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
789 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
794 fifo_size = max(priv->fifo_size, 1);
796 if (pop_tx_x(priv, xmit->buf)) {
797 pch_uart_hal_write(priv, xmit->buf, 1);
802 size = min(xmit->head - xmit->tail, fifo_size);
806 tx_size = pop_tx(priv, size);
808 port->icount.tx += tx_size;
812 priv->tx_empty = tx_empty;
815 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
816 uart_write_wakeup(port);
819 return PCH_UART_HANDLED_TX_INT;
822 static unsigned int dma_handle_tx(struct eg20t_port *priv)
824 struct uart_port *port = &priv->port;
825 struct circ_buf *xmit = &port->state->xmit;
826 struct scatterlist *sg;
830 struct dma_async_tx_descriptor *desc;
837 if (!priv->start_tx) {
838 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
840 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
845 if (priv->tx_dma_use) {
846 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
848 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
853 fifo_size = max(priv->fifo_size, 1);
855 if (pop_tx_x(priv, xmit->buf)) {
856 pch_uart_hal_write(priv, xmit->buf, 1);
862 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
863 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
864 xmit->tail, UART_XMIT_SIZE));
866 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
867 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
868 uart_write_wakeup(port);
872 if (bytes > fifo_size) {
873 num = bytes / fifo_size + 1;
875 rem = bytes % fifo_size;
882 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
883 __func__, num, size, rem);
885 priv->tx_dma_use = 1;
887 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
889 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
892 for (i = 0; i < num; i++, sg++) {
894 sg_set_page(sg, virt_to_page(xmit->buf),
897 sg_set_page(sg, virt_to_page(xmit->buf),
898 size, fifo_size * i);
902 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
904 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
909 for (i = 0; i < nent; i++, sg++) {
910 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
912 sg_dma_address(sg) = (sg_dma_address(sg) &
913 ~(UART_XMIT_SIZE - 1)) + sg->offset;
915 sg_dma_len(sg) = rem;
917 sg_dma_len(sg) = size;
920 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
921 priv->sg_tx_p, nent, DMA_TO_DEVICE,
922 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
924 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
928 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
929 priv->desc_tx = desc;
930 desc->callback = pch_dma_tx_complete;
931 desc->callback_param = priv;
933 desc->tx_submit(desc);
935 dma_async_issue_pending(priv->chan_tx);
937 return PCH_UART_HANDLED_TX_INT;
940 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
942 u8 fcr = ioread8(priv->membase + UART_FCR);
943 struct uart_port *port = &priv->port;
944 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
945 char *error_msg[5] = {};
949 fcr |= UART_FCR_CLEAR_RCVR;
950 iowrite8(fcr, priv->membase + UART_FCR);
952 if (lsr & PCH_UART_LSR_ERR)
953 error_msg[i++] = "Error data in FIFO\n";
955 if (lsr & UART_LSR_FE) {
956 port->icount.frame++;
957 error_msg[i++] = " Framing Error\n";
960 if (lsr & UART_LSR_PE) {
961 port->icount.parity++;
962 error_msg[i++] = " Parity Error\n";
965 if (lsr & UART_LSR_OE) {
966 port->icount.overrun++;
967 error_msg[i++] = " Overrun Error\n";
971 for (i = 0; error_msg[i] != NULL; i++)
972 dev_err(&priv->pdev->dev, error_msg[i]);
976 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
978 struct eg20t_port *priv = dev_id;
979 unsigned int handled;
985 spin_lock_irqsave(&priv->lock, flags);
987 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
989 case PCH_UART_IID_RLS: /* Receiver Line Status */
990 lsr = pch_uart_hal_get_line_status(priv);
991 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
992 UART_LSR_PE | UART_LSR_OE)) {
993 pch_uart_err_ir(priv, lsr);
994 ret = PCH_UART_HANDLED_RX_ERR_INT;
997 case PCH_UART_IID_RDR: /* Received Data Ready */
999 pch_uart_hal_disable_interrupt(priv,
1000 PCH_UART_HAL_RX_INT |
1001 PCH_UART_HAL_RX_ERR_INT);
1002 ret = dma_handle_rx(priv);
1004 pch_uart_hal_enable_interrupt(priv,
1005 PCH_UART_HAL_RX_INT |
1006 PCH_UART_HAL_RX_ERR_INT);
1008 ret = handle_rx(priv);
1011 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1013 ret = handle_rx_to(priv);
1015 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1018 ret = dma_handle_tx(priv);
1020 ret = handle_tx(priv);
1022 case PCH_UART_IID_MS: /* Modem Status */
1023 ret = PCH_UART_HANDLED_MS_INT;
1025 default: /* Never junp to this label */
1026 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1031 handled |= (unsigned int)ret;
1033 if (handled == 0 && iid <= 1) {
1034 if (priv->int_dis_flag)
1035 priv->int_dis_flag = 0;
1038 spin_unlock_irqrestore(&priv->lock, flags);
1039 return IRQ_RETVAL(handled);
1042 /* This function tests whether the transmitter fifo and shifter for the port
1043 described by 'port' is empty. */
1044 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1046 struct eg20t_port *priv;
1048 priv = container_of(port, struct eg20t_port, port);
1057 /* Returns the current state of modem control inputs. */
1058 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1060 struct eg20t_port *priv;
1062 unsigned int ret = 0;
1064 priv = container_of(port, struct eg20t_port, port);
1065 modem = pch_uart_hal_get_modem(priv);
1067 if (modem & UART_MSR_DCD)
1070 if (modem & UART_MSR_RI)
1073 if (modem & UART_MSR_DSR)
1076 if (modem & UART_MSR_CTS)
1082 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1085 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1087 if (mctrl & TIOCM_DTR)
1088 mcr |= UART_MCR_DTR;
1089 if (mctrl & TIOCM_RTS)
1090 mcr |= UART_MCR_RTS;
1091 if (mctrl & TIOCM_LOOP)
1092 mcr |= UART_MCR_LOOP;
1094 if (priv->mcr & UART_MCR_AFE)
1095 mcr |= UART_MCR_AFE;
1098 iowrite8(mcr, priv->membase + UART_MCR);
1101 static void pch_uart_stop_tx(struct uart_port *port)
1103 struct eg20t_port *priv;
1104 priv = container_of(port, struct eg20t_port, port);
1106 priv->tx_dma_use = 0;
1109 static void pch_uart_start_tx(struct uart_port *port)
1111 struct eg20t_port *priv;
1113 priv = container_of(port, struct eg20t_port, port);
1115 if (priv->use_dma) {
1116 if (priv->tx_dma_use) {
1117 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1124 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1127 static void pch_uart_stop_rx(struct uart_port *port)
1129 struct eg20t_port *priv;
1130 priv = container_of(port, struct eg20t_port, port);
1132 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1133 PCH_UART_HAL_RX_ERR_INT);
1134 priv->int_dis_flag = 1;
1137 /* Enable the modem status interrupts. */
1138 static void pch_uart_enable_ms(struct uart_port *port)
1140 struct eg20t_port *priv;
1141 priv = container_of(port, struct eg20t_port, port);
1142 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1145 /* Control the transmission of a break signal. */
1146 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1148 struct eg20t_port *priv;
1149 unsigned long flags;
1151 priv = container_of(port, struct eg20t_port, port);
1152 spin_lock_irqsave(&priv->lock, flags);
1153 pch_uart_hal_set_break(priv, ctl);
1154 spin_unlock_irqrestore(&priv->lock, flags);
1157 /* Grab any interrupt resources and initialise any low level driver state. */
1158 static int pch_uart_startup(struct uart_port *port)
1160 struct eg20t_port *priv;
1165 priv = container_of(port, struct eg20t_port, port);
1169 priv->base_baud = port->uartclk;
1171 port->uartclk = priv->base_baud;
1173 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1174 ret = pch_uart_hal_set_line(priv, default_baud,
1175 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1180 switch (priv->fifo_size) {
1182 fifo_size = PCH_UART_HAL_FIFO256;
1185 fifo_size = PCH_UART_HAL_FIFO64;
1188 fifo_size = PCH_UART_HAL_FIFO16;
1192 fifo_size = PCH_UART_HAL_FIFO_DIS;
1196 switch (priv->trigger) {
1197 case PCH_UART_HAL_TRIGGER1:
1200 case PCH_UART_HAL_TRIGGER_L:
1201 trigger_level = priv->fifo_size / 4;
1203 case PCH_UART_HAL_TRIGGER_M:
1204 trigger_level = priv->fifo_size / 2;
1206 case PCH_UART_HAL_TRIGGER_H:
1208 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1212 priv->trigger_level = trigger_level;
1213 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1214 fifo_size, priv->trigger);
1218 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1219 KBUILD_MODNAME, priv);
1224 pch_request_dma(port);
1227 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1228 PCH_UART_HAL_RX_ERR_INT);
1229 uart_update_timeout(port, CS8, default_baud);
1234 static void pch_uart_shutdown(struct uart_port *port)
1236 struct eg20t_port *priv;
1239 priv = container_of(port, struct eg20t_port, port);
1240 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1241 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1242 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1243 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1245 dev_err(priv->port.dev,
1246 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1250 free_irq(priv->port.irq, priv);
1253 /* Change the port parameters, including word length, parity, stop
1254 *bits. Update read_status_mask and ignore_status_mask to indicate
1255 *the types of events we are interested in receiving. */
1256 static void pch_uart_set_termios(struct uart_port *port,
1257 struct ktermios *termios, struct ktermios *old)
1261 unsigned int parity, bits, stb;
1262 struct eg20t_port *priv;
1263 unsigned long flags;
1265 priv = container_of(port, struct eg20t_port, port);
1266 switch (termios->c_cflag & CSIZE) {
1268 bits = PCH_UART_HAL_5BIT;
1271 bits = PCH_UART_HAL_6BIT;
1274 bits = PCH_UART_HAL_7BIT;
1277 bits = PCH_UART_HAL_8BIT;
1280 if (termios->c_cflag & CSTOPB)
1281 stb = PCH_UART_HAL_STB2;
1283 stb = PCH_UART_HAL_STB1;
1285 if (termios->c_cflag & PARENB) {
1286 if (termios->c_cflag & PARODD)
1287 parity = PCH_UART_HAL_PARITY_ODD;
1289 parity = PCH_UART_HAL_PARITY_EVEN;
1292 parity = PCH_UART_HAL_PARITY_NONE;
1295 /* Only UART0 has auto hardware flow function */
1296 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1297 priv->mcr |= UART_MCR_AFE;
1299 priv->mcr &= ~UART_MCR_AFE;
1301 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1303 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1305 spin_lock_irqsave(&priv->lock, flags);
1306 spin_lock(&port->lock);
1308 uart_update_timeout(port, termios->c_cflag, baud);
1309 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1313 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1314 /* Don't rewrite B0 */
1315 if (tty_termios_baud_rate(termios))
1316 tty_termios_encode_baud_rate(termios, baud, baud);
1319 spin_unlock(&port->lock);
1320 spin_unlock_irqrestore(&priv->lock, flags);
1323 static const char *pch_uart_type(struct uart_port *port)
1325 return KBUILD_MODNAME;
1328 static void pch_uart_release_port(struct uart_port *port)
1330 struct eg20t_port *priv;
1332 priv = container_of(port, struct eg20t_port, port);
1333 pci_iounmap(priv->pdev, priv->membase);
1334 pci_release_regions(priv->pdev);
1337 static int pch_uart_request_port(struct uart_port *port)
1339 struct eg20t_port *priv;
1341 void __iomem *membase;
1343 priv = container_of(port, struct eg20t_port, port);
1344 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1348 membase = pci_iomap(priv->pdev, 1, 0);
1350 pci_release_regions(priv->pdev);
1353 priv->membase = port->membase = membase;
1358 static void pch_uart_config_port(struct uart_port *port, int type)
1360 struct eg20t_port *priv;
1362 priv = container_of(port, struct eg20t_port, port);
1363 if (type & UART_CONFIG_TYPE) {
1364 port->type = priv->port_type;
1365 pch_uart_request_port(port);
1369 static int pch_uart_verify_port(struct uart_port *port,
1370 struct serial_struct *serinfo)
1372 struct eg20t_port *priv;
1374 priv = container_of(port, struct eg20t_port, port);
1375 if (serinfo->flags & UPF_LOW_LATENCY) {
1376 dev_info(priv->port.dev,
1377 "PCH UART : Use PIO Mode (without DMA)\n");
1379 serinfo->flags &= ~UPF_LOW_LATENCY;
1381 #ifndef CONFIG_PCH_DMA
1382 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1386 priv->use_dma_flag = 1;
1387 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1389 pch_request_dma(port);
1396 static struct uart_ops pch_uart_ops = {
1397 .tx_empty = pch_uart_tx_empty,
1398 .set_mctrl = pch_uart_set_mctrl,
1399 .get_mctrl = pch_uart_get_mctrl,
1400 .stop_tx = pch_uart_stop_tx,
1401 .start_tx = pch_uart_start_tx,
1402 .stop_rx = pch_uart_stop_rx,
1403 .enable_ms = pch_uart_enable_ms,
1404 .break_ctl = pch_uart_break_ctl,
1405 .startup = pch_uart_startup,
1406 .shutdown = pch_uart_shutdown,
1407 .set_termios = pch_uart_set_termios,
1408 /* .pm = pch_uart_pm, Not supported yet */
1409 /* .set_wake = pch_uart_set_wake, Not supported yet */
1410 .type = pch_uart_type,
1411 .release_port = pch_uart_release_port,
1412 .request_port = pch_uart_request_port,
1413 .config_port = pch_uart_config_port,
1414 .verify_port = pch_uart_verify_port
1417 static struct uart_driver pch_uart_driver = {
1418 .owner = THIS_MODULE,
1419 .driver_name = KBUILD_MODNAME,
1420 .dev_name = PCH_UART_DRIVER_DEVICE,
1426 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1427 const struct pci_device_id *id)
1429 struct eg20t_port *priv;
1431 unsigned int iobase;
1432 unsigned int mapbase;
1433 unsigned char *rxbuf;
1434 int fifosize, base_baud;
1436 struct pch_uart_driver_data *board;
1437 const char *board_name;
1439 board = &drv_dat[id->driver_data];
1440 port_type = board->port_type;
1442 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1444 goto init_port_alloc_err;
1446 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1448 goto init_port_free_txbuf;
1450 base_baud = 1843200; /* 1.8432MHz */
1452 /* quirk for CM-iTC board */
1453 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1454 if (board_name && strstr(board_name, "CM-iTC"))
1455 base_baud = 192000000; /* 192.0MHz */
1457 switch (port_type) {
1459 fifosize = 256; /* EG20T/ML7213: UART0 */
1462 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1465 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1466 goto init_port_hal_free;
1469 pci_enable_msi(pdev);
1470 pci_set_master(pdev);
1472 spin_lock_init(&priv->lock);
1474 iobase = pci_resource_start(pdev, 0);
1475 mapbase = pci_resource_start(pdev, 1);
1476 priv->mapbase = mapbase;
1477 priv->iobase = iobase;
1480 priv->rxbuf.buf = rxbuf;
1481 priv->rxbuf.size = PAGE_SIZE;
1483 priv->fifo_size = fifosize;
1484 priv->base_baud = base_baud;
1485 priv->port_type = PORT_MAX_8250 + port_type + 1;
1486 priv->port.dev = &pdev->dev;
1487 priv->port.iobase = iobase;
1488 priv->port.membase = NULL;
1489 priv->port.mapbase = mapbase;
1490 priv->port.irq = pdev->irq;
1491 priv->port.iotype = UPIO_PORT;
1492 priv->port.ops = &pch_uart_ops;
1493 priv->port.flags = UPF_BOOT_AUTOCONF;
1494 priv->port.fifosize = fifosize;
1495 priv->port.line = board->line_no;
1496 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1498 spin_lock_init(&priv->port.lock);
1500 pci_set_drvdata(pdev, priv);
1501 pch_uart_hal_request(pdev, fifosize, base_baud);
1503 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1505 goto init_port_hal_free;
1510 free_page((unsigned long)rxbuf);
1511 init_port_free_txbuf:
1513 init_port_alloc_err:
1518 static void pch_uart_exit_port(struct eg20t_port *priv)
1520 uart_remove_one_port(&pch_uart_driver, &priv->port);
1521 pci_set_drvdata(priv->pdev, NULL);
1522 free_page((unsigned long)priv->rxbuf.buf);
1525 static void pch_uart_pci_remove(struct pci_dev *pdev)
1527 struct eg20t_port *priv;
1529 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1531 pci_disable_msi(pdev);
1532 pch_uart_exit_port(priv);
1533 pci_disable_device(pdev);
1538 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1540 struct eg20t_port *priv = pci_get_drvdata(pdev);
1542 uart_suspend_port(&pch_uart_driver, &priv->port);
1544 pci_save_state(pdev);
1545 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1549 static int pch_uart_pci_resume(struct pci_dev *pdev)
1551 struct eg20t_port *priv = pci_get_drvdata(pdev);
1554 pci_set_power_state(pdev, PCI_D0);
1555 pci_restore_state(pdev);
1557 ret = pci_enable_device(pdev);
1560 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1564 uart_resume_port(&pch_uart_driver, &priv->port);
1569 #define pch_uart_pci_suspend NULL
1570 #define pch_uart_pci_resume NULL
1573 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1574 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1575 .driver_data = pch_et20t_uart0},
1576 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1577 .driver_data = pch_et20t_uart1},
1578 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1579 .driver_data = pch_et20t_uart2},
1580 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1581 .driver_data = pch_et20t_uart3},
1582 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1583 .driver_data = pch_ml7213_uart0},
1584 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1585 .driver_data = pch_ml7213_uart1},
1586 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1587 .driver_data = pch_ml7213_uart2},
1588 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1589 .driver_data = pch_ml7223_uart0},
1590 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1591 .driver_data = pch_ml7223_uart1},
1592 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1593 .driver_data = pch_ml7831_uart0},
1594 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1595 .driver_data = pch_ml7831_uart1},
1599 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1600 const struct pci_device_id *id)
1603 struct eg20t_port *priv;
1605 ret = pci_enable_device(pdev);
1609 priv = pch_uart_init_port(pdev, id);
1612 goto probe_disable_device;
1614 pci_set_drvdata(pdev, priv);
1618 probe_disable_device:
1619 pci_disable_msi(pdev);
1620 pci_disable_device(pdev);
1625 static struct pci_driver pch_uart_pci_driver = {
1627 .id_table = pch_uart_pci_id,
1628 .probe = pch_uart_pci_probe,
1629 .remove = __devexit_p(pch_uart_pci_remove),
1630 .suspend = pch_uart_pci_suspend,
1631 .resume = pch_uart_pci_resume,
1634 static int __init pch_uart_module_init(void)
1638 /* register as UART driver */
1639 ret = uart_register_driver(&pch_uart_driver);
1643 /* register as PCI driver */
1644 ret = pci_register_driver(&pch_uart_pci_driver);
1646 uart_unregister_driver(&pch_uart_driver);
1650 module_init(pch_uart_module_init);
1652 static void __exit pch_uart_module_exit(void)
1654 pci_unregister_driver(&pch_uart_pci_driver);
1655 uart_unregister_driver(&pch_uart_driver);
1657 module_exit(pch_uart_module_exit);
1659 MODULE_LICENSE("GPL v2");
1660 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1661 module_param(default_baud, uint, S_IRUGO);