drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #include <linux/kernel.h>
  18 #include <linux/serial_reg.h>
  19 #include <linux/slab.h>
  20 #include <linux/module.h>
  21 #include <linux/pci.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/dmi.h>
  28
  29 #include <linux/dmaengine.h>
  30 #include <linux/pch_dma.h>
  31
  32 enum {
  33         PCH_UART_HANDLED_RX_INT_SHIFT,
  34         PCH_UART_HANDLED_TX_INT_SHIFT,
  35         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  36         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  37         PCH_UART_HANDLED_MS_INT_SHIFT,
  38 };
  39
  40 enum {
  41         PCH_UART_8LINE,
  42         PCH_UART_2LINE,
  43 };
  44
  45 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  46
  47 /* Set the max number of UART port
  48  * Intel EG20T PCH: 4 port
  49  * LAPIS Semiconductor ML7213 IOH: 3 port
  50  * LAPIS Semiconductor ML7223 IOH: 2 port
  51 */
  52 #define PCH_UART_NR     4
  53
  54 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  55 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  56 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  57                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  58 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  59                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  60 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  61
  62 #define PCH_UART_RBR            0x00
  63 #define PCH_UART_THR            0x00
  64
  65 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  66                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  67 #define PCH_UART_IER_ERBFI      0x00000001
  68 #define PCH_UART_IER_ETBEI      0x00000002
  69 #define PCH_UART_IER_ELSI       0x00000004
  70 #define PCH_UART_IER_EDSSI      0x00000008
  71
  72 #define PCH_UART_IIR_IP                 0x00000001
  73 #define PCH_UART_IIR_IID                0x00000006
  74 #define PCH_UART_IIR_MSI                0x00000000
  75 #define PCH_UART_IIR_TRI                0x00000002
  76 #define PCH_UART_IIR_RRI                0x00000004
  77 #define PCH_UART_IIR_REI                0x00000006
  78 #define PCH_UART_IIR_TOI                0x00000008
  79 #define PCH_UART_IIR_FIFO256            0x00000020
  80 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  81 #define PCH_UART_IIR_FE                 0x000000C0
  82
  83 #define PCH_UART_FCR_FIFOE              0x00000001
  84 #define PCH_UART_FCR_RFR                0x00000002
  85 #define PCH_UART_FCR_TFR                0x00000004
  86 #define PCH_UART_FCR_DMS                0x00000008
  87 #define PCH_UART_FCR_FIFO256            0x00000020
  88 #define PCH_UART_FCR_RFTL               0x000000C0
  89
  90 #define PCH_UART_FCR_RFTL1              0x00000000
  91 #define PCH_UART_FCR_RFTL64             0x00000040
  92 #define PCH_UART_FCR_RFTL128            0x00000080
  93 #define PCH_UART_FCR_RFTL224            0x000000C0
  94 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  95 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  96 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  97 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  98 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  99 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 100 #define PCH_UART_FCR_RFTL_SHIFT         6
 101
 102 #define PCH_UART_LCR_WLS        0x00000003
 103 #define PCH_UART_LCR_STB        0x00000004
 104 #define PCH_UART_LCR_PEN        0x00000008
 105 #define PCH_UART_LCR_EPS        0x00000010
 106 #define PCH_UART_LCR_SP         0x00000020
 107 #define PCH_UART_LCR_SB         0x00000040
 108 #define PCH_UART_LCR_DLAB       0x00000080
 109 #define PCH_UART_LCR_NP         0x00000000
 110 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 111 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 112 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 113 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 114                                 PCH_UART_LCR_SP)
 115
 116 #define PCH_UART_LCR_5BIT       0x00000000
 117 #define PCH_UART_LCR_6BIT       0x00000001
 118 #define PCH_UART_LCR_7BIT       0x00000002
 119 #define PCH_UART_LCR_8BIT       0x00000003
 120
 121 #define PCH_UART_MCR_DTR        0x00000001
 122 #define PCH_UART_MCR_RTS        0x00000002
 123 #define PCH_UART_MCR_OUT        0x0000000C
 124 #define PCH_UART_MCR_LOOP       0x00000010
 125 #define PCH_UART_MCR_AFE        0x00000020
 126
 127 #define PCH_UART_LSR_DR         0x00000001
 128 #define PCH_UART_LSR_ERR        (1<<7)
 129
 130 #define PCH_UART_MSR_DCTS       0x00000001
 131 #define PCH_UART_MSR_DDSR       0x00000002
 132 #define PCH_UART_MSR_TERI       0x00000004
 133 #define PCH_UART_MSR_DDCD       0x00000008
 134 #define PCH_UART_MSR_CTS        0x00000010
 135 #define PCH_UART_MSR_DSR        0x00000020
 136 #define PCH_UART_MSR_RI         0x00000040
 137 #define PCH_UART_MSR_DCD        0x00000080
 138 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 139                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 140
 141 #define PCH_UART_DLL            0x00
 142 #define PCH_UART_DLM            0x01
 143
 144 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 145 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 146 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 147 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 148 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 149
 150 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 151 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 152 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 153 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 154 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 155 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 156 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 157 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 158 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 159 #define PCH_UART_HAL_STB1               0
 160 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 161
 162 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 163 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 164 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 165                                         PCH_UART_HAL_CLR_RX_FIFO)
 166
 167 #define PCH_UART_HAL_DMA_MODE0          0
 168 #define PCH_UART_HAL_FIFO_DIS           0
 169 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 170 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 171                                         PCH_UART_FCR_FIFO256)
 172 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 173 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 174 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 175 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 176 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 177 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 178 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 179 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 180 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 181 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 182 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 183 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 184 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 185 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 186
 187 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 188 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 189 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 190 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 191 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 192
 193 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 194 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 195 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 196 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 197 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 198
 199 #define PCI_VENDOR_ID_ROHM              0x10DB
 200
 201 struct pch_uart_buffer {
 202         unsigned char *buf;
 203         int size;
 204 };
 205
 206 struct eg20t_port {
 207         struct uart_port port;
 208         int port_type;
 209         void __iomem *membase;
 210         resource_size_t mapbase;
 211         unsigned int iobase;
 212         struct pci_dev *pdev;
 213         int fifo_size;
 214         int base_baud;
 215         int start_tx;
 216         int start_rx;
 217         int tx_empty;
 218         int int_dis_flag;
 219         int trigger;
 220         int trigger_level;
 221         struct pch_uart_buffer rxbuf;
 222         unsigned int dmsr;
 223         unsigned int fcr;
 224         unsigned int mcr;
 225         unsigned int use_dma;
 226         unsigned int use_dma_flag;
 227         struct dma_async_tx_descriptor  *desc_tx;
 228         struct dma_async_tx_descriptor  *desc_rx;
 229         struct pch_dma_slave            param_tx;
 230         struct pch_dma_slave            param_rx;
 231         struct dma_chan                 *chan_tx;
 232         struct dma_chan                 *chan_rx;
 233         struct scatterlist              *sg_tx_p;
 234         int                             nent;
 235         struct scatterlist              sg_rx;
 236         int                             tx_dma_use;
 237         void                            *rx_buf_virt;
 238         dma_addr_t                      rx_buf_dma;
 239
 240         /* protect the eg20t_port private structure and io access to membase */
 241         spinlock_t lock;
 242 };
 243
 244 /**
 245  * struct pch_uart_driver_data - private data structure for UART-DMA
 246  * @port_type:                  The number of DMA channel
 247  * @line_no:                    UART port line number (0, 1, 2...)
 248  */
 249 struct pch_uart_driver_data {
 250         int port_type;
 251         int line_no;
 252 };
 253
 254 enum pch_uart_num_t {
 255         pch_et20t_uart0 = 0,
 256         pch_et20t_uart1,
 257         pch_et20t_uart2,
 258         pch_et20t_uart3,
 259         pch_ml7213_uart0,
 260         pch_ml7213_uart1,
 261         pch_ml7213_uart2,
 262         pch_ml7223_uart0,
 263         pch_ml7223_uart1,
 264         pch_ml7831_uart0,
 265         pch_ml7831_uart1,
 266 };
 267
 268 static struct pch_uart_driver_data drv_dat[] = {
 269         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 270         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 271         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 272         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 273         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 274         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 275         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 276         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 277         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 278         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 279         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 280 };
 281
 282 static unsigned int default_baud = 9600;
 283 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 284 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 285 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 286 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 287
 288 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
 289                                  int base_baud)
 290 {
 291         struct eg20t_port *priv = pci_get_drvdata(pdev);
 292
 293         priv->trigger_level = 1;
 294         priv->fcr = 0;
 295 }
 296
 297 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
 298 {
 299         unsigned int msr = ioread8(base + UART_MSR);
 300         priv->dmsr |= msr & PCH_UART_MSR_DELTA;
 301
 302         return msr;
 303 }
 304
 305 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 306                                           unsigned int flag)
 307 {
 308         u8 ier = ioread8(priv->membase + UART_IER);
 309         ier |= flag & PCH_UART_IER_MASK;
 310         iowrite8(ier, priv->membase + UART_IER);
 311 }
 312
 313 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 314                                            unsigned int flag)
 315 {
 316         u8 ier = ioread8(priv->membase + UART_IER);
 317         ier &= ~(flag & PCH_UART_IER_MASK);
 318         iowrite8(ier, priv->membase + UART_IER);
 319 }
 320
 321 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
 322                                  unsigned int parity, unsigned int bits,
 323                                  unsigned int stb)
 324 {
 325         unsigned int dll, dlm, lcr;
 326         int div;
 327
 328         div = DIV_ROUND_CLOSEST(priv->base_baud / 16, baud);
 329         if (div < 0 || USHRT_MAX <= div) {
 330                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 331                 return -EINVAL;
 332         }
 333
 334         dll = (unsigned int)div & 0x00FFU;
 335         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 336
 337         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 338                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 339                 return -EINVAL;
 340         }
 341
 342         if (bits & ~PCH_UART_LCR_WLS) {
 343                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 344                 return -EINVAL;
 345         }
 346
 347         if (stb & ~PCH_UART_LCR_STB) {
 348                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 349                 return -EINVAL;
 350         }
 351
 352         lcr = parity;
 353         lcr |= bits;
 354         lcr |= stb;
 355
 356         dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
 357                  __func__, baud, div, lcr, jiffies);
 358         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 359         iowrite8(dll, priv->membase + PCH_UART_DLL);
 360         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 361         iowrite8(lcr, priv->membase + UART_LCR);
 362
 363         return 0;
 364 }
 365
 366 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 367                                     unsigned int flag)
 368 {
 369         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 370                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 371                         __func__, flag);
 372                 return -EINVAL;
 373         }
 374
 375         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 376         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 377                  priv->membase + UART_FCR);
 378         iowrite8(priv->fcr, priv->membase + UART_FCR);
 379
 380         return 0;
 381 }
 382
 383 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 384                                  unsigned int dmamode,
 385                                  unsigned int fifo_size, unsigned int trigger)
 386 {
 387         u8 fcr;
 388
 389         if (dmamode & ~PCH_UART_FCR_DMS) {
 390                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 391                         __func__, dmamode);
 392                 return -EINVAL;
 393         }
 394
 395         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 396                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 397                         __func__, fifo_size);
 398                 return -EINVAL;
 399         }
 400
 401         if (trigger & ~PCH_UART_FCR_RFTL) {
 402                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 403                         __func__, trigger);
 404                 return -EINVAL;
 405         }
 406
 407         switch (priv->fifo_size) {
 408         case 256:
 409                 priv->trigger_level =
 410                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 411                 break;
 412         case 64:
 413                 priv->trigger_level =
 414                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 415                 break;
 416         case 16:
 417                 priv->trigger_level =
 418                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 419                 break;
 420         default:
 421                 priv->trigger_level =
 422                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 423                 break;
 424         }
 425         fcr =
 426             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 427         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 428         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 429                  priv->membase + UART_FCR);
 430         iowrite8(fcr, priv->membase + UART_FCR);
 431         priv->fcr = fcr;
 432
 433         return 0;
 434 }
 435
 436 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 437 {
 438         priv->dmsr = 0;
 439         return get_msr(priv, priv->membase);
 440 }
 441
 442 static void pch_uart_hal_write(struct eg20t_port *priv,
 443                               const unsigned char *buf, int tx_size)
 444 {
 445         int i;
 446         unsigned int thr;
 447
 448         for (i = 0; i < tx_size;) {
 449                 thr = buf[i++];
 450                 iowrite8(thr, priv->membase + PCH_UART_THR);
 451         }
 452 }
 453
 454 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 455                              int rx_size)
 456 {
 457         int i;
 458         u8 rbr, lsr;
 459
 460         lsr = ioread8(priv->membase + UART_LSR);
 461         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 462              i < rx_size && lsr & UART_LSR_DR;
 463              lsr = ioread8(priv->membase + UART_LSR)) {
 464                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 465                 buf[i++] = rbr;
 466         }
 467         return i;
 468 }
 469
 470 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
 471 {
 472         unsigned int iir;
 473         int ret;
 474
 475         iir = ioread8(priv->membase + UART_IIR);
 476         ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
 477         return ret;
 478 }
 479
 480 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 481 {
 482         return ioread8(priv->membase + UART_LSR);
 483 }
 484
 485 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 486 {
 487         unsigned int lcr;
 488
 489         lcr = ioread8(priv->membase + UART_LCR);
 490         if (on)
 491                 lcr |= PCH_UART_LCR_SB;
 492         else
 493                 lcr &= ~PCH_UART_LCR_SB;
 494
 495         iowrite8(lcr, priv->membase + UART_LCR);
 496 }
 497
 498 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 499                    int size)
 500 {
 501         struct uart_port *port;
 502         struct tty_struct *tty;
 503
 504         port = &priv->port;
 505         tty = tty_port_tty_get(&port->state->port);
 506         if (!tty) {
 507                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 508                 return -EBUSY;
 509         }
 510
 511         tty_insert_flip_string(tty, buf, size);
 512         tty_flip_buffer_push(tty);
 513         tty_kref_put(tty);
 514
 515         return 0;
 516 }
 517
 518 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 519 {
 520         int ret;
 521         struct uart_port *port = &priv->port;
 522
 523         if (port->x_char) {
 524                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 525                         __func__, port->x_char, jiffies);
 526                 buf[0] = port->x_char;
 527                 port->x_char = 0;
 528                 ret = 1;
 529         } else {
 530                 ret = 0;
 531         }
 532
 533         return ret;
 534 }
 535
 536 static int dma_push_rx(struct eg20t_port *priv, int size)
 537 {
 538         struct tty_struct *tty;
 539         int room;
 540         struct uart_port *port = &priv->port;
 541
 542         port = &priv->port;
 543         tty = tty_port_tty_get(&port->state->port);
 544         if (!tty) {
 545                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 546                 return 0;
 547         }
 548
 549         room = tty_buffer_request_room(tty, size);
 550
 551         if (room < size)
 552                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 553                          size - room);
 554         if (!room)
 555                 return room;
 556
 557         tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
 558
 559         port->icount.rx += room;
 560         tty_kref_put(tty);
 561
 562         return room;
 563 }
 564
 565 static void pch_free_dma(struct uart_port *port)
 566 {
 567         struct eg20t_port *priv;
 568         priv = container_of(port, struct eg20t_port, port);
 569
 570         if (priv->chan_tx) {
 571                 dma_release_channel(priv->chan_tx);
 572                 priv->chan_tx = NULL;
 573         }
 574         if (priv->chan_rx) {
 575                 dma_release_channel(priv->chan_rx);
 576                 priv->chan_rx = NULL;
 577         }
 578         if (sg_dma_address(&priv->sg_rx))
 579                 dma_free_coherent(port->dev, port->fifosize,
 580                                   sg_virt(&priv->sg_rx),
 581                                   sg_dma_address(&priv->sg_rx));
 582
 583         return;
 584 }
 585
 586 static bool filter(struct dma_chan *chan, void *slave)
 587 {
 588         struct pch_dma_slave *param = slave;
 589
 590         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 591                                                   chan->device->dev)) {
 592                 chan->private = param;
 593                 return true;
 594         } else {
 595                 return false;
 596         }
 597 }
 598
 599 static void pch_request_dma(struct uart_port *port)
 600 {
 601         dma_cap_mask_t mask;
 602         struct dma_chan *chan;
 603         struct pci_dev *dma_dev;
 604         struct pch_dma_slave *param;
 605         struct eg20t_port *priv =
 606                                 container_of(port, struct eg20t_port, port);
 607         dma_cap_zero(mask);
 608         dma_cap_set(DMA_SLAVE, mask);
 609
 610         dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
 611                                        PCI_DEVFN(0xa, 0)); /* Get DMA's dev
 612                                                                 information */
 613         /* Set Tx DMA */
 614         param = &priv->param_tx;
 615         param->dma_dev = &dma_dev->dev;
 616         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 617
 618         param->tx_reg = port->mapbase + UART_TX;
 619         chan = dma_request_channel(mask, filter, param);
 620         if (!chan) {
 621                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 622                         __func__);
 623                 return;
 624         }
 625         priv->chan_tx = chan;
 626
 627         /* Set Rx DMA */
 628         param = &priv->param_rx;
 629         param->dma_dev = &dma_dev->dev;
 630         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 631
 632         param->rx_reg = port->mapbase + UART_RX;
 633         chan = dma_request_channel(mask, filter, param);
 634         if (!chan) {
 635                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 636                         __func__);
 637                 dma_release_channel(priv->chan_tx);
 638                 priv->chan_tx = NULL;
 639                 return;
 640         }
 641
 642         /* Get Consistent memory for DMA */
 643         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 644                                     &priv->rx_buf_dma, GFP_KERNEL);
 645         priv->chan_rx = chan;
 646 }
 647
 648 static void pch_dma_rx_complete(void *arg)
 649 {
 650         struct eg20t_port *priv = arg;
 651         struct uart_port *port = &priv->port;
 652         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
 653         int count;
 654
 655         if (!tty) {
 656                 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
 657                 return;
 658         }
 659
 660         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 661         count = dma_push_rx(priv, priv->trigger_level);
 662         if (count)
 663                 tty_flip_buffer_push(tty);
 664         tty_kref_put(tty);
 665         async_tx_ack(priv->desc_rx);
 666         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 667                                             PCH_UART_HAL_RX_ERR_INT);
 668 }
 669
 670 static void pch_dma_tx_complete(void *arg)
 671 {
 672         struct eg20t_port *priv = arg;
 673         struct uart_port *port = &priv->port;
 674         struct circ_buf *xmit = &port->state->xmit;
 675         struct scatterlist *sg = priv->sg_tx_p;
 676         int i;
 677
 678         for (i = 0; i < priv->nent; i++, sg++) {
 679                 xmit->tail += sg_dma_len(sg);
 680                 port->icount.tx += sg_dma_len(sg);
 681         }
 682         xmit->tail &= UART_XMIT_SIZE - 1;
 683         async_tx_ack(priv->desc_tx);
 684         dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 685         priv->tx_dma_use = 0;
 686         priv->nent = 0;
 687         kfree(priv->sg_tx_p);
 688         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 689 }
 690
 691 static int pop_tx(struct eg20t_port *priv, int size)
 692 {
 693         int count = 0;
 694         struct uart_port *port = &priv->port;
 695         struct circ_buf *xmit = &port->state->xmit;
 696
 697         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 698                 goto pop_tx_end;
 699
 700         do {
 701                 int cnt_to_end =
 702                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 703                 int sz = min(size - count, cnt_to_end);
 704                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 705                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 706                 count += sz;
 707         } while (!uart_circ_empty(xmit) && count < size);
 708
 709 pop_tx_end:
 710         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 711                  count, size - count, jiffies);
 712
 713         return count;
 714 }
 715
 716 static int handle_rx_to(struct eg20t_port *priv)
 717 {
 718         struct pch_uart_buffer *buf;
 719         int rx_size;
 720         int ret;
 721         if (!priv->start_rx) {
 722                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 723                                                      PCH_UART_HAL_RX_ERR_INT);
 724                 return 0;
 725         }
 726         buf = &priv->rxbuf;
 727         do {
 728                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 729                 ret = push_rx(priv, buf->buf, rx_size);
 730                 if (ret)
 731                         return 0;
 732         } while (rx_size == buf->size);
 733
 734         return PCH_UART_HANDLED_RX_INT;
 735 }
 736
 737 static int handle_rx(struct eg20t_port *priv)
 738 {
 739         return handle_rx_to(priv);
 740 }
 741
 742 static int dma_handle_rx(struct eg20t_port *priv)
 743 {
 744         struct uart_port *port = &priv->port;
 745         struct dma_async_tx_descriptor *desc;
 746         struct scatterlist *sg;
 747
 748         priv = container_of(port, struct eg20t_port, port);
 749         sg = &priv->sg_rx;
 750
 751         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 752
 753         sg_dma_len(sg) = priv->trigger_level;
 754
 755         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 756                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 757                      ~PAGE_MASK);
 758
 759         sg_dma_address(sg) = priv->rx_buf_dma;
 760
 761         desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
 762                         sg, 1, DMA_FROM_DEVICE,
 763                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 764
 765         if (!desc)
 766                 return 0;
 767
 768         priv->desc_rx = desc;
 769         desc->callback = pch_dma_rx_complete;
 770         desc->callback_param = priv;
 771         desc->tx_submit(desc);
 772         dma_async_issue_pending(priv->chan_rx);
 773
 774         return PCH_UART_HANDLED_RX_INT;
 775 }
 776
 777 static unsigned int handle_tx(struct eg20t_port *priv)
 778 {
 779         struct uart_port *port = &priv->port;
 780         struct circ_buf *xmit = &port->state->xmit;
 781         int fifo_size;
 782         int tx_size;
 783         int size;
 784         int tx_empty;
 785
 786         if (!priv->start_tx) {
 787                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 788                         __func__, jiffies);
 789                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 790                 priv->tx_empty = 1;
 791                 return 0;
 792         }
 793
 794         fifo_size = max(priv->fifo_size, 1);
 795         tx_empty = 1;
 796         if (pop_tx_x(priv, xmit->buf)) {
 797                 pch_uart_hal_write(priv, xmit->buf, 1);
 798                 port->icount.tx++;
 799                 tx_empty = 0;
 800                 fifo_size--;
 801         }
 802         size = min(xmit->head - xmit->tail, fifo_size);
 803         if (size < 0)
 804                 size = fifo_size;
 805
 806         tx_size = pop_tx(priv, size);
 807         if (tx_size > 0) {
 808                 port->icount.tx += tx_size;
 809                 tx_empty = 0;
 810         }
 811
 812         priv->tx_empty = tx_empty;
 813
 814         if (tx_empty) {
 815                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 816                 uart_write_wakeup(port);
 817         }
 818
 819         return PCH_UART_HANDLED_TX_INT;
 820 }
 821
 822 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 823 {
 824         struct uart_port *port = &priv->port;
 825         struct circ_buf *xmit = &port->state->xmit;
 826         struct scatterlist *sg;
 827         int nent;
 828         int fifo_size;
 829         int tx_empty;
 830         struct dma_async_tx_descriptor *desc;
 831         int num;
 832         int i;
 833         int bytes;
 834         int size;
 835         int rem;
 836
 837         if (!priv->start_tx) {
 838                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 839                         __func__, jiffies);
 840                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 841                 priv->tx_empty = 1;
 842                 return 0;
 843         }
 844
 845         if (priv->tx_dma_use) {
 846                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 847                         __func__, jiffies);
 848                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 849                 priv->tx_empty = 1;
 850                 return 0;
 851         }
 852
 853         fifo_size = max(priv->fifo_size, 1);
 854         tx_empty = 1;
 855         if (pop_tx_x(priv, xmit->buf)) {
 856                 pch_uart_hal_write(priv, xmit->buf, 1);
 857                 port->icount.tx++;
 858                 tx_empty = 0;
 859                 fifo_size--;
 860         }
 861
 862         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 863                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 864                              xmit->tail, UART_XMIT_SIZE));
 865         if (!bytes) {
 866                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 867                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 868                 uart_write_wakeup(port);
 869                 return 0;
 870         }
 871
 872         if (bytes > fifo_size) {
 873                 num = bytes / fifo_size + 1;
 874                 size = fifo_size;
 875                 rem = bytes % fifo_size;
 876         } else {
 877                 num = 1;
 878                 size = bytes;
 879                 rem = bytes;
 880         }
 881
 882         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 883                 __func__, num, size, rem);
 884
 885         priv->tx_dma_use = 1;
 886
 887         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
 888
 889         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
 890         sg = priv->sg_tx_p;
 891
 892         for (i = 0; i < num; i++, sg++) {
 893                 if (i == (num - 1))
 894                         sg_set_page(sg, virt_to_page(xmit->buf),
 895                                     rem, fifo_size * i);
 896                 else
 897                         sg_set_page(sg, virt_to_page(xmit->buf),
 898                                     size, fifo_size * i);
 899         }
 900
 901         sg = priv->sg_tx_p;
 902         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
 903         if (!nent) {
 904                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
 905                 return 0;
 906         }
 907         priv->nent = nent;
 908
 909         for (i = 0; i < nent; i++, sg++) {
 910                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
 911                               fifo_size * i;
 912                 sg_dma_address(sg) = (sg_dma_address(sg) &
 913                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
 914                 if (i == (nent - 1))
 915                         sg_dma_len(sg) = rem;
 916                 else
 917                         sg_dma_len(sg) = size;
 918         }
 919
 920         desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
 921                                         priv->sg_tx_p, nent, DMA_TO_DEVICE,
 922                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 923         if (!desc) {
 924                 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
 925                         __func__);
 926                 return 0;
 927         }
 928         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
 929         priv->desc_tx = desc;
 930         desc->callback = pch_dma_tx_complete;
 931         desc->callback_param = priv;
 932
 933         desc->tx_submit(desc);
 934
 935         dma_async_issue_pending(priv->chan_tx);
 936
 937         return PCH_UART_HANDLED_TX_INT;
 938 }
 939
 940 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
 941 {
 942         u8 fcr = ioread8(priv->membase + UART_FCR);
 943
 944         /* Reset FIFO */
 945         fcr |= UART_FCR_CLEAR_RCVR;
 946         iowrite8(fcr, priv->membase + UART_FCR);
 947
 948         if (lsr & PCH_UART_LSR_ERR)
 949                 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
 950
 951         if (lsr & UART_LSR_FE)
 952                 dev_err(&priv->pdev->dev, "Framing Error\n");
 953
 954         if (lsr & UART_LSR_PE)
 955                 dev_err(&priv->pdev->dev, "Parity Error\n");
 956
 957         if (lsr & UART_LSR_OE)
 958                 dev_err(&priv->pdev->dev, "Overrun Error\n");
 959 }
 960
 961 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
 962 {
 963         struct eg20t_port *priv = dev_id;
 964         unsigned int handled;
 965         u8 lsr;
 966         int ret = 0;
 967         unsigned int iid;
 968         unsigned long flags;
 969
 970         spin_lock_irqsave(&priv->lock, flags);
 971         handled = 0;
 972         while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
 973                 switch (iid) {
 974                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
 975                         lsr = pch_uart_hal_get_line_status(priv);
 976                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
 977                                                 UART_LSR_PE | UART_LSR_OE)) {
 978                                 pch_uart_err_ir(priv, lsr);
 979                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
 980                         }
 981                         break;
 982                 case PCH_UART_IID_RDR:  /* Received Data Ready */
 983                         if (priv->use_dma) {
 984                                 pch_uart_hal_disable_interrupt(priv,
 985                                                 PCH_UART_HAL_RX_INT |
 986                                                 PCH_UART_HAL_RX_ERR_INT);
 987                                 ret = dma_handle_rx(priv);
 988                                 if (!ret)
 989                                         pch_uart_hal_enable_interrupt(priv,
 990                                                 PCH_UART_HAL_RX_INT |
 991                                                 PCH_UART_HAL_RX_ERR_INT);
 992                         } else {
 993                                 ret = handle_rx(priv);
 994                         }
 995                         break;
 996                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
 997                                                    (FIFO Timeout) */
 998                         ret = handle_rx_to(priv);
 999                         break;
1000                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1001                                                    Empty */
1002                         if (priv->use_dma)
1003                                 ret = dma_handle_tx(priv);
1004                         else
1005                                 ret = handle_tx(priv);
1006                         break;
1007                 case PCH_UART_IID_MS:   /* Modem Status */
1008                         ret = PCH_UART_HANDLED_MS_INT;
1009                         break;
1010                 default:        /* Never junp to this label */
1011                         dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1012                                 iid, jiffies);
1013                         ret = -1;
1014                         break;
1015                 }
1016                 handled |= (unsigned int)ret;
1017         }
1018         if (handled == 0 && iid <= 1) {
1019                 if (priv->int_dis_flag)
1020                         priv->int_dis_flag = 0;
1021         }
1022
1023         spin_unlock_irqrestore(&priv->lock, flags);
1024         return IRQ_RETVAL(handled);
1025 }
1026
1027 /* This function tests whether the transmitter fifo and shifter for the port
1028                                                 described by 'port' is empty. */
1029 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1030 {
1031         struct eg20t_port *priv;
1032         int ret;
1033         priv = container_of(port, struct eg20t_port, port);
1034         if (priv->tx_empty)
1035                 ret = TIOCSER_TEMT;
1036         else
1037                 ret = 0;
1038
1039         return ret;
1040 }
1041
1042 /* Returns the current state of modem control inputs. */
1043 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1044 {
1045         struct eg20t_port *priv;
1046         u8 modem;
1047         unsigned int ret = 0;
1048
1049         priv = container_of(port, struct eg20t_port, port);
1050         modem = pch_uart_hal_get_modem(priv);
1051
1052         if (modem & UART_MSR_DCD)
1053                 ret |= TIOCM_CAR;
1054
1055         if (modem & UART_MSR_RI)
1056                 ret |= TIOCM_RNG;
1057
1058         if (modem & UART_MSR_DSR)
1059                 ret |= TIOCM_DSR;
1060
1061         if (modem & UART_MSR_CTS)
1062                 ret |= TIOCM_CTS;
1063
1064         return ret;
1065 }
1066
1067 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1068 {
1069         u32 mcr = 0;
1070         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1071
1072         if (mctrl & TIOCM_DTR)
1073                 mcr |= UART_MCR_DTR;
1074         if (mctrl & TIOCM_RTS)
1075                 mcr |= UART_MCR_RTS;
1076         if (mctrl & TIOCM_LOOP)
1077                 mcr |= UART_MCR_LOOP;
1078
1079         if (priv->mcr & UART_MCR_AFE)
1080                 mcr |= UART_MCR_AFE;
1081
1082         if (mctrl)
1083                 iowrite8(mcr, priv->membase + UART_MCR);
1084 }
1085
1086 static void pch_uart_stop_tx(struct uart_port *port)
1087 {
1088         struct eg20t_port *priv;
1089         priv = container_of(port, struct eg20t_port, port);
1090         priv->start_tx = 0;
1091         priv->tx_dma_use = 0;
1092 }
1093
1094 static void pch_uart_start_tx(struct uart_port *port)
1095 {
1096         struct eg20t_port *priv;
1097
1098         priv = container_of(port, struct eg20t_port, port);
1099
1100         if (priv->use_dma) {
1101                 if (priv->tx_dma_use) {
1102                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1103                                 __func__);
1104                         return;
1105                 }
1106         }
1107
1108         priv->start_tx = 1;
1109         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1110 }
1111
1112 static void pch_uart_stop_rx(struct uart_port *port)
1113 {
1114         struct eg20t_port *priv;
1115         priv = container_of(port, struct eg20t_port, port);
1116         priv->start_rx = 0;
1117         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1118                                              PCH_UART_HAL_RX_ERR_INT);
1119         priv->int_dis_flag = 1;
1120 }
1121
1122 /* Enable the modem status interrupts. */
1123 static void pch_uart_enable_ms(struct uart_port *port)
1124 {
1125         struct eg20t_port *priv;
1126         priv = container_of(port, struct eg20t_port, port);
1127         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1128 }
1129
1130 /* Control the transmission of a break signal. */
1131 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1132 {
1133         struct eg20t_port *priv;
1134         unsigned long flags;
1135
1136         priv = container_of(port, struct eg20t_port, port);
1137         spin_lock_irqsave(&priv->lock, flags);
1138         pch_uart_hal_set_break(priv, ctl);
1139         spin_unlock_irqrestore(&priv->lock, flags);
1140 }
1141
1142 /* Grab any interrupt resources and initialise any low level driver state. */
1143 static int pch_uart_startup(struct uart_port *port)
1144 {
1145         struct eg20t_port *priv;
1146         int ret;
1147         int fifo_size;
1148         int trigger_level;
1149
1150         priv = container_of(port, struct eg20t_port, port);
1151         priv->tx_empty = 1;
1152
1153         if (port->uartclk)
1154                 priv->base_baud = port->uartclk;
1155         else
1156                 port->uartclk = priv->base_baud;
1157
1158         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1159         ret = pch_uart_hal_set_line(priv, default_baud,
1160                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1161                               PCH_UART_HAL_STB1);
1162         if (ret)
1163                 return ret;
1164
1165         switch (priv->fifo_size) {
1166         case 256:
1167                 fifo_size = PCH_UART_HAL_FIFO256;
1168                 break;
1169         case 64:
1170                 fifo_size = PCH_UART_HAL_FIFO64;
1171                 break;
1172         case 16:
1173                 fifo_size = PCH_UART_HAL_FIFO16;
1174                 break;
1175         case 1:
1176         default:
1177                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1178                 break;
1179         }
1180
1181         switch (priv->trigger) {
1182         case PCH_UART_HAL_TRIGGER1:
1183                 trigger_level = 1;
1184                 break;
1185         case PCH_UART_HAL_TRIGGER_L:
1186                 trigger_level = priv->fifo_size / 4;
1187                 break;
1188         case PCH_UART_HAL_TRIGGER_M:
1189                 trigger_level = priv->fifo_size / 2;
1190                 break;
1191         case PCH_UART_HAL_TRIGGER_H:
1192         default:
1193                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1194                 break;
1195         }
1196
1197         priv->trigger_level = trigger_level;
1198         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1199                                     fifo_size, priv->trigger);
1200         if (ret < 0)
1201                 return ret;
1202
1203         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1204                         KBUILD_MODNAME, priv);
1205         if (ret < 0)
1206                 return ret;
1207
1208         if (priv->use_dma)
1209                 pch_request_dma(port);
1210
1211         priv->start_rx = 1;
1212         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1213                                             PCH_UART_HAL_RX_ERR_INT);
1214         uart_update_timeout(port, CS8, default_baud);
1215
1216         return 0;
1217 }
1218
1219 static void pch_uart_shutdown(struct uart_port *port)
1220 {
1221         struct eg20t_port *priv;
1222         int ret;
1223
1224         priv = container_of(port, struct eg20t_port, port);
1225         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1226         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1227         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1228                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1229         if (ret)
1230                 dev_err(priv->port.dev,
1231                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1232
1233         pch_free_dma(port);
1234
1235         free_irq(priv->port.irq, priv);
1236 }
1237
1238 /* Change the port parameters, including word length, parity, stop
1239  *bits.  Update read_status_mask and ignore_status_mask to indicate
1240  *the types of events we are interested in receiving.  */
1241 static void pch_uart_set_termios(struct uart_port *port,
1242                                  struct ktermios *termios, struct ktermios *old)
1243 {
1244         int baud;
1245         int rtn;
1246         unsigned int parity, bits, stb;
1247         struct eg20t_port *priv;
1248         unsigned long flags;
1249
1250         priv = container_of(port, struct eg20t_port, port);
1251         switch (termios->c_cflag & CSIZE) {
1252         case CS5:
1253                 bits = PCH_UART_HAL_5BIT;
1254                 break;
1255         case CS6:
1256                 bits = PCH_UART_HAL_6BIT;
1257                 break;
1258         case CS7:
1259                 bits = PCH_UART_HAL_7BIT;
1260                 break;
1261         default:                /* CS8 */
1262                 bits = PCH_UART_HAL_8BIT;
1263                 break;
1264         }
1265         if (termios->c_cflag & CSTOPB)
1266                 stb = PCH_UART_HAL_STB2;
1267         else
1268                 stb = PCH_UART_HAL_STB1;
1269
1270         if (termios->c_cflag & PARENB) {
1271                 if (termios->c_cflag & PARODD)
1272                         parity = PCH_UART_HAL_PARITY_ODD;
1273                 else
1274                         parity = PCH_UART_HAL_PARITY_EVEN;
1275
1276         } else {
1277                 parity = PCH_UART_HAL_PARITY_NONE;
1278         }
1279
1280         /* Only UART0 has auto hardware flow function */
1281         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1282                 priv->mcr |= UART_MCR_AFE;
1283         else
1284                 priv->mcr &= ~UART_MCR_AFE;
1285
1286         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1287
1288         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1289
1290         spin_lock_irqsave(&priv->lock, flags);
1291         spin_lock(&port->lock);
1292
1293         uart_update_timeout(port, termios->c_cflag, baud);
1294         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1295         if (rtn)
1296                 goto out;
1297
1298         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1299         /* Don't rewrite B0 */
1300         if (tty_termios_baud_rate(termios))
1301                 tty_termios_encode_baud_rate(termios, baud, baud);
1302
1303 out:
1304         spin_unlock(&port->lock);
1305         spin_unlock_irqrestore(&priv->lock, flags);
1306 }
1307
1308 static const char *pch_uart_type(struct uart_port *port)
1309 {
1310         return KBUILD_MODNAME;
1311 }
1312
1313 static void pch_uart_release_port(struct uart_port *port)
1314 {
1315         struct eg20t_port *priv;
1316
1317         priv = container_of(port, struct eg20t_port, port);
1318         pci_iounmap(priv->pdev, priv->membase);
1319         pci_release_regions(priv->pdev);
1320 }
1321
1322 static int pch_uart_request_port(struct uart_port *port)
1323 {
1324         struct eg20t_port *priv;
1325         int ret;
1326         void __iomem *membase;
1327
1328         priv = container_of(port, struct eg20t_port, port);
1329         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1330         if (ret < 0)
1331                 return -EBUSY;
1332
1333         membase = pci_iomap(priv->pdev, 1, 0);
1334         if (!membase) {
1335                 pci_release_regions(priv->pdev);
1336                 return -EBUSY;
1337         }
1338         priv->membase = port->membase = membase;
1339
1340         return 0;
1341 }
1342
1343 static void pch_uart_config_port(struct uart_port *port, int type)
1344 {
1345         struct eg20t_port *priv;
1346
1347         priv = container_of(port, struct eg20t_port, port);
1348         if (type & UART_CONFIG_TYPE) {
1349                 port->type = priv->port_type;
1350                 pch_uart_request_port(port);
1351         }
1352 }
1353
1354 static int pch_uart_verify_port(struct uart_port *port,
1355                                 struct serial_struct *serinfo)
1356 {
1357         struct eg20t_port *priv;
1358
1359         priv = container_of(port, struct eg20t_port, port);
1360         if (serinfo->flags & UPF_LOW_LATENCY) {
1361                 dev_info(priv->port.dev,
1362                         "PCH UART : Use PIO Mode (without DMA)\n");
1363                 priv->use_dma = 0;
1364                 serinfo->flags &= ~UPF_LOW_LATENCY;
1365         } else {
1366 #ifndef CONFIG_PCH_DMA
1367                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1368                         __func__);
1369                 return -EOPNOTSUPP;
1370 #endif
1371                 priv->use_dma_flag = 1;
1372                 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1373                 if (!priv->use_dma)
1374                         pch_request_dma(port);
1375                 priv->use_dma = 1;
1376         }
1377
1378         return 0;
1379 }
1380
1381 static struct uart_ops pch_uart_ops = {
1382         .tx_empty = pch_uart_tx_empty,
1383         .set_mctrl = pch_uart_set_mctrl,
1384         .get_mctrl = pch_uart_get_mctrl,
1385         .stop_tx = pch_uart_stop_tx,
1386         .start_tx = pch_uart_start_tx,
1387         .stop_rx = pch_uart_stop_rx,
1388         .enable_ms = pch_uart_enable_ms,
1389         .break_ctl = pch_uart_break_ctl,
1390         .startup = pch_uart_startup,
1391         .shutdown = pch_uart_shutdown,
1392         .set_termios = pch_uart_set_termios,
1393 /*      .pm             = pch_uart_pm,          Not supported yet */
1394 /*      .set_wake       = pch_uart_set_wake,    Not supported yet */
1395         .type = pch_uart_type,
1396         .release_port = pch_uart_release_port,
1397         .request_port = pch_uart_request_port,
1398         .config_port = pch_uart_config_port,
1399         .verify_port = pch_uart_verify_port
1400 };
1401
1402 static struct uart_driver pch_uart_driver = {
1403         .owner = THIS_MODULE,
1404         .driver_name = KBUILD_MODNAME,
1405         .dev_name = PCH_UART_DRIVER_DEVICE,
1406         .major = 0,
1407         .minor = 0,
1408         .nr = PCH_UART_NR,
1409 };
1410
1411 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1412                                              const struct pci_device_id *id)
1413 {
1414         struct eg20t_port *priv;
1415         int ret;
1416         unsigned int iobase;
1417         unsigned int mapbase;
1418         unsigned char *rxbuf;
1419         int fifosize, base_baud;
1420         int port_type;
1421         struct pch_uart_driver_data *board;
1422         const char *board_name;
1423
1424         board = &drv_dat[id->driver_data];
1425         port_type = board->port_type;
1426
1427         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1428         if (priv == NULL)
1429                 goto init_port_alloc_err;
1430
1431         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1432         if (!rxbuf)
1433                 goto init_port_free_txbuf;
1434
1435         base_baud = 1843200; /* 1.8432MHz */
1436
1437         /* quirk for CM-iTC board */
1438         board_name = dmi_get_system_info(DMI_BOARD_NAME);
1439         if (board_name && strstr(board_name, "CM-iTC"))
1440                 base_baud = 192000000; /* 192.0MHz */
1441
1442         switch (port_type) {
1443         case PORT_UNKNOWN:
1444                 fifosize = 256; /* EG20T/ML7213: UART0 */
1445                 break;
1446         case PORT_8250:
1447                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1448                 break;
1449         default:
1450                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1451                 goto init_port_hal_free;
1452         }
1453
1454         pci_enable_msi(pdev);
1455         pci_set_master(pdev);
1456
1457         spin_lock_init(&priv->lock);
1458
1459         iobase = pci_resource_start(pdev, 0);
1460         mapbase = pci_resource_start(pdev, 1);
1461         priv->mapbase = mapbase;
1462         priv->iobase = iobase;
1463         priv->pdev = pdev;
1464         priv->tx_empty = 1;
1465         priv->rxbuf.buf = rxbuf;
1466         priv->rxbuf.size = PAGE_SIZE;
1467
1468         priv->fifo_size = fifosize;
1469         priv->base_baud = base_baud;
1470         priv->port_type = PORT_MAX_8250 + port_type + 1;
1471         priv->port.dev = &pdev->dev;
1472         priv->port.iobase = iobase;
1473         priv->port.membase = NULL;
1474         priv->port.mapbase = mapbase;
1475         priv->port.irq = pdev->irq;
1476         priv->port.iotype = UPIO_PORT;
1477         priv->port.ops = &pch_uart_ops;
1478         priv->port.flags = UPF_BOOT_AUTOCONF;
1479         priv->port.fifosize = fifosize;
1480         priv->port.line = board->line_no;
1481         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1482
1483         spin_lock_init(&priv->port.lock);
1484
1485         pci_set_drvdata(pdev, priv);
1486         pch_uart_hal_request(pdev, fifosize, base_baud);
1487
1488         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1489         if (ret < 0)
1490                 goto init_port_hal_free;
1491
1492         return priv;
1493
1494 init_port_hal_free:
1495         free_page((unsigned long)rxbuf);
1496 init_port_free_txbuf:
1497         kfree(priv);
1498 init_port_alloc_err:
1499
1500         return NULL;
1501 }
1502
1503 static void pch_uart_exit_port(struct eg20t_port *priv)
1504 {
1505         uart_remove_one_port(&pch_uart_driver, &priv->port);
1506         pci_set_drvdata(priv->pdev, NULL);
1507         free_page((unsigned long)priv->rxbuf.buf);
1508 }
1509
1510 static void pch_uart_pci_remove(struct pci_dev *pdev)
1511 {
1512         struct eg20t_port *priv;
1513
1514         priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1515
1516         pci_disable_msi(pdev);
1517         pch_uart_exit_port(priv);
1518         pci_disable_device(pdev);
1519         kfree(priv);
1520         return;
1521 }
1522 #ifdef CONFIG_PM
1523 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1524 {
1525         struct eg20t_port *priv = pci_get_drvdata(pdev);
1526
1527         uart_suspend_port(&pch_uart_driver, &priv->port);
1528
1529         pci_save_state(pdev);
1530         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1531         return 0;
1532 }
1533
1534 static int pch_uart_pci_resume(struct pci_dev *pdev)
1535 {
1536         struct eg20t_port *priv = pci_get_drvdata(pdev);
1537         int ret;
1538
1539         pci_set_power_state(pdev, PCI_D0);
1540         pci_restore_state(pdev);
1541
1542         ret = pci_enable_device(pdev);
1543         if (ret) {
1544                 dev_err(&pdev->dev,
1545                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1546                 return ret;
1547         }
1548
1549         uart_resume_port(&pch_uart_driver, &priv->port);
1550
1551         return 0;
1552 }
1553 #else
1554 #define pch_uart_pci_suspend NULL
1555 #define pch_uart_pci_resume NULL
1556 #endif
1557
1558 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1559         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1560          .driver_data = pch_et20t_uart0},
1561         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1562          .driver_data = pch_et20t_uart1},
1563         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1564          .driver_data = pch_et20t_uart2},
1565         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1566          .driver_data = pch_et20t_uart3},
1567         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1568          .driver_data = pch_ml7213_uart0},
1569         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1570          .driver_data = pch_ml7213_uart1},
1571         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1572          .driver_data = pch_ml7213_uart2},
1573         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1574          .driver_data = pch_ml7223_uart0},
1575         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1576          .driver_data = pch_ml7223_uart1},
1577         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1578          .driver_data = pch_ml7831_uart0},
1579         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1580          .driver_data = pch_ml7831_uart1},
1581         {0,},
1582 };
1583
1584 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1585                                         const struct pci_device_id *id)
1586 {
1587         int ret;
1588         struct eg20t_port *priv;
1589
1590         ret = pci_enable_device(pdev);
1591         if (ret < 0)
1592                 goto probe_error;
1593
1594         priv = pch_uart_init_port(pdev, id);
1595         if (!priv) {
1596                 ret = -EBUSY;
1597                 goto probe_disable_device;
1598         }
1599         pci_set_drvdata(pdev, priv);
1600
1601         return ret;
1602
1603 probe_disable_device:
1604         pci_disable_msi(pdev);
1605         pci_disable_device(pdev);
1606 probe_error:
1607         return ret;
1608 }
1609
1610 static struct pci_driver pch_uart_pci_driver = {
1611         .name = "pch_uart",
1612         .id_table = pch_uart_pci_id,
1613         .probe = pch_uart_pci_probe,
1614         .remove = __devexit_p(pch_uart_pci_remove),
1615         .suspend = pch_uart_pci_suspend,
1616         .resume = pch_uart_pci_resume,
1617 };
1618
1619 static int __init pch_uart_module_init(void)
1620 {
1621         int ret;
1622
1623         /* register as UART driver */
1624         ret = uart_register_driver(&pch_uart_driver);
1625         if (ret < 0)
1626                 return ret;
1627
1628         /* register as PCI driver */
1629         ret = pci_register_driver(&pch_uart_pci_driver);
1630         if (ret < 0)
1631                 uart_unregister_driver(&pch_uart_driver);
1632
1633         return ret;
1634 }
1635 module_init(pch_uart_module_init);
1636
1637 static void __exit pch_uart_module_exit(void)
1638 {
1639         pci_unregister_driver(&pch_uart_pci_driver);
1640         uart_unregister_driver(&pch_uart_driver);
1641 }
1642 module_exit(pch_uart_module_exit);
1643
1644 MODULE_LICENSE("GPL v2");
1645 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1646 module_param(default_baud, uint, S_IRUGO);