2 * Driver for msm7k serial device and console
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
22 #include <linux/atomic.h>
23 #include <linux/hrtimer.h>
24 #include <linux/module.h>
26 #include <linux/ioport.h>
27 #include <linux/irq.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/platform_device.h>
36 #include <linux/delay.h>
38 #include <linux/of_device.h>
40 #include "msm_serial.h"
43 struct uart_port uart;
48 void __iomem *gsbi_base;
50 unsigned int old_snap_state;
53 static inline void wait_for_xmitr(struct uart_port *port)
55 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
56 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
60 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
63 static void msm_stop_tx(struct uart_port *port)
65 struct msm_port *msm_port = UART_TO_MSM(port);
67 msm_port->imr &= ~UART_IMR_TXLEV;
68 msm_write(port, msm_port->imr, UART_IMR);
71 static void msm_start_tx(struct uart_port *port)
73 struct msm_port *msm_port = UART_TO_MSM(port);
75 msm_port->imr |= UART_IMR_TXLEV;
76 msm_write(port, msm_port->imr, UART_IMR);
79 static void msm_stop_rx(struct uart_port *port)
81 struct msm_port *msm_port = UART_TO_MSM(port);
83 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
84 msm_write(port, msm_port->imr, UART_IMR);
87 static void msm_enable_ms(struct uart_port *port)
89 struct msm_port *msm_port = UART_TO_MSM(port);
91 msm_port->imr |= UART_IMR_DELTA_CTS;
92 msm_write(port, msm_port->imr, UART_IMR);
95 static void handle_rx_dm(struct uart_port *port, unsigned int misr)
97 struct tty_port *tport = &port->state->port;
100 struct msm_port *msm_port = UART_TO_MSM(port);
102 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
103 port->icount.overrun++;
104 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
105 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
108 if (misr & UART_IMR_RXSTALE) {
109 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
110 msm_port->old_snap_state;
111 msm_port->old_snap_state = 0;
113 count = 4 * (msm_read(port, UART_RFWR));
114 msm_port->old_snap_state += count;
117 /* TODO: Precise error reporting */
119 port->icount.rx += count;
124 sr = msm_read(port, UART_SR);
125 if ((sr & UART_SR_RX_READY) == 0) {
126 msm_port->old_snap_state -= count;
129 c = msm_read(port, UARTDM_RF);
130 if (sr & UART_SR_RX_BREAK) {
132 if (uart_handle_break(port))
134 } else if (sr & UART_SR_PAR_FRAME_ERR)
135 port->icount.frame++;
137 /* TODO: handle sysrq */
138 tty_insert_flip_string(tport, (char *)&c,
139 (count > 4) ? 4 : count);
143 tty_flip_buffer_push(tport);
144 if (misr & (UART_IMR_RXSTALE))
145 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
146 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
147 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
150 static void handle_rx(struct uart_port *port)
152 struct tty_port *tport = &port->state->port;
156 * Handle overrun. My understanding of the hardware is that overrun
157 * is not tied to the RX buffer, so we handle the case out of band.
159 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
160 port->icount.overrun++;
161 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
162 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
165 /* and now the main RX loop */
166 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
168 char flag = TTY_NORMAL;
170 c = msm_read(port, UART_RF);
172 if (sr & UART_SR_RX_BREAK) {
174 if (uart_handle_break(port))
176 } else if (sr & UART_SR_PAR_FRAME_ERR) {
177 port->icount.frame++;
182 /* Mask conditions we're ignorning. */
183 sr &= port->read_status_mask;
185 if (sr & UART_SR_RX_BREAK) {
187 } else if (sr & UART_SR_PAR_FRAME_ERR) {
191 if (!uart_handle_sysrq_char(port, c))
192 tty_insert_flip_char(tport, c, flag);
195 tty_flip_buffer_push(tport);
198 static void reset_dm_count(struct uart_port *port)
200 wait_for_xmitr(port);
201 msm_write(port, 1, UARTDM_NCF_TX);
202 msm_read(port, UARTDM_NCF_TX);
205 static void handle_tx(struct uart_port *port)
207 struct circ_buf *xmit = &port->state->xmit;
208 struct msm_port *msm_port = UART_TO_MSM(port);
212 if (msm_port->is_uartdm)
213 reset_dm_count(port);
215 msm_write(port, port->x_char,
216 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
221 if (msm_port->is_uartdm)
222 reset_dm_count(port);
224 while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
225 if (uart_circ_empty(xmit)) {
226 /* disable tx interrupts */
227 msm_port->imr &= ~UART_IMR_TXLEV;
228 msm_write(port, msm_port->imr, UART_IMR);
231 msm_write(port, xmit->buf[xmit->tail],
232 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
234 if (msm_port->is_uartdm)
235 reset_dm_count(port);
237 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
242 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
243 uart_write_wakeup(port);
246 static void handle_delta_cts(struct uart_port *port)
248 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
250 wake_up_interruptible(&port->state->port.delta_msr_wait);
253 static irqreturn_t msm_irq(int irq, void *dev_id)
255 struct uart_port *port = dev_id;
256 struct msm_port *msm_port = UART_TO_MSM(port);
259 spin_lock(&port->lock);
260 misr = msm_read(port, UART_MISR);
261 msm_write(port, 0, UART_IMR); /* disable interrupt */
263 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
264 if (msm_port->is_uartdm)
265 handle_rx_dm(port, misr);
269 if (misr & UART_IMR_TXLEV)
271 if (misr & UART_IMR_DELTA_CTS)
272 handle_delta_cts(port);
274 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
275 spin_unlock(&port->lock);
280 static unsigned int msm_tx_empty(struct uart_port *port)
282 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
285 static unsigned int msm_get_mctrl(struct uart_port *port)
287 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
291 static void msm_reset(struct uart_port *port)
293 /* reset everything */
294 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
295 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
296 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
297 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
298 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
299 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
302 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
305 mr = msm_read(port, UART_MR1);
307 if (!(mctrl & TIOCM_RTS)) {
308 mr &= ~UART_MR1_RX_RDY_CTL;
309 msm_write(port, mr, UART_MR1);
310 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
312 mr |= UART_MR1_RX_RDY_CTL;
313 msm_write(port, mr, UART_MR1);
317 static void msm_break_ctl(struct uart_port *port, int break_ctl)
320 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
322 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
325 struct msm_baud_map {
331 static const struct msm_baud_map *
332 msm_find_best_baud(struct uart_port *port, unsigned int baud)
334 unsigned int i, divisor;
335 const struct msm_baud_map *entry;
336 static const struct msm_baud_map table[] = {
355 divisor = uart_get_divisor(port, baud);
357 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++)
358 if (entry->divisor <= divisor)
361 return entry; /* Default to smallest divider */
364 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
366 unsigned int rxstale, watermark;
367 struct msm_port *msm_port = UART_TO_MSM(port);
368 const struct msm_baud_map *entry;
370 entry = msm_find_best_baud(port, baud);
372 if (msm_port->is_uartdm)
373 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
375 msm_write(port, entry->code, UART_CSR);
377 /* RX stale watermark */
378 rxstale = entry->rxstale;
379 watermark = UART_IPR_STALE_LSB & rxstale;
380 watermark |= UART_IPR_RXSTALE_LAST;
381 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
382 msm_write(port, watermark, UART_IPR);
384 /* set RX watermark */
385 watermark = (port->fifosize * 3) / 4;
386 msm_write(port, watermark, UART_RFWR);
388 /* set TX watermark */
389 msm_write(port, 10, UART_TFWR);
391 if (msm_port->is_uartdm) {
392 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
393 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
394 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
401 static void msm_init_clock(struct uart_port *port)
403 struct msm_port *msm_port = UART_TO_MSM(port);
405 clk_prepare_enable(msm_port->clk);
406 if (!IS_ERR(msm_port->pclk))
407 clk_prepare_enable(msm_port->pclk);
408 msm_serial_set_mnd_regs(port);
411 static int msm_startup(struct uart_port *port)
413 struct msm_port *msm_port = UART_TO_MSM(port);
414 unsigned int data, rfr_level;
417 snprintf(msm_port->name, sizeof(msm_port->name),
418 "msm_serial%d", port->line);
420 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
421 msm_port->name, port);
425 msm_init_clock(port);
427 if (likely(port->fifosize > 12))
428 rfr_level = port->fifosize - 12;
430 rfr_level = port->fifosize;
432 /* set automatic RFR level */
433 data = msm_read(port, UART_MR1);
434 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
435 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
436 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
437 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
438 msm_write(port, data, UART_MR1);
440 /* make sure that RXSTALE count is non-zero */
441 data = msm_read(port, UART_IPR);
442 if (unlikely(!data)) {
443 data |= UART_IPR_RXSTALE_LAST;
444 data |= UART_IPR_STALE_LSB;
445 msm_write(port, data, UART_IPR);
449 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
450 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
452 data = UART_CR_TX_ENABLE;
455 data |= UART_CR_RX_ENABLE;
456 msm_write(port, data, UART_CR); /* enable TX & RX */
458 /* Make sure IPR is not 0 to start with*/
459 if (msm_port->is_uartdm)
460 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
462 /* turn on RX and CTS interrupts */
463 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
464 UART_IMR_CURRENT_CTS;
466 if (msm_port->is_uartdm) {
467 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
468 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
469 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
472 msm_write(port, msm_port->imr, UART_IMR);
476 static void msm_shutdown(struct uart_port *port)
478 struct msm_port *msm_port = UART_TO_MSM(port);
481 msm_write(port, 0, UART_IMR); /* disable interrupts */
483 clk_disable_unprepare(msm_port->clk);
485 free_irq(port->irq, port);
488 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
489 struct ktermios *old)
492 unsigned int baud, mr;
494 spin_lock_irqsave(&port->lock, flags);
496 /* calculate and set baud rate */
497 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
498 baud = msm_set_baud_rate(port, baud);
499 if (tty_termios_baud_rate(termios))
500 tty_termios_encode_baud_rate(termios, baud, baud);
502 /* calculate parity */
503 mr = msm_read(port, UART_MR2);
504 mr &= ~UART_MR2_PARITY_MODE;
505 if (termios->c_cflag & PARENB) {
506 if (termios->c_cflag & PARODD)
507 mr |= UART_MR2_PARITY_MODE_ODD;
508 else if (termios->c_cflag & CMSPAR)
509 mr |= UART_MR2_PARITY_MODE_SPACE;
511 mr |= UART_MR2_PARITY_MODE_EVEN;
514 /* calculate bits per char */
515 mr &= ~UART_MR2_BITS_PER_CHAR;
516 switch (termios->c_cflag & CSIZE) {
518 mr |= UART_MR2_BITS_PER_CHAR_5;
521 mr |= UART_MR2_BITS_PER_CHAR_6;
524 mr |= UART_MR2_BITS_PER_CHAR_7;
528 mr |= UART_MR2_BITS_PER_CHAR_8;
532 /* calculate stop bits */
533 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
534 if (termios->c_cflag & CSTOPB)
535 mr |= UART_MR2_STOP_BIT_LEN_TWO;
537 mr |= UART_MR2_STOP_BIT_LEN_ONE;
539 /* set parity, bits per char, and stop bit */
540 msm_write(port, mr, UART_MR2);
542 /* calculate and set hardware flow control */
543 mr = msm_read(port, UART_MR1);
544 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
545 if (termios->c_cflag & CRTSCTS) {
546 mr |= UART_MR1_CTS_CTL;
547 mr |= UART_MR1_RX_RDY_CTL;
549 msm_write(port, mr, UART_MR1);
551 /* Configure status bits to ignore based on termio flags. */
552 port->read_status_mask = 0;
553 if (termios->c_iflag & INPCK)
554 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
555 if (termios->c_iflag & (BRKINT | PARMRK))
556 port->read_status_mask |= UART_SR_RX_BREAK;
558 uart_update_timeout(port, termios->c_cflag, baud);
560 spin_unlock_irqrestore(&port->lock, flags);
563 static const char *msm_type(struct uart_port *port)
568 static void msm_release_port(struct uart_port *port)
570 struct platform_device *pdev = to_platform_device(port->dev);
571 struct msm_port *msm_port = UART_TO_MSM(port);
572 struct resource *uart_resource;
573 struct resource *gsbi_resource;
574 resource_size_t size;
576 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
577 if (unlikely(!uart_resource))
579 size = resource_size(uart_resource);
581 release_mem_region(port->mapbase, size);
582 iounmap(port->membase);
583 port->membase = NULL;
585 if (msm_port->gsbi_base) {
586 writel_relaxed(GSBI_PROTOCOL_IDLE,
587 msm_port->gsbi_base + GSBI_CONTROL);
589 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
590 if (unlikely(!gsbi_resource))
593 size = resource_size(gsbi_resource);
594 release_mem_region(gsbi_resource->start, size);
595 iounmap(msm_port->gsbi_base);
596 msm_port->gsbi_base = NULL;
600 static int msm_request_port(struct uart_port *port)
602 struct msm_port *msm_port = UART_TO_MSM(port);
603 struct platform_device *pdev = to_platform_device(port->dev);
604 struct resource *uart_resource;
605 struct resource *gsbi_resource;
606 resource_size_t size;
609 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
610 if (unlikely(!uart_resource))
613 size = resource_size(uart_resource);
615 if (!request_mem_region(port->mapbase, size, "msm_serial"))
618 port->membase = ioremap(port->mapbase, size);
619 if (!port->membase) {
621 goto fail_release_port;
624 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
625 /* Is this a GSBI-based port? */
627 size = resource_size(gsbi_resource);
629 if (!request_mem_region(gsbi_resource->start, size,
632 goto fail_release_port_membase;
635 msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
636 if (!msm_port->gsbi_base) {
638 goto fail_release_gsbi;
645 release_mem_region(gsbi_resource->start, size);
646 fail_release_port_membase:
647 iounmap(port->membase);
649 release_mem_region(port->mapbase, size);
653 static void msm_config_port(struct uart_port *port, int flags)
655 struct msm_port *msm_port = UART_TO_MSM(port);
657 if (flags & UART_CONFIG_TYPE) {
658 port->type = PORT_MSM;
659 ret = msm_request_port(port);
663 if (msm_port->is_uartdm)
664 writel_relaxed(GSBI_PROTOCOL_UART,
665 msm_port->gsbi_base + GSBI_CONTROL);
668 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
670 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
672 if (unlikely(port->irq != ser->irq))
677 static void msm_power(struct uart_port *port, unsigned int state,
678 unsigned int oldstate)
680 struct msm_port *msm_port = UART_TO_MSM(port);
684 clk_prepare_enable(msm_port->clk);
685 if (!IS_ERR(msm_port->pclk))
686 clk_prepare_enable(msm_port->pclk);
689 clk_disable_unprepare(msm_port->clk);
690 if (!IS_ERR(msm_port->pclk))
691 clk_disable_unprepare(msm_port->pclk);
694 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
698 static struct uart_ops msm_uart_pops = {
699 .tx_empty = msm_tx_empty,
700 .set_mctrl = msm_set_mctrl,
701 .get_mctrl = msm_get_mctrl,
702 .stop_tx = msm_stop_tx,
703 .start_tx = msm_start_tx,
704 .stop_rx = msm_stop_rx,
705 .enable_ms = msm_enable_ms,
706 .break_ctl = msm_break_ctl,
707 .startup = msm_startup,
708 .shutdown = msm_shutdown,
709 .set_termios = msm_set_termios,
711 .release_port = msm_release_port,
712 .request_port = msm_request_port,
713 .config_port = msm_config_port,
714 .verify_port = msm_verify_port,
718 static struct msm_port msm_uart_ports[] = {
722 .ops = &msm_uart_pops,
723 .flags = UPF_BOOT_AUTOCONF,
731 .ops = &msm_uart_pops,
732 .flags = UPF_BOOT_AUTOCONF,
740 .ops = &msm_uart_pops,
741 .flags = UPF_BOOT_AUTOCONF,
748 #define UART_NR ARRAY_SIZE(msm_uart_ports)
750 static inline struct uart_port *get_port_from_line(unsigned int line)
752 return &msm_uart_ports[line].uart;
755 #ifdef CONFIG_SERIAL_MSM_CONSOLE
757 static void msm_console_putchar(struct uart_port *port, int c)
759 struct msm_port *msm_port = UART_TO_MSM(port);
761 if (msm_port->is_uartdm)
762 reset_dm_count(port);
764 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
766 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
769 static void msm_console_write(struct console *co, const char *s,
772 struct uart_port *port;
773 struct msm_port *msm_port;
775 BUG_ON(co->index < 0 || co->index >= UART_NR);
777 port = get_port_from_line(co->index);
778 msm_port = UART_TO_MSM(port);
780 spin_lock(&port->lock);
781 uart_console_write(port, s, count, msm_console_putchar);
782 spin_unlock(&port->lock);
785 static int __init msm_console_setup(struct console *co, char *options)
787 struct uart_port *port;
788 struct msm_port *msm_port;
789 int baud, flow, bits, parity;
791 if (unlikely(co->index >= UART_NR || co->index < 0))
794 port = get_port_from_line(co->index);
795 msm_port = UART_TO_MSM(port);
797 if (unlikely(!port->membase))
800 msm_init_clock(port);
803 uart_parse_options(options, &baud, &parity, &bits, &flow);
808 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
811 if (baud < 300 || baud > 115200)
813 msm_set_baud_rate(port, baud);
817 if (msm_port->is_uartdm) {
818 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
819 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
822 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
824 return uart_set_options(port, co, baud, parity, bits, flow);
827 static struct uart_driver msm_uart_driver;
829 static struct console msm_console = {
831 .write = msm_console_write,
832 .device = uart_console_device,
833 .setup = msm_console_setup,
834 .flags = CON_PRINTBUFFER,
836 .data = &msm_uart_driver,
839 #define MSM_CONSOLE (&msm_console)
842 #define MSM_CONSOLE NULL
845 static struct uart_driver msm_uart_driver = {
846 .owner = THIS_MODULE,
847 .driver_name = "msm_serial",
848 .dev_name = "ttyMSM",
853 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
855 static int __init msm_serial_probe(struct platform_device *pdev)
857 struct msm_port *msm_port;
858 struct resource *resource;
859 struct uart_port *port;
863 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
865 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
868 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
870 port = get_port_from_line(pdev->id);
871 port->dev = &pdev->dev;
872 msm_port = UART_TO_MSM(port);
874 if (platform_get_resource(pdev, IORESOURCE_MEM, 1))
875 msm_port->is_uartdm = 1;
877 msm_port->is_uartdm = 0;
879 if (msm_port->is_uartdm) {
880 msm_port->clk = devm_clk_get(&pdev->dev, "gsbi_uart_clk");
881 msm_port->pclk = devm_clk_get(&pdev->dev, "gsbi_pclk");
883 msm_port->clk = devm_clk_get(&pdev->dev, "uart_clk");
884 msm_port->pclk = ERR_PTR(-ENOENT);
887 if (IS_ERR(msm_port->clk))
888 return PTR_ERR(msm_port->clk);
890 if (msm_port->is_uartdm) {
891 if (IS_ERR(msm_port->pclk))
892 return PTR_ERR(msm_port->pclk);
894 clk_set_rate(msm_port->clk, 1843200);
897 port->uartclk = clk_get_rate(msm_port->clk);
898 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
901 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
902 if (unlikely(!resource))
904 port->mapbase = resource->start;
906 irq = platform_get_irq(pdev, 0);
907 if (unlikely(irq < 0))
911 platform_set_drvdata(pdev, port);
913 return uart_add_one_port(&msm_uart_driver, port);
916 static int msm_serial_remove(struct platform_device *pdev)
918 struct uart_port *port = platform_get_drvdata(pdev);
920 uart_remove_one_port(&msm_uart_driver, port);
925 static struct of_device_id msm_match_table[] = {
926 { .compatible = "qcom,msm-uart" },
930 static struct platform_driver msm_platform_driver = {
931 .remove = msm_serial_remove,
933 .name = "msm_serial",
934 .owner = THIS_MODULE,
935 .of_match_table = msm_match_table,
939 static int __init msm_serial_init(void)
943 ret = uart_register_driver(&msm_uart_driver);
947 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
949 uart_unregister_driver(&msm_uart_driver);
951 printk(KERN_INFO "msm_serial: driver initialized\n");
956 static void __exit msm_serial_exit(void)
958 #ifdef CONFIG_SERIAL_MSM_CONSOLE
959 unregister_console(&msm_console);
961 platform_driver_unregister(&msm_platform_driver);
962 uart_unregister_driver(&msm_uart_driver);
965 module_init(msm_serial_init);
966 module_exit(msm_serial_exit);
968 MODULE_AUTHOR("Robert Love <rlove@google.com>");
969 MODULE_DESCRIPTION("Driver for msm7x serial device");
970 MODULE_LICENSE("GPL");