c1c1e525444ac9b99841c258df58c1a540189dd4
[pandora-kernel.git] / drivers / tty / serial / 8250_pci.c
1 /*
2  *  Probe module for 8250/16550-type PCI serial ports.
3  *
4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5  *
6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License.
11  */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_core.h>
21 #include <linux/8250_pci.h>
22 #include <linux/bitops.h>
23
24 #include <asm/byteorder.h>
25 #include <asm/io.h>
26
27 #include "8250.h"
28
29 #undef SERIAL_DEBUG_PCI
30
31 /*
32  * init function returns:
33  *  > 0 - number of ports
34  *  = 0 - use board->num_ports
35  *  < 0 - error
36  */
37 struct pci_serial_quirk {
38         u32     vendor;
39         u32     device;
40         u32     subvendor;
41         u32     subdevice;
42         int     (*probe)(struct pci_dev *dev);
43         int     (*init)(struct pci_dev *dev);
44         int     (*setup)(struct serial_private *,
45                          const struct pciserial_board *,
46                          struct uart_port *, int);
47         void    (*exit)(struct pci_dev *dev);
48 };
49
50 #define PCI_NUM_BAR_RESOURCES   6
51
52 struct serial_private {
53         struct pci_dev          *dev;
54         unsigned int            nr;
55         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
56         struct pci_serial_quirk *quirk;
57         int                     line[0];
58 };
59
60 static int pci_default_setup(struct serial_private*,
61           const struct pciserial_board*, struct uart_port*, int);
62
63 static void moan_device(const char *str, struct pci_dev *dev)
64 {
65         printk(KERN_WARNING
66                "%s: %s\n"
67                "Please send the output of lspci -vv, this\n"
68                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
69                "manufacturer and name of serial board or\n"
70                "modem board to <linux-serial@vger.kernel.org>.\n",
71                pci_name(dev), str, dev->vendor, dev->device,
72                dev->subsystem_vendor, dev->subsystem_device);
73 }
74
75 static int
76 setup_port(struct serial_private *priv, struct uart_port *port,
77            int bar, int offset, int regshift)
78 {
79         struct pci_dev *dev = priv->dev;
80         unsigned long base, len;
81
82         if (bar >= PCI_NUM_BAR_RESOURCES)
83                 return -EINVAL;
84
85         base = pci_resource_start(dev, bar);
86
87         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
88                 len =  pci_resource_len(dev, bar);
89
90                 if (!priv->remapped_bar[bar])
91                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
92                 if (!priv->remapped_bar[bar])
93                         return -ENOMEM;
94
95                 port->iotype = UPIO_MEM;
96                 port->iobase = 0;
97                 port->mapbase = base + offset;
98                 port->membase = priv->remapped_bar[bar] + offset;
99                 port->regshift = regshift;
100         } else {
101                 port->iotype = UPIO_PORT;
102                 port->iobase = base + offset;
103                 port->mapbase = 0;
104                 port->membase = NULL;
105                 port->regshift = 0;
106         }
107         return 0;
108 }
109
110 /*
111  * ADDI-DATA GmbH communication cards <info@addi-data.com>
112  */
113 static int addidata_apci7800_setup(struct serial_private *priv,
114                                 const struct pciserial_board *board,
115                                 struct uart_port *port, int idx)
116 {
117         unsigned int bar = 0, offset = board->first_offset;
118         bar = FL_GET_BASE(board->flags);
119
120         if (idx < 2) {
121                 offset += idx * board->uart_offset;
122         } else if ((idx >= 2) && (idx < 4)) {
123                 bar += 1;
124                 offset += ((idx - 2) * board->uart_offset);
125         } else if ((idx >= 4) && (idx < 6)) {
126                 bar += 2;
127                 offset += ((idx - 4) * board->uart_offset);
128         } else if (idx >= 6) {
129                 bar += 3;
130                 offset += ((idx - 6) * board->uart_offset);
131         }
132
133         return setup_port(priv, port, bar, offset, board->reg_shift);
134 }
135
136 /*
137  * AFAVLAB uses a different mixture of BARs and offsets
138  * Not that ugly ;) -- HW
139  */
140 static int
141 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
142               struct uart_port *port, int idx)
143 {
144         unsigned int bar, offset = board->first_offset;
145
146         bar = FL_GET_BASE(board->flags);
147         if (idx < 4)
148                 bar += idx;
149         else {
150                 bar = 4;
151                 offset += (idx - 4) * board->uart_offset;
152         }
153
154         return setup_port(priv, port, bar, offset, board->reg_shift);
155 }
156
157 /*
158  * HP's Remote Management Console.  The Diva chip came in several
159  * different versions.  N-class, L2000 and A500 have two Diva chips, each
160  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
161  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
162  * one Diva chip, but it has been expanded to 5 UARTs.
163  */
164 static int pci_hp_diva_init(struct pci_dev *dev)
165 {
166         int rc = 0;
167
168         switch (dev->subsystem_device) {
169         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
170         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
171         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
172         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
173                 rc = 3;
174                 break;
175         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
176                 rc = 2;
177                 break;
178         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
179                 rc = 4;
180                 break;
181         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
182         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
183                 rc = 1;
184                 break;
185         }
186
187         return rc;
188 }
189
190 /*
191  * HP's Diva chip puts the 4th/5th serial port further out, and
192  * some serial ports are supposed to be hidden on certain models.
193  */
194 static int
195 pci_hp_diva_setup(struct serial_private *priv,
196                 const struct pciserial_board *board,
197                 struct uart_port *port, int idx)
198 {
199         unsigned int offset = board->first_offset;
200         unsigned int bar = FL_GET_BASE(board->flags);
201
202         switch (priv->dev->subsystem_device) {
203         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
204                 if (idx == 3)
205                         idx++;
206                 break;
207         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
208                 if (idx > 0)
209                         idx++;
210                 if (idx > 2)
211                         idx++;
212                 break;
213         }
214         if (idx > 2)
215                 offset = 0x18;
216
217         offset += idx * board->uart_offset;
218
219         return setup_port(priv, port, bar, offset, board->reg_shift);
220 }
221
222 /*
223  * Added for EKF Intel i960 serial boards
224  */
225 static int pci_inteli960ni_init(struct pci_dev *dev)
226 {
227         unsigned long oldval;
228
229         if (!(dev->subsystem_device & 0x1000))
230                 return -ENODEV;
231
232         /* is firmware started? */
233         pci_read_config_dword(dev, 0x44, (void *)&oldval);
234         if (oldval == 0x00001000L) { /* RESET value */
235                 printk(KERN_DEBUG "Local i960 firmware missing");
236                 return -ENODEV;
237         }
238         return 0;
239 }
240
241 /*
242  * Some PCI serial cards using the PLX 9050 PCI interface chip require
243  * that the card interrupt be explicitly enabled or disabled.  This
244  * seems to be mainly needed on card using the PLX which also use I/O
245  * mapped memory.
246  */
247 static int pci_plx9050_init(struct pci_dev *dev)
248 {
249         u8 irq_config;
250         void __iomem *p;
251
252         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
253                 moan_device("no memory in bar 0", dev);
254                 return 0;
255         }
256
257         irq_config = 0x41;
258         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
259             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
260                 irq_config = 0x43;
261
262         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
263             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
264                 /*
265                  * As the megawolf cards have the int pins active
266                  * high, and have 2 UART chips, both ints must be
267                  * enabled on the 9050. Also, the UARTS are set in
268                  * 16450 mode by default, so we have to enable the
269                  * 16C950 'enhanced' mode so that we can use the
270                  * deep FIFOs
271                  */
272                 irq_config = 0x5b;
273         /*
274          * enable/disable interrupts
275          */
276         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
277         if (p == NULL)
278                 return -ENOMEM;
279         writel(irq_config, p + 0x4c);
280
281         /*
282          * Read the register back to ensure that it took effect.
283          */
284         readl(p + 0x4c);
285         iounmap(p);
286
287         return 0;
288 }
289
290 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
291 {
292         u8 __iomem *p;
293
294         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
295                 return;
296
297         /*
298          * disable interrupts
299          */
300         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
301         if (p != NULL) {
302                 writel(0, p + 0x4c);
303
304                 /*
305                  * Read the register back to ensure that it took effect.
306                  */
307                 readl(p + 0x4c);
308                 iounmap(p);
309         }
310 }
311
312 #define NI8420_INT_ENABLE_REG   0x38
313 #define NI8420_INT_ENABLE_BIT   0x2000
314
315 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
316 {
317         void __iomem *p;
318         unsigned long base, len;
319         unsigned int bar = 0;
320
321         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
322                 moan_device("no memory in bar", dev);
323                 return;
324         }
325
326         base = pci_resource_start(dev, bar);
327         len =  pci_resource_len(dev, bar);
328         p = ioremap_nocache(base, len);
329         if (p == NULL)
330                 return;
331
332         /* Disable the CPU Interrupt */
333         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
334                p + NI8420_INT_ENABLE_REG);
335         iounmap(p);
336 }
337
338
339 /* MITE registers */
340 #define MITE_IOWBSR1    0xc4
341 #define MITE_IOWCR1     0xf4
342 #define MITE_LCIMR1     0x08
343 #define MITE_LCIMR2     0x10
344
345 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
346
347 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
348 {
349         void __iomem *p;
350         unsigned long base, len;
351         unsigned int bar = 0;
352
353         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354                 moan_device("no memory in bar", dev);
355                 return;
356         }
357
358         base = pci_resource_start(dev, bar);
359         len =  pci_resource_len(dev, bar);
360         p = ioremap_nocache(base, len);
361         if (p == NULL)
362                 return;
363
364         /* Disable the CPU Interrupt */
365         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
366         iounmap(p);
367 }
368
369 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
370 static int
371 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
372                 struct uart_port *port, int idx)
373 {
374         unsigned int bar, offset = board->first_offset;
375
376         bar = 0;
377
378         if (idx < 4) {
379                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
380                 offset += idx * board->uart_offset;
381         } else if (idx < 8) {
382                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
383                 offset += idx * board->uart_offset + 0xC00;
384         } else /* we have only 8 ports on PMC-OCTALPRO */
385                 return 1;
386
387         return setup_port(priv, port, bar, offset, board->reg_shift);
388 }
389
390 /*
391 * This does initialization for PMC OCTALPRO cards:
392 * maps the device memory, resets the UARTs (needed, bc
393 * if the module is removed and inserted again, the card
394 * is in the sleep mode) and enables global interrupt.
395 */
396
397 /* global control register offset for SBS PMC-OctalPro */
398 #define OCT_REG_CR_OFF          0x500
399
400 static int sbs_init(struct pci_dev *dev)
401 {
402         u8 __iomem *p;
403
404         p = pci_ioremap_bar(dev, 0);
405
406         if (p == NULL)
407                 return -ENOMEM;
408         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
409         writeb(0x10, p + OCT_REG_CR_OFF);
410         udelay(50);
411         writeb(0x0, p + OCT_REG_CR_OFF);
412
413         /* Set bit-2 (INTENABLE) of Control Register */
414         writeb(0x4, p + OCT_REG_CR_OFF);
415         iounmap(p);
416
417         return 0;
418 }
419
420 /*
421  * Disables the global interrupt of PMC-OctalPro
422  */
423
424 static void __devexit sbs_exit(struct pci_dev *dev)
425 {
426         u8 __iomem *p;
427
428         p = pci_ioremap_bar(dev, 0);
429         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
430         if (p != NULL)
431                 writeb(0, p + OCT_REG_CR_OFF);
432         iounmap(p);
433 }
434
435 /*
436  * SIIG serial cards have an PCI interface chip which also controls
437  * the UART clocking frequency. Each UART can be clocked independently
438  * (except cards equipped with 4 UARTs) and initial clocking settings
439  * are stored in the EEPROM chip. It can cause problems because this
440  * version of serial driver doesn't support differently clocked UART's
441  * on single PCI card. To prevent this, initialization functions set
442  * high frequency clocking for all UART's on given card. It is safe (I
443  * hope) because it doesn't touch EEPROM settings to prevent conflicts
444  * with other OSes (like M$ DOS).
445  *
446  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
447  *
448  * There is two family of SIIG serial cards with different PCI
449  * interface chip and different configuration methods:
450  *     - 10x cards have control registers in IO and/or memory space;
451  *     - 20x cards have control registers in standard PCI configuration space.
452  *
453  * Note: all 10x cards have PCI device ids 0x10..
454  *       all 20x cards have PCI device ids 0x20..
455  *
456  * There are also Quartet Serial cards which use Oxford Semiconductor
457  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
458  *
459  * Note: some SIIG cards are probed by the parport_serial object.
460  */
461
462 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
463 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
464
465 static int pci_siig10x_init(struct pci_dev *dev)
466 {
467         u16 data;
468         void __iomem *p;
469
470         switch (dev->device & 0xfff8) {
471         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
472                 data = 0xffdf;
473                 break;
474         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
475                 data = 0xf7ff;
476                 break;
477         default:                        /* 1S1P, 4S */
478                 data = 0xfffb;
479                 break;
480         }
481
482         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
483         if (p == NULL)
484                 return -ENOMEM;
485
486         writew(readw(p + 0x28) & data, p + 0x28);
487         readw(p + 0x28);
488         iounmap(p);
489         return 0;
490 }
491
492 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
493 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
494
495 static int pci_siig20x_init(struct pci_dev *dev)
496 {
497         u8 data;
498
499         /* Change clock frequency for the first UART. */
500         pci_read_config_byte(dev, 0x6f, &data);
501         pci_write_config_byte(dev, 0x6f, data & 0xef);
502
503         /* If this card has 2 UART, we have to do the same with second UART. */
504         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
505             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
506                 pci_read_config_byte(dev, 0x73, &data);
507                 pci_write_config_byte(dev, 0x73, data & 0xef);
508         }
509         return 0;
510 }
511
512 static int pci_siig_init(struct pci_dev *dev)
513 {
514         unsigned int type = dev->device & 0xff00;
515
516         if (type == 0x1000)
517                 return pci_siig10x_init(dev);
518         else if (type == 0x2000)
519                 return pci_siig20x_init(dev);
520
521         moan_device("Unknown SIIG card", dev);
522         return -ENODEV;
523 }
524
525 static int pci_siig_setup(struct serial_private *priv,
526                           const struct pciserial_board *board,
527                           struct uart_port *port, int idx)
528 {
529         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
530
531         if (idx > 3) {
532                 bar = 4;
533                 offset = (idx - 4) * 8;
534         }
535
536         return setup_port(priv, port, bar, offset, 0);
537 }
538
539 /*
540  * Timedia has an explosion of boards, and to avoid the PCI table from
541  * growing *huge*, we use this function to collapse some 70 entries
542  * in the PCI table into one, for sanity's and compactness's sake.
543  */
544 static const unsigned short timedia_single_port[] = {
545         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
546 };
547
548 static const unsigned short timedia_dual_port[] = {
549         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
550         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
551         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
552         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
553         0xD079, 0
554 };
555
556 static const unsigned short timedia_quad_port[] = {
557         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
558         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
559         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
560         0xB157, 0
561 };
562
563 static const unsigned short timedia_eight_port[] = {
564         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
565         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
566 };
567
568 static const struct timedia_struct {
569         int num;
570         const unsigned short *ids;
571 } timedia_data[] = {
572         { 1, timedia_single_port },
573         { 2, timedia_dual_port },
574         { 4, timedia_quad_port },
575         { 8, timedia_eight_port }
576 };
577
578 /*
579  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
580  * listing them individually, this driver merely grabs them all with
581  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
582  * and should be left free to be claimed by parport_serial instead.
583  */
584 static int pci_timedia_probe(struct pci_dev *dev)
585 {
586         /*
587          * Check the third digit of the subdevice ID
588          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
589          */
590         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
591                 dev_info(&dev->dev,
592                         "ignoring Timedia subdevice %04x for parport_serial\n",
593                         dev->subsystem_device);
594                 return -ENODEV;
595         }
596
597         return 0;
598 }
599
600 static int pci_timedia_init(struct pci_dev *dev)
601 {
602         const unsigned short *ids;
603         int i, j;
604
605         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
606                 ids = timedia_data[i].ids;
607                 for (j = 0; ids[j]; j++)
608                         if (dev->subsystem_device == ids[j])
609                                 return timedia_data[i].num;
610         }
611         return 0;
612 }
613
614 /*
615  * Timedia/SUNIX uses a mixture of BARs and offsets
616  * Ugh, this is ugly as all hell --- TYT
617  */
618 static int
619 pci_timedia_setup(struct serial_private *priv,
620                   const struct pciserial_board *board,
621                   struct uart_port *port, int idx)
622 {
623         unsigned int bar = 0, offset = board->first_offset;
624
625         switch (idx) {
626         case 0:
627                 bar = 0;
628                 break;
629         case 1:
630                 offset = board->uart_offset;
631                 bar = 0;
632                 break;
633         case 2:
634                 bar = 1;
635                 break;
636         case 3:
637                 offset = board->uart_offset;
638                 /* FALLTHROUGH */
639         case 4: /* BAR 2 */
640         case 5: /* BAR 3 */
641         case 6: /* BAR 4 */
642         case 7: /* BAR 5 */
643                 bar = idx - 2;
644         }
645
646         return setup_port(priv, port, bar, offset, board->reg_shift);
647 }
648
649 /*
650  * Some Titan cards are also a little weird
651  */
652 static int
653 titan_400l_800l_setup(struct serial_private *priv,
654                       const struct pciserial_board *board,
655                       struct uart_port *port, int idx)
656 {
657         unsigned int bar, offset = board->first_offset;
658
659         switch (idx) {
660         case 0:
661                 bar = 1;
662                 break;
663         case 1:
664                 bar = 2;
665                 break;
666         default:
667                 bar = 4;
668                 offset = (idx - 2) * board->uart_offset;
669         }
670
671         return setup_port(priv, port, bar, offset, board->reg_shift);
672 }
673
674 static int pci_xircom_init(struct pci_dev *dev)
675 {
676         msleep(100);
677         return 0;
678 }
679
680 static int pci_ni8420_init(struct pci_dev *dev)
681 {
682         void __iomem *p;
683         unsigned long base, len;
684         unsigned int bar = 0;
685
686         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
687                 moan_device("no memory in bar", dev);
688                 return 0;
689         }
690
691         base = pci_resource_start(dev, bar);
692         len =  pci_resource_len(dev, bar);
693         p = ioremap_nocache(base, len);
694         if (p == NULL)
695                 return -ENOMEM;
696
697         /* Enable CPU Interrupt */
698         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
699                p + NI8420_INT_ENABLE_REG);
700
701         iounmap(p);
702         return 0;
703 }
704
705 #define MITE_IOWBSR1_WSIZE      0xa
706 #define MITE_IOWBSR1_WIN_OFFSET 0x800
707 #define MITE_IOWBSR1_WENAB      (1 << 7)
708 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
709 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
710 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
711
712 static int pci_ni8430_init(struct pci_dev *dev)
713 {
714         void __iomem *p;
715         unsigned long base, len;
716         u32 device_window;
717         unsigned int bar = 0;
718
719         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
720                 moan_device("no memory in bar", dev);
721                 return 0;
722         }
723
724         base = pci_resource_start(dev, bar);
725         len =  pci_resource_len(dev, bar);
726         p = ioremap_nocache(base, len);
727         if (p == NULL)
728                 return -ENOMEM;
729
730         /* Set device window address and size in BAR0 */
731         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
732                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
733         writel(device_window, p + MITE_IOWBSR1);
734
735         /* Set window access to go to RAMSEL IO address space */
736         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
737                p + MITE_IOWCR1);
738
739         /* Enable IO Bus Interrupt 0 */
740         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
741
742         /* Enable CPU Interrupt */
743         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
744
745         iounmap(p);
746         return 0;
747 }
748
749 /* UART Port Control Register */
750 #define NI8430_PORTCON  0x0f
751 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
752
753 static int
754 pci_ni8430_setup(struct serial_private *priv,
755                  const struct pciserial_board *board,
756                  struct uart_port *port, int idx)
757 {
758         void __iomem *p;
759         unsigned long base, len;
760         unsigned int bar, offset = board->first_offset;
761
762         if (idx >= board->num_ports)
763                 return 1;
764
765         bar = FL_GET_BASE(board->flags);
766         offset += idx * board->uart_offset;
767
768         base = pci_resource_start(priv->dev, bar);
769         len =  pci_resource_len(priv->dev, bar);
770         p = ioremap_nocache(base, len);
771
772         /* enable the transceiver */
773         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
774                p + offset + NI8430_PORTCON);
775
776         iounmap(p);
777
778         return setup_port(priv, port, bar, offset, board->reg_shift);
779 }
780
781 static int pci_netmos_9900_setup(struct serial_private *priv,
782                                 const struct pciserial_board *board,
783                                 struct uart_port *port, int idx)
784 {
785         unsigned int bar;
786
787         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
788                 /* netmos apparently orders BARs by datasheet layout, so serial
789                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
790                  */
791                 bar = 3 * idx;
792
793                 return setup_port(priv, port, bar, 0, board->reg_shift);
794         } else {
795                 return pci_default_setup(priv, board, port, idx);
796         }
797 }
798
799 /* the 99xx series comes with a range of device IDs and a variety
800  * of capabilities:
801  *
802  * 9900 has varying capabilities and can cascade to sub-controllers
803  *   (cascading should be purely internal)
804  * 9904 is hardwired with 4 serial ports
805  * 9912 and 9922 are hardwired with 2 serial ports
806  */
807 static int pci_netmos_9900_numports(struct pci_dev *dev)
808 {
809         unsigned int c = dev->class;
810         unsigned int pi;
811         unsigned short sub_serports;
812
813         pi = (c & 0xff);
814
815         if (pi == 2) {
816                 return 1;
817         } else if ((pi == 0) &&
818                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
819                 /* two possibilities: 0x30ps encodes number of parallel and
820                  * serial ports, or 0x1000 indicates *something*. This is not
821                  * immediately obvious, since the 2s1p+4s configuration seems
822                  * to offer all functionality on functions 0..2, while still
823                  * advertising the same function 3 as the 4s+2s1p config.
824                  */
825                 sub_serports = dev->subsystem_device & 0xf;
826                 if (sub_serports > 0) {
827                         return sub_serports;
828                 } else {
829                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
830                         return 0;
831                 }
832         }
833
834         moan_device("unknown NetMos/Mostech program interface", dev);
835         return 0;
836 }
837
838 static int pci_netmos_init(struct pci_dev *dev)
839 {
840         /* subdevice 0x00PS means <P> parallel, <S> serial */
841         unsigned int num_serial = dev->subsystem_device & 0xf;
842
843         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
844                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
845                 return 0;
846
847         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
848                         dev->subsystem_device == 0x0299)
849                 return 0;
850
851         switch (dev->device) { /* FALLTHROUGH on all */
852                 case PCI_DEVICE_ID_NETMOS_9904:
853                 case PCI_DEVICE_ID_NETMOS_9912:
854                 case PCI_DEVICE_ID_NETMOS_9922:
855                 case PCI_DEVICE_ID_NETMOS_9900:
856                         num_serial = pci_netmos_9900_numports(dev);
857                         break;
858
859                 default:
860                         if (num_serial == 0 ) {
861                                 moan_device("unknown NetMos/Mostech device", dev);
862                         }
863         }
864
865         if (num_serial == 0)
866                 return -ENODEV;
867
868         return num_serial;
869 }
870
871 /*
872  * These chips are available with optionally one parallel port and up to
873  * two serial ports. Unfortunately they all have the same product id.
874  *
875  * Basic configuration is done over a region of 32 I/O ports. The base
876  * ioport is called INTA or INTC, depending on docs/other drivers.
877  *
878  * The region of the 32 I/O ports is configured in POSIO0R...
879  */
880
881 /* registers */
882 #define ITE_887x_MISCR          0x9c
883 #define ITE_887x_INTCBAR        0x78
884 #define ITE_887x_UARTBAR        0x7c
885 #define ITE_887x_PS0BAR         0x10
886 #define ITE_887x_POSIO0         0x60
887
888 /* I/O space size */
889 #define ITE_887x_IOSIZE         32
890 /* I/O space size (bits 26-24; 8 bytes = 011b) */
891 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
892 /* I/O space size (bits 26-24; 32 bytes = 101b) */
893 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
894 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
895 #define ITE_887x_POSIO_SPEED            (3 << 29)
896 /* enable IO_Space bit */
897 #define ITE_887x_POSIO_ENABLE           (1 << 31)
898
899 static int pci_ite887x_init(struct pci_dev *dev)
900 {
901         /* inta_addr are the configuration addresses of the ITE */
902         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
903                                                         0x200, 0x280, 0 };
904         int ret, i, type;
905         struct resource *iobase = NULL;
906         u32 miscr, uartbar, ioport;
907
908         /* search for the base-ioport */
909         i = 0;
910         while (inta_addr[i] && iobase == NULL) {
911                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
912                                                                 "ite887x");
913                 if (iobase != NULL) {
914                         /* write POSIO0R - speed | size | ioport */
915                         pci_write_config_dword(dev, ITE_887x_POSIO0,
916                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
917                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
918                         /* write INTCBAR - ioport */
919                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
920                                                                 inta_addr[i]);
921                         ret = inb(inta_addr[i]);
922                         if (ret != 0xff) {
923                                 /* ioport connected */
924                                 break;
925                         }
926                         release_region(iobase->start, ITE_887x_IOSIZE);
927                         iobase = NULL;
928                 }
929                 i++;
930         }
931
932         if (!inta_addr[i]) {
933                 printk(KERN_ERR "ite887x: could not find iobase\n");
934                 return -ENODEV;
935         }
936
937         /* start of undocumented type checking (see parport_pc.c) */
938         type = inb(iobase->start + 0x18) & 0x0f;
939
940         switch (type) {
941         case 0x2:       /* ITE8871 (1P) */
942         case 0xa:       /* ITE8875 (1P) */
943                 ret = 0;
944                 break;
945         case 0xe:       /* ITE8872 (2S1P) */
946                 ret = 2;
947                 break;
948         case 0x6:       /* ITE8873 (1S) */
949                 ret = 1;
950                 break;
951         case 0x8:       /* ITE8874 (2S) */
952                 ret = 2;
953                 break;
954         default:
955                 moan_device("Unknown ITE887x", dev);
956                 ret = -ENODEV;
957         }
958
959         /* configure all serial ports */
960         for (i = 0; i < ret; i++) {
961                 /* read the I/O port from the device */
962                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
963                                                                 &ioport);
964                 ioport &= 0x0000FF00;   /* the actual base address */
965                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
966                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
967                         ITE_887x_POSIO_IOSIZE_8 | ioport);
968
969                 /* write the ioport to the UARTBAR */
970                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
971                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
972                 uartbar |= (ioport << (16 * i));        /* set the ioport */
973                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
974
975                 /* get current config */
976                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
977                 /* disable interrupts (UARTx_Routing[3:0]) */
978                 miscr &= ~(0xf << (12 - 4 * i));
979                 /* activate the UART (UARTx_En) */
980                 miscr |= 1 << (23 - i);
981                 /* write new config with activated UART */
982                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
983         }
984
985         if (ret <= 0) {
986                 /* the device has no UARTs if we get here */
987                 release_region(iobase->start, ITE_887x_IOSIZE);
988         }
989
990         return ret;
991 }
992
993 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
994 {
995         u32 ioport;
996         /* the ioport is bit 0-15 in POSIO0R */
997         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
998         ioport &= 0xffff;
999         release_region(ioport, ITE_887x_IOSIZE);
1000 }
1001
1002 /*
1003  * Oxford Semiconductor Inc.
1004  * Check that device is part of the Tornado range of devices, then determine
1005  * the number of ports available on the device.
1006  */
1007 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1008 {
1009         u8 __iomem *p;
1010         unsigned long deviceID;
1011         unsigned int  number_uarts = 0;
1012
1013         /* OxSemi Tornado devices are all 0xCxxx */
1014         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1015             (dev->device & 0xF000) != 0xC000)
1016                 return 0;
1017
1018         p = pci_iomap(dev, 0, 5);
1019         if (p == NULL)
1020                 return -ENOMEM;
1021
1022         deviceID = ioread32(p);
1023         /* Tornado device */
1024         if (deviceID == 0x07000200) {
1025                 number_uarts = ioread8(p + 4);
1026                 printk(KERN_DEBUG
1027                         "%d ports detected on Oxford PCI Express device\n",
1028                                                                 number_uarts);
1029         }
1030         pci_iounmap(dev, p);
1031         return number_uarts;
1032 }
1033
1034 static int
1035 pci_default_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_port *port, int idx)
1038 {
1039         unsigned int bar, offset = board->first_offset, maxnr;
1040
1041         bar = FL_GET_BASE(board->flags);
1042         if (board->flags & FL_BASE_BARS)
1043                 bar += idx;
1044         else
1045                 offset += idx * board->uart_offset;
1046
1047         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1048                 (board->reg_shift + 3);
1049
1050         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1051                 return 1;
1052
1053         return setup_port(priv, port, bar, offset, board->reg_shift);
1054 }
1055
1056 static int
1057 ce4100_serial_setup(struct serial_private *priv,
1058                   const struct pciserial_board *board,
1059                   struct uart_port *port, int idx)
1060 {
1061         int ret;
1062
1063         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1064         port->iotype = UPIO_MEM32;
1065         port->type = PORT_XSCALE;
1066         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1067         port->regshift = 2;
1068
1069         return ret;
1070 }
1071
1072 static int
1073 pci_omegapci_setup(struct serial_private *priv,
1074                       const struct pciserial_board *board,
1075                       struct uart_port *port, int idx)
1076 {
1077         return setup_port(priv, port, 2, idx * 8, 0);
1078 }
1079
1080 static int
1081 pci_brcm_trumanage_setup(struct serial_private *priv,
1082                          const struct pciserial_board *board,
1083                          struct uart_port *port, int idx)
1084 {
1085         int ret = pci_default_setup(priv, board, port, idx);
1086
1087         port->type = PORT_BRCM_TRUMANAGE;
1088         port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1089         return ret;
1090 }
1091
1092 static int skip_tx_en_setup(struct serial_private *priv,
1093                         const struct pciserial_board *board,
1094                         struct uart_port *port, int idx)
1095 {
1096         port->flags |= UPF_NO_TXEN_TEST;
1097         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1098                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1099                           priv->dev->vendor,
1100                           priv->dev->device,
1101                           priv->dev->subsystem_vendor,
1102                           priv->dev->subsystem_device);
1103
1104         return pci_default_setup(priv, board, port, idx);
1105 }
1106
1107 static int pci_eg20t_init(struct pci_dev *dev)
1108 {
1109 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1110         return -ENODEV;
1111 #else
1112         return 0;
1113 #endif
1114 }
1115
1116 static int
1117 pci_xr17c154_setup(struct serial_private *priv,
1118                   const struct pciserial_board *board,
1119                   struct uart_port *port, int idx)
1120 {
1121         port->flags |= UPF_EXAR_EFR;
1122         return pci_default_setup(priv, board, port, idx);
1123 }
1124
1125 /* This should be in linux/pci_ids.h */
1126 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1127 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1128 #define PCI_DEVICE_ID_OCTPRO            0x0001
1129 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1130 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1131 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1132 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1133 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1134 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1135 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1136 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1137 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1138 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1139 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1140 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1141 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1142 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1143 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1144 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1145 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1146 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1147 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1148 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1149 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1150 #define PCI_DEVICE_ID_TITAN_200V3       0xA306
1151 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1152 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1153 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1154 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1155 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1156 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1157 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1158 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1159
1160 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1161 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1162 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1163
1164 /*
1165  * Master list of serial port init/setup/exit quirks.
1166  * This does not describe the general nature of the port.
1167  * (ie, baud base, number and location of ports, etc)
1168  *
1169  * This list is ordered alphabetically by vendor then device.
1170  * Specific entries must come before more generic entries.
1171  */
1172 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1173         /*
1174         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1175         */
1176         {
1177                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1178                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1179                 .subvendor      = PCI_ANY_ID,
1180                 .subdevice      = PCI_ANY_ID,
1181                 .setup          = addidata_apci7800_setup,
1182         },
1183         /*
1184          * AFAVLAB cards - these may be called via parport_serial
1185          *  It is not clear whether this applies to all products.
1186          */
1187         {
1188                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1189                 .device         = PCI_ANY_ID,
1190                 .subvendor      = PCI_ANY_ID,
1191                 .subdevice      = PCI_ANY_ID,
1192                 .setup          = afavlab_setup,
1193         },
1194         /*
1195          * HP Diva
1196          */
1197         {
1198                 .vendor         = PCI_VENDOR_ID_HP,
1199                 .device         = PCI_DEVICE_ID_HP_DIVA,
1200                 .subvendor      = PCI_ANY_ID,
1201                 .subdevice      = PCI_ANY_ID,
1202                 .init           = pci_hp_diva_init,
1203                 .setup          = pci_hp_diva_setup,
1204         },
1205         /*
1206          * Intel
1207          */
1208         {
1209                 .vendor         = PCI_VENDOR_ID_INTEL,
1210                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1211                 .subvendor      = 0xe4bf,
1212                 .subdevice      = PCI_ANY_ID,
1213                 .init           = pci_inteli960ni_init,
1214                 .setup          = pci_default_setup,
1215         },
1216         {
1217                 .vendor         = PCI_VENDOR_ID_INTEL,
1218                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1219                 .subvendor      = PCI_ANY_ID,
1220                 .subdevice      = PCI_ANY_ID,
1221                 .setup          = skip_tx_en_setup,
1222         },
1223         {
1224                 .vendor         = PCI_VENDOR_ID_INTEL,
1225                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1226                 .subvendor      = PCI_ANY_ID,
1227                 .subdevice      = PCI_ANY_ID,
1228                 .setup          = skip_tx_en_setup,
1229         },
1230         {
1231                 .vendor         = PCI_VENDOR_ID_INTEL,
1232                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1233                 .subvendor      = PCI_ANY_ID,
1234                 .subdevice      = PCI_ANY_ID,
1235                 .setup          = skip_tx_en_setup,
1236         },
1237         {
1238                 .vendor         = PCI_VENDOR_ID_INTEL,
1239                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1240                 .subvendor      = PCI_ANY_ID,
1241                 .subdevice      = PCI_ANY_ID,
1242                 .setup          = ce4100_serial_setup,
1243         },
1244         /*
1245          * ITE
1246          */
1247         {
1248                 .vendor         = PCI_VENDOR_ID_ITE,
1249                 .device         = PCI_DEVICE_ID_ITE_8872,
1250                 .subvendor      = PCI_ANY_ID,
1251                 .subdevice      = PCI_ANY_ID,
1252                 .init           = pci_ite887x_init,
1253                 .setup          = pci_default_setup,
1254                 .exit           = __devexit_p(pci_ite887x_exit),
1255         },
1256         /*
1257          * National Instruments
1258          */
1259         {
1260                 .vendor         = PCI_VENDOR_ID_NI,
1261                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1262                 .subvendor      = PCI_ANY_ID,
1263                 .subdevice      = PCI_ANY_ID,
1264                 .init           = pci_ni8420_init,
1265                 .setup          = pci_default_setup,
1266                 .exit           = __devexit_p(pci_ni8420_exit),
1267         },
1268         {
1269                 .vendor         = PCI_VENDOR_ID_NI,
1270                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1271                 .subvendor      = PCI_ANY_ID,
1272                 .subdevice      = PCI_ANY_ID,
1273                 .init           = pci_ni8420_init,
1274                 .setup          = pci_default_setup,
1275                 .exit           = __devexit_p(pci_ni8420_exit),
1276         },
1277         {
1278                 .vendor         = PCI_VENDOR_ID_NI,
1279                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1280                 .subvendor      = PCI_ANY_ID,
1281                 .subdevice      = PCI_ANY_ID,
1282                 .init           = pci_ni8420_init,
1283                 .setup          = pci_default_setup,
1284                 .exit           = __devexit_p(pci_ni8420_exit),
1285         },
1286         {
1287                 .vendor         = PCI_VENDOR_ID_NI,
1288                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1289                 .subvendor      = PCI_ANY_ID,
1290                 .subdevice      = PCI_ANY_ID,
1291                 .init           = pci_ni8420_init,
1292                 .setup          = pci_default_setup,
1293                 .exit           = __devexit_p(pci_ni8420_exit),
1294         },
1295         {
1296                 .vendor         = PCI_VENDOR_ID_NI,
1297                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1298                 .subvendor      = PCI_ANY_ID,
1299                 .subdevice      = PCI_ANY_ID,
1300                 .init           = pci_ni8420_init,
1301                 .setup          = pci_default_setup,
1302                 .exit           = __devexit_p(pci_ni8420_exit),
1303         },
1304         {
1305                 .vendor         = PCI_VENDOR_ID_NI,
1306                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1307                 .subvendor      = PCI_ANY_ID,
1308                 .subdevice      = PCI_ANY_ID,
1309                 .init           = pci_ni8420_init,
1310                 .setup          = pci_default_setup,
1311                 .exit           = __devexit_p(pci_ni8420_exit),
1312         },
1313         {
1314                 .vendor         = PCI_VENDOR_ID_NI,
1315                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1316                 .subvendor      = PCI_ANY_ID,
1317                 .subdevice      = PCI_ANY_ID,
1318                 .init           = pci_ni8420_init,
1319                 .setup          = pci_default_setup,
1320                 .exit           = __devexit_p(pci_ni8420_exit),
1321         },
1322         {
1323                 .vendor         = PCI_VENDOR_ID_NI,
1324                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1325                 .subvendor      = PCI_ANY_ID,
1326                 .subdevice      = PCI_ANY_ID,
1327                 .init           = pci_ni8420_init,
1328                 .setup          = pci_default_setup,
1329                 .exit           = __devexit_p(pci_ni8420_exit),
1330         },
1331         {
1332                 .vendor         = PCI_VENDOR_ID_NI,
1333                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1334                 .subvendor      = PCI_ANY_ID,
1335                 .subdevice      = PCI_ANY_ID,
1336                 .init           = pci_ni8420_init,
1337                 .setup          = pci_default_setup,
1338                 .exit           = __devexit_p(pci_ni8420_exit),
1339         },
1340         {
1341                 .vendor         = PCI_VENDOR_ID_NI,
1342                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1343                 .subvendor      = PCI_ANY_ID,
1344                 .subdevice      = PCI_ANY_ID,
1345                 .init           = pci_ni8420_init,
1346                 .setup          = pci_default_setup,
1347                 .exit           = __devexit_p(pci_ni8420_exit),
1348         },
1349         {
1350                 .vendor         = PCI_VENDOR_ID_NI,
1351                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1352                 .subvendor      = PCI_ANY_ID,
1353                 .subdevice      = PCI_ANY_ID,
1354                 .init           = pci_ni8420_init,
1355                 .setup          = pci_default_setup,
1356                 .exit           = __devexit_p(pci_ni8420_exit),
1357         },
1358         {
1359                 .vendor         = PCI_VENDOR_ID_NI,
1360                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1361                 .subvendor      = PCI_ANY_ID,
1362                 .subdevice      = PCI_ANY_ID,
1363                 .init           = pci_ni8420_init,
1364                 .setup          = pci_default_setup,
1365                 .exit           = __devexit_p(pci_ni8420_exit),
1366         },
1367         {
1368                 .vendor         = PCI_VENDOR_ID_NI,
1369                 .device         = PCI_ANY_ID,
1370                 .subvendor      = PCI_ANY_ID,
1371                 .subdevice      = PCI_ANY_ID,
1372                 .init           = pci_ni8430_init,
1373                 .setup          = pci_ni8430_setup,
1374                 .exit           = __devexit_p(pci_ni8430_exit),
1375         },
1376         /*
1377          * Panacom
1378          */
1379         {
1380                 .vendor         = PCI_VENDOR_ID_PANACOM,
1381                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1382                 .subvendor      = PCI_ANY_ID,
1383                 .subdevice      = PCI_ANY_ID,
1384                 .init           = pci_plx9050_init,
1385                 .setup          = pci_default_setup,
1386                 .exit           = __devexit_p(pci_plx9050_exit),
1387         },
1388         {
1389                 .vendor         = PCI_VENDOR_ID_PANACOM,
1390                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1391                 .subvendor      = PCI_ANY_ID,
1392                 .subdevice      = PCI_ANY_ID,
1393                 .init           = pci_plx9050_init,
1394                 .setup          = pci_default_setup,
1395                 .exit           = __devexit_p(pci_plx9050_exit),
1396         },
1397         /*
1398          * PLX
1399          */
1400         {
1401                 .vendor         = PCI_VENDOR_ID_PLX,
1402                 .device         = PCI_DEVICE_ID_PLX_9030,
1403                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1404                 .subdevice      = PCI_ANY_ID,
1405                 .setup          = pci_default_setup,
1406         },
1407         {
1408                 .vendor         = PCI_VENDOR_ID_PLX,
1409                 .device         = PCI_DEVICE_ID_PLX_9050,
1410                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1411                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1412                 .init           = pci_plx9050_init,
1413                 .setup          = pci_default_setup,
1414                 .exit           = __devexit_p(pci_plx9050_exit),
1415         },
1416         {
1417                 .vendor         = PCI_VENDOR_ID_PLX,
1418                 .device         = PCI_DEVICE_ID_PLX_9050,
1419                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1420                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1421                 .init           = pci_plx9050_init,
1422                 .setup          = pci_default_setup,
1423                 .exit           = __devexit_p(pci_plx9050_exit),
1424         },
1425         {
1426                 .vendor         = PCI_VENDOR_ID_PLX,
1427                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1428                 .subvendor      = PCI_VENDOR_ID_PLX,
1429                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1430                 .init           = pci_plx9050_init,
1431                 .setup          = pci_default_setup,
1432                 .exit           = __devexit_p(pci_plx9050_exit),
1433         },
1434         /*
1435          * SBS Technologies, Inc., PMC-OCTALPRO 232
1436          */
1437         {
1438                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1439                 .device         = PCI_DEVICE_ID_OCTPRO,
1440                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1441                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1442                 .init           = sbs_init,
1443                 .setup          = sbs_setup,
1444                 .exit           = __devexit_p(sbs_exit),
1445         },
1446         /*
1447          * SBS Technologies, Inc., PMC-OCTALPRO 422
1448          */
1449         {
1450                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1451                 .device         = PCI_DEVICE_ID_OCTPRO,
1452                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1453                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1454                 .init           = sbs_init,
1455                 .setup          = sbs_setup,
1456                 .exit           = __devexit_p(sbs_exit),
1457         },
1458         /*
1459          * SBS Technologies, Inc., P-Octal 232
1460          */
1461         {
1462                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1463                 .device         = PCI_DEVICE_ID_OCTPRO,
1464                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1465                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1466                 .init           = sbs_init,
1467                 .setup          = sbs_setup,
1468                 .exit           = __devexit_p(sbs_exit),
1469         },
1470         /*
1471          * SBS Technologies, Inc., P-Octal 422
1472          */
1473         {
1474                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1475                 .device         = PCI_DEVICE_ID_OCTPRO,
1476                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1477                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1478                 .init           = sbs_init,
1479                 .setup          = sbs_setup,
1480                 .exit           = __devexit_p(sbs_exit),
1481         },
1482         /*
1483          * SIIG cards - these may be called via parport_serial
1484          */
1485         {
1486                 .vendor         = PCI_VENDOR_ID_SIIG,
1487                 .device         = PCI_ANY_ID,
1488                 .subvendor      = PCI_ANY_ID,
1489                 .subdevice      = PCI_ANY_ID,
1490                 .init           = pci_siig_init,
1491                 .setup          = pci_siig_setup,
1492         },
1493         /*
1494          * Titan cards
1495          */
1496         {
1497                 .vendor         = PCI_VENDOR_ID_TITAN,
1498                 .device         = PCI_DEVICE_ID_TITAN_400L,
1499                 .subvendor      = PCI_ANY_ID,
1500                 .subdevice      = PCI_ANY_ID,
1501                 .setup          = titan_400l_800l_setup,
1502         },
1503         {
1504                 .vendor         = PCI_VENDOR_ID_TITAN,
1505                 .device         = PCI_DEVICE_ID_TITAN_800L,
1506                 .subvendor      = PCI_ANY_ID,
1507                 .subdevice      = PCI_ANY_ID,
1508                 .setup          = titan_400l_800l_setup,
1509         },
1510         /*
1511          * Timedia cards
1512          */
1513         {
1514                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1515                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1516                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1517                 .subdevice      = PCI_ANY_ID,
1518                 .probe          = pci_timedia_probe,
1519                 .init           = pci_timedia_init,
1520                 .setup          = pci_timedia_setup,
1521         },
1522         {
1523                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1524                 .device         = PCI_ANY_ID,
1525                 .subvendor      = PCI_ANY_ID,
1526                 .subdevice      = PCI_ANY_ID,
1527                 .setup          = pci_timedia_setup,
1528         },
1529         /*
1530          * Exar cards
1531          */
1532         {
1533                 .vendor = PCI_VENDOR_ID_EXAR,
1534                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1535                 .subvendor      = PCI_ANY_ID,
1536                 .subdevice      = PCI_ANY_ID,
1537                 .setup          = pci_xr17c154_setup,
1538         },
1539         {
1540                 .vendor = PCI_VENDOR_ID_EXAR,
1541                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1542                 .subvendor      = PCI_ANY_ID,
1543                 .subdevice      = PCI_ANY_ID,
1544                 .setup          = pci_xr17c154_setup,
1545         },
1546         {
1547                 .vendor = PCI_VENDOR_ID_EXAR,
1548                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1549                 .subvendor      = PCI_ANY_ID,
1550                 .subdevice      = PCI_ANY_ID,
1551                 .setup          = pci_xr17c154_setup,
1552         },
1553         /*
1554          * Xircom cards
1555          */
1556         {
1557                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1558                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1559                 .subvendor      = PCI_ANY_ID,
1560                 .subdevice      = PCI_ANY_ID,
1561                 .init           = pci_xircom_init,
1562                 .setup          = pci_default_setup,
1563         },
1564         /*
1565          * Netmos cards - these may be called via parport_serial
1566          */
1567         {
1568                 .vendor         = PCI_VENDOR_ID_NETMOS,
1569                 .device         = PCI_ANY_ID,
1570                 .subvendor      = PCI_ANY_ID,
1571                 .subdevice      = PCI_ANY_ID,
1572                 .init           = pci_netmos_init,
1573                 .setup          = pci_netmos_9900_setup,
1574         },
1575         /*
1576          * For Oxford Semiconductor Tornado based devices
1577          */
1578         {
1579                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1580                 .device         = PCI_ANY_ID,
1581                 .subvendor      = PCI_ANY_ID,
1582                 .subdevice      = PCI_ANY_ID,
1583                 .init           = pci_oxsemi_tornado_init,
1584                 .setup          = pci_default_setup,
1585         },
1586         {
1587                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1588                 .device         = PCI_ANY_ID,
1589                 .subvendor      = PCI_ANY_ID,
1590                 .subdevice      = PCI_ANY_ID,
1591                 .init           = pci_oxsemi_tornado_init,
1592                 .setup          = pci_default_setup,
1593         },
1594         {
1595                 .vendor         = PCI_VENDOR_ID_DIGI,
1596                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1597                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1598                 .subdevice              = PCI_ANY_ID,
1599                 .init                   = pci_oxsemi_tornado_init,
1600                 .setup          = pci_default_setup,
1601         },
1602         {
1603                 .vendor         = PCI_VENDOR_ID_INTEL,
1604                 .device         = 0x8811,
1605                 .subvendor      = PCI_ANY_ID,
1606                 .subdevice      = PCI_ANY_ID,
1607                 .init           = pci_eg20t_init,
1608                 .setup          = pci_default_setup,
1609         },
1610         {
1611                 .vendor         = PCI_VENDOR_ID_INTEL,
1612                 .device         = 0x8812,
1613                 .subvendor      = PCI_ANY_ID,
1614                 .subdevice      = PCI_ANY_ID,
1615                 .init           = pci_eg20t_init,
1616                 .setup          = pci_default_setup,
1617         },
1618         {
1619                 .vendor         = PCI_VENDOR_ID_INTEL,
1620                 .device         = 0x8813,
1621                 .subvendor      = PCI_ANY_ID,
1622                 .subdevice      = PCI_ANY_ID,
1623                 .init           = pci_eg20t_init,
1624                 .setup          = pci_default_setup,
1625         },
1626         {
1627                 .vendor         = PCI_VENDOR_ID_INTEL,
1628                 .device         = 0x8814,
1629                 .subvendor      = PCI_ANY_ID,
1630                 .subdevice      = PCI_ANY_ID,
1631                 .init           = pci_eg20t_init,
1632                 .setup          = pci_default_setup,
1633         },
1634         {
1635                 .vendor         = 0x10DB,
1636                 .device         = 0x8027,
1637                 .subvendor      = PCI_ANY_ID,
1638                 .subdevice      = PCI_ANY_ID,
1639                 .init           = pci_eg20t_init,
1640                 .setup          = pci_default_setup,
1641         },
1642         {
1643                 .vendor         = 0x10DB,
1644                 .device         = 0x8028,
1645                 .subvendor      = PCI_ANY_ID,
1646                 .subdevice      = PCI_ANY_ID,
1647                 .init           = pci_eg20t_init,
1648                 .setup          = pci_default_setup,
1649         },
1650         {
1651                 .vendor         = 0x10DB,
1652                 .device         = 0x8029,
1653                 .subvendor      = PCI_ANY_ID,
1654                 .subdevice      = PCI_ANY_ID,
1655                 .init           = pci_eg20t_init,
1656                 .setup          = pci_default_setup,
1657         },
1658         {
1659                 .vendor         = 0x10DB,
1660                 .device         = 0x800C,
1661                 .subvendor      = PCI_ANY_ID,
1662                 .subdevice      = PCI_ANY_ID,
1663                 .init           = pci_eg20t_init,
1664                 .setup          = pci_default_setup,
1665         },
1666         {
1667                 .vendor         = 0x10DB,
1668                 .device         = 0x800D,
1669                 .subvendor      = PCI_ANY_ID,
1670                 .subdevice      = PCI_ANY_ID,
1671                 .init           = pci_eg20t_init,
1672                 .setup          = pci_default_setup,
1673         },
1674         /*
1675          * Cronyx Omega PCI (PLX-chip based)
1676          */
1677         {
1678                 .vendor         = PCI_VENDOR_ID_PLX,
1679                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1680                 .subvendor      = PCI_ANY_ID,
1681                 .subdevice      = PCI_ANY_ID,
1682                 .setup          = pci_omegapci_setup,
1683          },
1684         /*
1685          * Broadcom TruManage (NetXtreme)
1686          */
1687         {
1688                 .vendor         = PCI_VENDOR_ID_BROADCOM,
1689                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
1690                 .subvendor      = PCI_ANY_ID,
1691                 .subdevice      = PCI_ANY_ID,
1692                 .setup          = pci_brcm_trumanage_setup,
1693         },
1694
1695         /*
1696          * Default "match everything" terminator entry
1697          */
1698         {
1699                 .vendor         = PCI_ANY_ID,
1700                 .device         = PCI_ANY_ID,
1701                 .subvendor      = PCI_ANY_ID,
1702                 .subdevice      = PCI_ANY_ID,
1703                 .setup          = pci_default_setup,
1704         }
1705 };
1706
1707 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1708 {
1709         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1710 }
1711
1712 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1713 {
1714         struct pci_serial_quirk *quirk;
1715
1716         for (quirk = pci_serial_quirks; ; quirk++)
1717                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1718                     quirk_id_matches(quirk->device, dev->device) &&
1719                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1720                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1721                         break;
1722         return quirk;
1723 }
1724
1725 static inline int get_pci_irq(struct pci_dev *dev,
1726                                 const struct pciserial_board *board)
1727 {
1728         if (board->flags & FL_NOIRQ)
1729                 return 0;
1730         else
1731                 return dev->irq;
1732 }
1733
1734 /*
1735  * This is the configuration table for all of the PCI serial boards
1736  * which we support.  It is directly indexed by the pci_board_num_t enum
1737  * value, which is encoded in the pci_device_id PCI probe table's
1738  * driver_data member.
1739  *
1740  * The makeup of these names are:
1741  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1742  *
1743  *  bn          = PCI BAR number
1744  *  bt          = Index using PCI BARs
1745  *  n           = number of serial ports
1746  *  baud        = baud rate
1747  *  offsetinhex = offset for each sequential port (in hex)
1748  *
1749  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1750  *
1751  * Please note: in theory if n = 1, _bt infix should make no difference.
1752  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1753  */
1754 enum pci_board_num_t {
1755         pbn_default = 0,
1756
1757         pbn_b0_1_115200,
1758         pbn_b0_2_115200,
1759         pbn_b0_4_115200,
1760         pbn_b0_5_115200,
1761         pbn_b0_8_115200,
1762
1763         pbn_b0_1_921600,
1764         pbn_b0_2_921600,
1765         pbn_b0_4_921600,
1766
1767         pbn_b0_2_1130000,
1768
1769         pbn_b0_4_1152000,
1770
1771         pbn_b0_2_1843200,
1772         pbn_b0_4_1843200,
1773
1774         pbn_b0_2_1843200_200,
1775         pbn_b0_4_1843200_200,
1776         pbn_b0_8_1843200_200,
1777
1778         pbn_b0_1_4000000,
1779
1780         pbn_b0_bt_1_115200,
1781         pbn_b0_bt_2_115200,
1782         pbn_b0_bt_4_115200,
1783         pbn_b0_bt_8_115200,
1784
1785         pbn_b0_bt_1_460800,
1786         pbn_b0_bt_2_460800,
1787         pbn_b0_bt_4_460800,
1788
1789         pbn_b0_bt_1_921600,
1790         pbn_b0_bt_2_921600,
1791         pbn_b0_bt_4_921600,
1792         pbn_b0_bt_8_921600,
1793
1794         pbn_b1_1_115200,
1795         pbn_b1_2_115200,
1796         pbn_b1_4_115200,
1797         pbn_b1_8_115200,
1798         pbn_b1_16_115200,
1799
1800         pbn_b1_1_921600,
1801         pbn_b1_2_921600,
1802         pbn_b1_4_921600,
1803         pbn_b1_8_921600,
1804
1805         pbn_b1_2_1250000,
1806
1807         pbn_b1_bt_1_115200,
1808         pbn_b1_bt_2_115200,
1809         pbn_b1_bt_4_115200,
1810
1811         pbn_b1_bt_2_921600,
1812
1813         pbn_b1_1_1382400,
1814         pbn_b1_2_1382400,
1815         pbn_b1_4_1382400,
1816         pbn_b1_8_1382400,
1817
1818         pbn_b2_1_115200,
1819         pbn_b2_2_115200,
1820         pbn_b2_4_115200,
1821         pbn_b2_8_115200,
1822
1823         pbn_b2_1_460800,
1824         pbn_b2_4_460800,
1825         pbn_b2_8_460800,
1826         pbn_b2_16_460800,
1827
1828         pbn_b2_1_921600,
1829         pbn_b2_4_921600,
1830         pbn_b2_8_921600,
1831
1832         pbn_b2_8_1152000,
1833
1834         pbn_b2_bt_1_115200,
1835         pbn_b2_bt_2_115200,
1836         pbn_b2_bt_4_115200,
1837
1838         pbn_b2_bt_2_921600,
1839         pbn_b2_bt_4_921600,
1840
1841         pbn_b3_2_115200,
1842         pbn_b3_4_115200,
1843         pbn_b3_8_115200,
1844
1845         pbn_b4_bt_2_921600,
1846         pbn_b4_bt_4_921600,
1847         pbn_b4_bt_8_921600,
1848
1849         /*
1850          * Board-specific versions.
1851          */
1852         pbn_panacom,
1853         pbn_panacom2,
1854         pbn_panacom4,
1855         pbn_exsys_4055,
1856         pbn_plx_romulus,
1857         pbn_oxsemi,
1858         pbn_oxsemi_1_4000000,
1859         pbn_oxsemi_2_4000000,
1860         pbn_oxsemi_4_4000000,
1861         pbn_oxsemi_8_4000000,
1862         pbn_intel_i960,
1863         pbn_sgi_ioc3,
1864         pbn_computone_4,
1865         pbn_computone_6,
1866         pbn_computone_8,
1867         pbn_sbsxrsio,
1868         pbn_exar_XR17C152,
1869         pbn_exar_XR17C154,
1870         pbn_exar_XR17C158,
1871         pbn_exar_ibm_saturn,
1872         pbn_pasemi_1682M,
1873         pbn_ni8430_2,
1874         pbn_ni8430_4,
1875         pbn_ni8430_8,
1876         pbn_ni8430_16,
1877         pbn_ADDIDATA_PCIe_1_3906250,
1878         pbn_ADDIDATA_PCIe_2_3906250,
1879         pbn_ADDIDATA_PCIe_4_3906250,
1880         pbn_ADDIDATA_PCIe_8_3906250,
1881         pbn_ce4100_1_115200,
1882         pbn_omegapci,
1883         pbn_NETMOS9900_2s_115200,
1884         pbn_brcm_trumanage,
1885 };
1886
1887 /*
1888  * uart_offset - the space between channels
1889  * reg_shift   - describes how the UART registers are mapped
1890  *               to PCI memory by the card.
1891  * For example IER register on SBS, Inc. PMC-OctPro is located at
1892  * offset 0x10 from the UART base, while UART_IER is defined as 1
1893  * in include/linux/serial_reg.h,
1894  * see first lines of serial_in() and serial_out() in 8250.c
1895 */
1896
1897 static struct pciserial_board pci_boards[] __devinitdata = {
1898         [pbn_default] = {
1899                 .flags          = FL_BASE0,
1900                 .num_ports      = 1,
1901                 .base_baud      = 115200,
1902                 .uart_offset    = 8,
1903         },
1904         [pbn_b0_1_115200] = {
1905                 .flags          = FL_BASE0,
1906                 .num_ports      = 1,
1907                 .base_baud      = 115200,
1908                 .uart_offset    = 8,
1909         },
1910         [pbn_b0_2_115200] = {
1911                 .flags          = FL_BASE0,
1912                 .num_ports      = 2,
1913                 .base_baud      = 115200,
1914                 .uart_offset    = 8,
1915         },
1916         [pbn_b0_4_115200] = {
1917                 .flags          = FL_BASE0,
1918                 .num_ports      = 4,
1919                 .base_baud      = 115200,
1920                 .uart_offset    = 8,
1921         },
1922         [pbn_b0_5_115200] = {
1923                 .flags          = FL_BASE0,
1924                 .num_ports      = 5,
1925                 .base_baud      = 115200,
1926                 .uart_offset    = 8,
1927         },
1928         [pbn_b0_8_115200] = {
1929                 .flags          = FL_BASE0,
1930                 .num_ports      = 8,
1931                 .base_baud      = 115200,
1932                 .uart_offset    = 8,
1933         },
1934         [pbn_b0_1_921600] = {
1935                 .flags          = FL_BASE0,
1936                 .num_ports      = 1,
1937                 .base_baud      = 921600,
1938                 .uart_offset    = 8,
1939         },
1940         [pbn_b0_2_921600] = {
1941                 .flags          = FL_BASE0,
1942                 .num_ports      = 2,
1943                 .base_baud      = 921600,
1944                 .uart_offset    = 8,
1945         },
1946         [pbn_b0_4_921600] = {
1947                 .flags          = FL_BASE0,
1948                 .num_ports      = 4,
1949                 .base_baud      = 921600,
1950                 .uart_offset    = 8,
1951         },
1952
1953         [pbn_b0_2_1130000] = {
1954                 .flags          = FL_BASE0,
1955                 .num_ports      = 2,
1956                 .base_baud      = 1130000,
1957                 .uart_offset    = 8,
1958         },
1959
1960         [pbn_b0_4_1152000] = {
1961                 .flags          = FL_BASE0,
1962                 .num_ports      = 4,
1963                 .base_baud      = 1152000,
1964                 .uart_offset    = 8,
1965         },
1966
1967         [pbn_b0_2_1843200] = {
1968                 .flags          = FL_BASE0,
1969                 .num_ports      = 2,
1970                 .base_baud      = 1843200,
1971                 .uart_offset    = 8,
1972         },
1973         [pbn_b0_4_1843200] = {
1974                 .flags          = FL_BASE0,
1975                 .num_ports      = 4,
1976                 .base_baud      = 1843200,
1977                 .uart_offset    = 8,
1978         },
1979
1980         [pbn_b0_2_1843200_200] = {
1981                 .flags          = FL_BASE0,
1982                 .num_ports      = 2,
1983                 .base_baud      = 1843200,
1984                 .uart_offset    = 0x200,
1985         },
1986         [pbn_b0_4_1843200_200] = {
1987                 .flags          = FL_BASE0,
1988                 .num_ports      = 4,
1989                 .base_baud      = 1843200,
1990                 .uart_offset    = 0x200,
1991         },
1992         [pbn_b0_8_1843200_200] = {
1993                 .flags          = FL_BASE0,
1994                 .num_ports      = 8,
1995                 .base_baud      = 1843200,
1996                 .uart_offset    = 0x200,
1997         },
1998         [pbn_b0_1_4000000] = {
1999                 .flags          = FL_BASE0,
2000                 .num_ports      = 1,
2001                 .base_baud      = 4000000,
2002                 .uart_offset    = 8,
2003         },
2004
2005         [pbn_b0_bt_1_115200] = {
2006                 .flags          = FL_BASE0|FL_BASE_BARS,
2007                 .num_ports      = 1,
2008                 .base_baud      = 115200,
2009                 .uart_offset    = 8,
2010         },
2011         [pbn_b0_bt_2_115200] = {
2012                 .flags          = FL_BASE0|FL_BASE_BARS,
2013                 .num_ports      = 2,
2014                 .base_baud      = 115200,
2015                 .uart_offset    = 8,
2016         },
2017         [pbn_b0_bt_4_115200] = {
2018                 .flags          = FL_BASE0|FL_BASE_BARS,
2019                 .num_ports      = 4,
2020                 .base_baud      = 115200,
2021                 .uart_offset    = 8,
2022         },
2023         [pbn_b0_bt_8_115200] = {
2024                 .flags          = FL_BASE0|FL_BASE_BARS,
2025                 .num_ports      = 8,
2026                 .base_baud      = 115200,
2027                 .uart_offset    = 8,
2028         },
2029
2030         [pbn_b0_bt_1_460800] = {
2031                 .flags          = FL_BASE0|FL_BASE_BARS,
2032                 .num_ports      = 1,
2033                 .base_baud      = 460800,
2034                 .uart_offset    = 8,
2035         },
2036         [pbn_b0_bt_2_460800] = {
2037                 .flags          = FL_BASE0|FL_BASE_BARS,
2038                 .num_ports      = 2,
2039                 .base_baud      = 460800,
2040                 .uart_offset    = 8,
2041         },
2042         [pbn_b0_bt_4_460800] = {
2043                 .flags          = FL_BASE0|FL_BASE_BARS,
2044                 .num_ports      = 4,
2045                 .base_baud      = 460800,
2046                 .uart_offset    = 8,
2047         },
2048
2049         [pbn_b0_bt_1_921600] = {
2050                 .flags          = FL_BASE0|FL_BASE_BARS,
2051                 .num_ports      = 1,
2052                 .base_baud      = 921600,
2053                 .uart_offset    = 8,
2054         },
2055         [pbn_b0_bt_2_921600] = {
2056                 .flags          = FL_BASE0|FL_BASE_BARS,
2057                 .num_ports      = 2,
2058                 .base_baud      = 921600,
2059                 .uart_offset    = 8,
2060         },
2061         [pbn_b0_bt_4_921600] = {
2062                 .flags          = FL_BASE0|FL_BASE_BARS,
2063                 .num_ports      = 4,
2064                 .base_baud      = 921600,
2065                 .uart_offset    = 8,
2066         },
2067         [pbn_b0_bt_8_921600] = {
2068                 .flags          = FL_BASE0|FL_BASE_BARS,
2069                 .num_ports      = 8,
2070                 .base_baud      = 921600,
2071                 .uart_offset    = 8,
2072         },
2073
2074         [pbn_b1_1_115200] = {
2075                 .flags          = FL_BASE1,
2076                 .num_ports      = 1,
2077                 .base_baud      = 115200,
2078                 .uart_offset    = 8,
2079         },
2080         [pbn_b1_2_115200] = {
2081                 .flags          = FL_BASE1,
2082                 .num_ports      = 2,
2083                 .base_baud      = 115200,
2084                 .uart_offset    = 8,
2085         },
2086         [pbn_b1_4_115200] = {
2087                 .flags          = FL_BASE1,
2088                 .num_ports      = 4,
2089                 .base_baud      = 115200,
2090                 .uart_offset    = 8,
2091         },
2092         [pbn_b1_8_115200] = {
2093                 .flags          = FL_BASE1,
2094                 .num_ports      = 8,
2095                 .base_baud      = 115200,
2096                 .uart_offset    = 8,
2097         },
2098         [pbn_b1_16_115200] = {
2099                 .flags          = FL_BASE1,
2100                 .num_ports      = 16,
2101                 .base_baud      = 115200,
2102                 .uart_offset    = 8,
2103         },
2104
2105         [pbn_b1_1_921600] = {
2106                 .flags          = FL_BASE1,
2107                 .num_ports      = 1,
2108                 .base_baud      = 921600,
2109                 .uart_offset    = 8,
2110         },
2111         [pbn_b1_2_921600] = {
2112                 .flags          = FL_BASE1,
2113                 .num_ports      = 2,
2114                 .base_baud      = 921600,
2115                 .uart_offset    = 8,
2116         },
2117         [pbn_b1_4_921600] = {
2118                 .flags          = FL_BASE1,
2119                 .num_ports      = 4,
2120                 .base_baud      = 921600,
2121                 .uart_offset    = 8,
2122         },
2123         [pbn_b1_8_921600] = {
2124                 .flags          = FL_BASE1,
2125                 .num_ports      = 8,
2126                 .base_baud      = 921600,
2127                 .uart_offset    = 8,
2128         },
2129         [pbn_b1_2_1250000] = {
2130                 .flags          = FL_BASE1,
2131                 .num_ports      = 2,
2132                 .base_baud      = 1250000,
2133                 .uart_offset    = 8,
2134         },
2135
2136         [pbn_b1_bt_1_115200] = {
2137                 .flags          = FL_BASE1|FL_BASE_BARS,
2138                 .num_ports      = 1,
2139                 .base_baud      = 115200,
2140                 .uart_offset    = 8,
2141         },
2142         [pbn_b1_bt_2_115200] = {
2143                 .flags          = FL_BASE1|FL_BASE_BARS,
2144                 .num_ports      = 2,
2145                 .base_baud      = 115200,
2146                 .uart_offset    = 8,
2147         },
2148         [pbn_b1_bt_4_115200] = {
2149                 .flags          = FL_BASE1|FL_BASE_BARS,
2150                 .num_ports      = 4,
2151                 .base_baud      = 115200,
2152                 .uart_offset    = 8,
2153         },
2154
2155         [pbn_b1_bt_2_921600] = {
2156                 .flags          = FL_BASE1|FL_BASE_BARS,
2157                 .num_ports      = 2,
2158                 .base_baud      = 921600,
2159                 .uart_offset    = 8,
2160         },
2161
2162         [pbn_b1_1_1382400] = {
2163                 .flags          = FL_BASE1,
2164                 .num_ports      = 1,
2165                 .base_baud      = 1382400,
2166                 .uart_offset    = 8,
2167         },
2168         [pbn_b1_2_1382400] = {
2169                 .flags          = FL_BASE1,
2170                 .num_ports      = 2,
2171                 .base_baud      = 1382400,
2172                 .uart_offset    = 8,
2173         },
2174         [pbn_b1_4_1382400] = {
2175                 .flags          = FL_BASE1,
2176                 .num_ports      = 4,
2177                 .base_baud      = 1382400,
2178                 .uart_offset    = 8,
2179         },
2180         [pbn_b1_8_1382400] = {
2181                 .flags          = FL_BASE1,
2182                 .num_ports      = 8,
2183                 .base_baud      = 1382400,
2184                 .uart_offset    = 8,
2185         },
2186
2187         [pbn_b2_1_115200] = {
2188                 .flags          = FL_BASE2,
2189                 .num_ports      = 1,
2190                 .base_baud      = 115200,
2191                 .uart_offset    = 8,
2192         },
2193         [pbn_b2_2_115200] = {
2194                 .flags          = FL_BASE2,
2195                 .num_ports      = 2,
2196                 .base_baud      = 115200,
2197                 .uart_offset    = 8,
2198         },
2199         [pbn_b2_4_115200] = {
2200                 .flags          = FL_BASE2,
2201                 .num_ports      = 4,
2202                 .base_baud      = 115200,
2203                 .uart_offset    = 8,
2204         },
2205         [pbn_b2_8_115200] = {
2206                 .flags          = FL_BASE2,
2207                 .num_ports      = 8,
2208                 .base_baud      = 115200,
2209                 .uart_offset    = 8,
2210         },
2211
2212         [pbn_b2_1_460800] = {
2213                 .flags          = FL_BASE2,
2214                 .num_ports      = 1,
2215                 .base_baud      = 460800,
2216                 .uart_offset    = 8,
2217         },
2218         [pbn_b2_4_460800] = {
2219                 .flags          = FL_BASE2,
2220                 .num_ports      = 4,
2221                 .base_baud      = 460800,
2222                 .uart_offset    = 8,
2223         },
2224         [pbn_b2_8_460800] = {
2225                 .flags          = FL_BASE2,
2226                 .num_ports      = 8,
2227                 .base_baud      = 460800,
2228                 .uart_offset    = 8,
2229         },
2230         [pbn_b2_16_460800] = {
2231                 .flags          = FL_BASE2,
2232                 .num_ports      = 16,
2233                 .base_baud      = 460800,
2234                 .uart_offset    = 8,
2235          },
2236
2237         [pbn_b2_1_921600] = {
2238                 .flags          = FL_BASE2,
2239                 .num_ports      = 1,
2240                 .base_baud      = 921600,
2241                 .uart_offset    = 8,
2242         },
2243         [pbn_b2_4_921600] = {
2244                 .flags          = FL_BASE2,
2245                 .num_ports      = 4,
2246                 .base_baud      = 921600,
2247                 .uart_offset    = 8,
2248         },
2249         [pbn_b2_8_921600] = {
2250                 .flags          = FL_BASE2,
2251                 .num_ports      = 8,
2252                 .base_baud      = 921600,
2253                 .uart_offset    = 8,
2254         },
2255
2256         [pbn_b2_8_1152000] = {
2257                 .flags          = FL_BASE2,
2258                 .num_ports      = 8,
2259                 .base_baud      = 1152000,
2260                 .uart_offset    = 8,
2261         },
2262
2263         [pbn_b2_bt_1_115200] = {
2264                 .flags          = FL_BASE2|FL_BASE_BARS,
2265                 .num_ports      = 1,
2266                 .base_baud      = 115200,
2267                 .uart_offset    = 8,
2268         },
2269         [pbn_b2_bt_2_115200] = {
2270                 .flags          = FL_BASE2|FL_BASE_BARS,
2271                 .num_ports      = 2,
2272                 .base_baud      = 115200,
2273                 .uart_offset    = 8,
2274         },
2275         [pbn_b2_bt_4_115200] = {
2276                 .flags          = FL_BASE2|FL_BASE_BARS,
2277                 .num_ports      = 4,
2278                 .base_baud      = 115200,
2279                 .uart_offset    = 8,
2280         },
2281
2282         [pbn_b2_bt_2_921600] = {
2283                 .flags          = FL_BASE2|FL_BASE_BARS,
2284                 .num_ports      = 2,
2285                 .base_baud      = 921600,
2286                 .uart_offset    = 8,
2287         },
2288         [pbn_b2_bt_4_921600] = {
2289                 .flags          = FL_BASE2|FL_BASE_BARS,
2290                 .num_ports      = 4,
2291                 .base_baud      = 921600,
2292                 .uart_offset    = 8,
2293         },
2294
2295         [pbn_b3_2_115200] = {
2296                 .flags          = FL_BASE3,
2297                 .num_ports      = 2,
2298                 .base_baud      = 115200,
2299                 .uart_offset    = 8,
2300         },
2301         [pbn_b3_4_115200] = {
2302                 .flags          = FL_BASE3,
2303                 .num_ports      = 4,
2304                 .base_baud      = 115200,
2305                 .uart_offset    = 8,
2306         },
2307         [pbn_b3_8_115200] = {
2308                 .flags          = FL_BASE3,
2309                 .num_ports      = 8,
2310                 .base_baud      = 115200,
2311                 .uart_offset    = 8,
2312         },
2313
2314         [pbn_b4_bt_2_921600] = {
2315                 .flags          = FL_BASE4,
2316                 .num_ports      = 2,
2317                 .base_baud      = 921600,
2318                 .uart_offset    = 8,
2319         },
2320         [pbn_b4_bt_4_921600] = {
2321                 .flags          = FL_BASE4,
2322                 .num_ports      = 4,
2323                 .base_baud      = 921600,
2324                 .uart_offset    = 8,
2325         },
2326         [pbn_b4_bt_8_921600] = {
2327                 .flags          = FL_BASE4,
2328                 .num_ports      = 8,
2329                 .base_baud      = 921600,
2330                 .uart_offset    = 8,
2331         },
2332
2333         /*
2334          * Entries following this are board-specific.
2335          */
2336
2337         /*
2338          * Panacom - IOMEM
2339          */
2340         [pbn_panacom] = {
2341                 .flags          = FL_BASE2,
2342                 .num_ports      = 2,
2343                 .base_baud      = 921600,
2344                 .uart_offset    = 0x400,
2345                 .reg_shift      = 7,
2346         },
2347         [pbn_panacom2] = {
2348                 .flags          = FL_BASE2|FL_BASE_BARS,
2349                 .num_ports      = 2,
2350                 .base_baud      = 921600,
2351                 .uart_offset    = 0x400,
2352                 .reg_shift      = 7,
2353         },
2354         [pbn_panacom4] = {
2355                 .flags          = FL_BASE2|FL_BASE_BARS,
2356                 .num_ports      = 4,
2357                 .base_baud      = 921600,
2358                 .uart_offset    = 0x400,
2359                 .reg_shift      = 7,
2360         },
2361
2362         [pbn_exsys_4055] = {
2363                 .flags          = FL_BASE2,
2364                 .num_ports      = 4,
2365                 .base_baud      = 115200,
2366                 .uart_offset    = 8,
2367         },
2368
2369         /* I think this entry is broken - the first_offset looks wrong --rmk */
2370         [pbn_plx_romulus] = {
2371                 .flags          = FL_BASE2,
2372                 .num_ports      = 4,
2373                 .base_baud      = 921600,
2374                 .uart_offset    = 8 << 2,
2375                 .reg_shift      = 2,
2376                 .first_offset   = 0x03,
2377         },
2378
2379         /*
2380          * This board uses the size of PCI Base region 0 to
2381          * signal now many ports are available
2382          */
2383         [pbn_oxsemi] = {
2384                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2385                 .num_ports      = 32,
2386                 .base_baud      = 115200,
2387                 .uart_offset    = 8,
2388         },
2389         [pbn_oxsemi_1_4000000] = {
2390                 .flags          = FL_BASE0,
2391                 .num_ports      = 1,
2392                 .base_baud      = 4000000,
2393                 .uart_offset    = 0x200,
2394                 .first_offset   = 0x1000,
2395         },
2396         [pbn_oxsemi_2_4000000] = {
2397                 .flags          = FL_BASE0,
2398                 .num_ports      = 2,
2399                 .base_baud      = 4000000,
2400                 .uart_offset    = 0x200,
2401                 .first_offset   = 0x1000,
2402         },
2403         [pbn_oxsemi_4_4000000] = {
2404                 .flags          = FL_BASE0,
2405                 .num_ports      = 4,
2406                 .base_baud      = 4000000,
2407                 .uart_offset    = 0x200,
2408                 .first_offset   = 0x1000,
2409         },
2410         [pbn_oxsemi_8_4000000] = {
2411                 .flags          = FL_BASE0,
2412                 .num_ports      = 8,
2413                 .base_baud      = 4000000,
2414                 .uart_offset    = 0x200,
2415                 .first_offset   = 0x1000,
2416         },
2417
2418
2419         /*
2420          * EKF addition for i960 Boards form EKF with serial port.
2421          * Max 256 ports.
2422          */
2423         [pbn_intel_i960] = {
2424                 .flags          = FL_BASE0,
2425                 .num_ports      = 32,
2426                 .base_baud      = 921600,
2427                 .uart_offset    = 8 << 2,
2428                 .reg_shift      = 2,
2429                 .first_offset   = 0x10000,
2430         },
2431         [pbn_sgi_ioc3] = {
2432                 .flags          = FL_BASE0|FL_NOIRQ,
2433                 .num_ports      = 1,
2434                 .base_baud      = 458333,
2435                 .uart_offset    = 8,
2436                 .reg_shift      = 0,
2437                 .first_offset   = 0x20178,
2438         },
2439
2440         /*
2441          * Computone - uses IOMEM.
2442          */
2443         [pbn_computone_4] = {
2444                 .flags          = FL_BASE0,
2445                 .num_ports      = 4,
2446                 .base_baud      = 921600,
2447                 .uart_offset    = 0x40,
2448                 .reg_shift      = 2,
2449                 .first_offset   = 0x200,
2450         },
2451         [pbn_computone_6] = {
2452                 .flags          = FL_BASE0,
2453                 .num_ports      = 6,
2454                 .base_baud      = 921600,
2455                 .uart_offset    = 0x40,
2456                 .reg_shift      = 2,
2457                 .first_offset   = 0x200,
2458         },
2459         [pbn_computone_8] = {
2460                 .flags          = FL_BASE0,
2461                 .num_ports      = 8,
2462                 .base_baud      = 921600,
2463                 .uart_offset    = 0x40,
2464                 .reg_shift      = 2,
2465                 .first_offset   = 0x200,
2466         },
2467         [pbn_sbsxrsio] = {
2468                 .flags          = FL_BASE0,
2469                 .num_ports      = 8,
2470                 .base_baud      = 460800,
2471                 .uart_offset    = 256,
2472                 .reg_shift      = 4,
2473         },
2474         /*
2475          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2476          *  Only basic 16550A support.
2477          *  XR17C15[24] are not tested, but they should work.
2478          */
2479         [pbn_exar_XR17C152] = {
2480                 .flags          = FL_BASE0,
2481                 .num_ports      = 2,
2482                 .base_baud      = 921600,
2483                 .uart_offset    = 0x200,
2484         },
2485         [pbn_exar_XR17C154] = {
2486                 .flags          = FL_BASE0,
2487                 .num_ports      = 4,
2488                 .base_baud      = 921600,
2489                 .uart_offset    = 0x200,
2490         },
2491         [pbn_exar_XR17C158] = {
2492                 .flags          = FL_BASE0,
2493                 .num_ports      = 8,
2494                 .base_baud      = 921600,
2495                 .uart_offset    = 0x200,
2496         },
2497         [pbn_exar_ibm_saturn] = {
2498                 .flags          = FL_BASE0,
2499                 .num_ports      = 1,
2500                 .base_baud      = 921600,
2501                 .uart_offset    = 0x200,
2502         },
2503
2504         /*
2505          * PA Semi PWRficient PA6T-1682M on-chip UART
2506          */
2507         [pbn_pasemi_1682M] = {
2508                 .flags          = FL_BASE0,
2509                 .num_ports      = 1,
2510                 .base_baud      = 8333333,
2511         },
2512         /*
2513          * National Instruments 843x
2514          */
2515         [pbn_ni8430_16] = {
2516                 .flags          = FL_BASE0,
2517                 .num_ports      = 16,
2518                 .base_baud      = 3686400,
2519                 .uart_offset    = 0x10,
2520                 .first_offset   = 0x800,
2521         },
2522         [pbn_ni8430_8] = {
2523                 .flags          = FL_BASE0,
2524                 .num_ports      = 8,
2525                 .base_baud      = 3686400,
2526                 .uart_offset    = 0x10,
2527                 .first_offset   = 0x800,
2528         },
2529         [pbn_ni8430_4] = {
2530                 .flags          = FL_BASE0,
2531                 .num_ports      = 4,
2532                 .base_baud      = 3686400,
2533                 .uart_offset    = 0x10,
2534                 .first_offset   = 0x800,
2535         },
2536         [pbn_ni8430_2] = {
2537                 .flags          = FL_BASE0,
2538                 .num_ports      = 2,
2539                 .base_baud      = 3686400,
2540                 .uart_offset    = 0x10,
2541                 .first_offset   = 0x800,
2542         },
2543         /*
2544          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2545          */
2546         [pbn_ADDIDATA_PCIe_1_3906250] = {
2547                 .flags          = FL_BASE0,
2548                 .num_ports      = 1,
2549                 .base_baud      = 3906250,
2550                 .uart_offset    = 0x200,
2551                 .first_offset   = 0x1000,
2552         },
2553         [pbn_ADDIDATA_PCIe_2_3906250] = {
2554                 .flags          = FL_BASE0,
2555                 .num_ports      = 2,
2556                 .base_baud      = 3906250,
2557                 .uart_offset    = 0x200,
2558                 .first_offset   = 0x1000,
2559         },
2560         [pbn_ADDIDATA_PCIe_4_3906250] = {
2561                 .flags          = FL_BASE0,
2562                 .num_ports      = 4,
2563                 .base_baud      = 3906250,
2564                 .uart_offset    = 0x200,
2565                 .first_offset   = 0x1000,
2566         },
2567         [pbn_ADDIDATA_PCIe_8_3906250] = {
2568                 .flags          = FL_BASE0,
2569                 .num_ports      = 8,
2570                 .base_baud      = 3906250,
2571                 .uart_offset    = 0x200,
2572                 .first_offset   = 0x1000,
2573         },
2574         [pbn_ce4100_1_115200] = {
2575                 .flags          = FL_BASE0,
2576                 .num_ports      = 1,
2577                 .base_baud      = 921600,
2578                 .reg_shift      = 2,
2579         },
2580         [pbn_omegapci] = {
2581                 .flags          = FL_BASE0,
2582                 .num_ports      = 8,
2583                 .base_baud      = 115200,
2584                 .uart_offset    = 0x200,
2585         },
2586         [pbn_NETMOS9900_2s_115200] = {
2587                 .flags          = FL_BASE0,
2588                 .num_ports      = 2,
2589                 .base_baud      = 115200,
2590         },
2591         [pbn_brcm_trumanage] = {
2592                 .flags          = FL_BASE0,
2593                 .num_ports      = 1,
2594                 .reg_shift      = 2,
2595                 .base_baud      = 115200,
2596         },
2597 };
2598
2599 static const struct pci_device_id softmodem_blacklist[] = {
2600         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2601         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2602         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2603 };
2604
2605 /*
2606  * Given a complete unknown PCI device, try to use some heuristics to
2607  * guess what the configuration might be, based on the pitiful PCI
2608  * serial specs.  Returns 0 on success, 1 on failure.
2609  */
2610 static int __devinit
2611 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2612 {
2613         const struct pci_device_id *blacklist;
2614         int num_iomem, num_port, first_port = -1, i;
2615
2616         /*
2617          * If it is not a communications device or the programming
2618          * interface is greater than 6, give up.
2619          *
2620          * (Should we try to make guesses for multiport serial devices
2621          * later?)
2622          */
2623         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2624              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2625             (dev->class & 0xff) > 6)
2626                 return -ENODEV;
2627
2628         /*
2629          * Do not access blacklisted devices that are known not to
2630          * feature serial ports.
2631          */
2632         for (blacklist = softmodem_blacklist;
2633              blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
2634              blacklist++) {
2635                 if (dev->vendor == blacklist->vendor &&
2636                     dev->device == blacklist->device)
2637                         return -ENODEV;
2638         }
2639
2640         num_iomem = num_port = 0;
2641         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2642                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2643                         num_port++;
2644                         if (first_port == -1)
2645                                 first_port = i;
2646                 }
2647                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2648                         num_iomem++;
2649         }
2650
2651         /*
2652          * If there is 1 or 0 iomem regions, and exactly one port,
2653          * use it.  We guess the number of ports based on the IO
2654          * region size.
2655          */
2656         if (num_iomem <= 1 && num_port == 1) {
2657                 board->flags = first_port;
2658                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2659                 return 0;
2660         }
2661
2662         /*
2663          * Now guess if we've got a board which indexes by BARs.
2664          * Each IO BAR should be 8 bytes, and they should follow
2665          * consecutively.
2666          */
2667         first_port = -1;
2668         num_port = 0;
2669         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2670                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2671                     pci_resource_len(dev, i) == 8 &&
2672                     (first_port == -1 || (first_port + num_port) == i)) {
2673                         num_port++;
2674                         if (first_port == -1)
2675                                 first_port = i;
2676                 }
2677         }
2678
2679         if (num_port > 1) {
2680                 board->flags = first_port | FL_BASE_BARS;
2681                 board->num_ports = num_port;
2682                 return 0;
2683         }
2684
2685         return -ENODEV;
2686 }
2687
2688 static inline int
2689 serial_pci_matches(const struct pciserial_board *board,
2690                    const struct pciserial_board *guessed)
2691 {
2692         return
2693             board->num_ports == guessed->num_ports &&
2694             board->base_baud == guessed->base_baud &&
2695             board->uart_offset == guessed->uart_offset &&
2696             board->reg_shift == guessed->reg_shift &&
2697             board->first_offset == guessed->first_offset;
2698 }
2699
2700 struct serial_private *
2701 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2702 {
2703         struct uart_port serial_port;
2704         struct serial_private *priv;
2705         struct pci_serial_quirk *quirk;
2706         int rc, nr_ports, i;
2707
2708         nr_ports = board->num_ports;
2709
2710         /*
2711          * Find an init and setup quirks.
2712          */
2713         quirk = find_quirk(dev);
2714
2715         /*
2716          * Run the new-style initialization function.
2717          * The initialization function returns:
2718          *  <0  - error
2719          *   0  - use board->num_ports
2720          *  >0  - number of ports
2721          */
2722         if (quirk->init) {
2723                 rc = quirk->init(dev);
2724                 if (rc < 0) {
2725                         priv = ERR_PTR(rc);
2726                         goto err_out;
2727                 }
2728                 if (rc)
2729                         nr_ports = rc;
2730         }
2731
2732         priv = kzalloc(sizeof(struct serial_private) +
2733                        sizeof(unsigned int) * nr_ports,
2734                        GFP_KERNEL);
2735         if (!priv) {
2736                 priv = ERR_PTR(-ENOMEM);
2737                 goto err_deinit;
2738         }
2739
2740         priv->dev = dev;
2741         priv->quirk = quirk;
2742
2743         memset(&serial_port, 0, sizeof(struct uart_port));
2744         serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2745         serial_port.uartclk = board->base_baud * 16;
2746         serial_port.irq = get_pci_irq(dev, board);
2747         serial_port.dev = &dev->dev;
2748
2749         for (i = 0; i < nr_ports; i++) {
2750                 if (quirk->setup(priv, board, &serial_port, i))
2751                         break;
2752
2753 #ifdef SERIAL_DEBUG_PCI
2754                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2755                        serial_port.iobase, serial_port.irq, serial_port.iotype);
2756 #endif
2757
2758                 priv->line[i] = serial8250_register_port(&serial_port);
2759                 if (priv->line[i] < 0) {
2760                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2761                         break;
2762                 }
2763         }
2764         priv->nr = i;
2765         return priv;
2766
2767 err_deinit:
2768         if (quirk->exit)
2769                 quirk->exit(dev);
2770 err_out:
2771         return priv;
2772 }
2773 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2774
2775 void pciserial_remove_ports(struct serial_private *priv)
2776 {
2777         struct pci_serial_quirk *quirk;
2778         int i;
2779
2780         for (i = 0; i < priv->nr; i++)
2781                 serial8250_unregister_port(priv->line[i]);
2782
2783         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2784                 if (priv->remapped_bar[i])
2785                         iounmap(priv->remapped_bar[i]);
2786                 priv->remapped_bar[i] = NULL;
2787         }
2788
2789         /*
2790          * Find the exit quirks.
2791          */
2792         quirk = find_quirk(priv->dev);
2793         if (quirk->exit)
2794                 quirk->exit(priv->dev);
2795
2796         kfree(priv);
2797 }
2798 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2799
2800 void pciserial_suspend_ports(struct serial_private *priv)
2801 {
2802         int i;
2803
2804         for (i = 0; i < priv->nr; i++)
2805                 if (priv->line[i] >= 0)
2806                         serial8250_suspend_port(priv->line[i]);
2807 }
2808 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2809
2810 void pciserial_resume_ports(struct serial_private *priv)
2811 {
2812         int i;
2813
2814         /*
2815          * Ensure that the board is correctly configured.
2816          */
2817         if (priv->quirk->init)
2818                 priv->quirk->init(priv->dev);
2819
2820         for (i = 0; i < priv->nr; i++)
2821                 if (priv->line[i] >= 0)
2822                         serial8250_resume_port(priv->line[i]);
2823 }
2824 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2825
2826 /*
2827  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2828  * to the arrangement of serial ports on a PCI card.
2829  */
2830 static int __devinit
2831 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2832 {
2833         struct pci_serial_quirk *quirk;
2834         struct serial_private *priv;
2835         const struct pciserial_board *board;
2836         struct pciserial_board tmp;
2837         int rc;
2838
2839         quirk = find_quirk(dev);
2840         if (quirk->probe) {
2841                 rc = quirk->probe(dev);
2842                 if (rc)
2843                         return rc;
2844         }
2845
2846         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2847                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2848                         ent->driver_data);
2849                 return -EINVAL;
2850         }
2851
2852         board = &pci_boards[ent->driver_data];
2853
2854         rc = pci_enable_device(dev);
2855         pci_save_state(dev);
2856         if (rc)
2857                 return rc;
2858
2859         if (ent->driver_data == pbn_default) {
2860                 /*
2861                  * Use a copy of the pci_board entry for this;
2862                  * avoid changing entries in the table.
2863                  */
2864                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2865                 board = &tmp;
2866
2867                 /*
2868                  * We matched one of our class entries.  Try to
2869                  * determine the parameters of this board.
2870                  */
2871                 rc = serial_pci_guess_board(dev, &tmp);
2872                 if (rc)
2873                         goto disable;
2874         } else {
2875                 /*
2876                  * We matched an explicit entry.  If we are able to
2877                  * detect this boards settings with our heuristic,
2878                  * then we no longer need this entry.
2879                  */
2880                 memcpy(&tmp, &pci_boards[pbn_default],
2881                        sizeof(struct pciserial_board));
2882                 rc = serial_pci_guess_board(dev, &tmp);
2883                 if (rc == 0 && serial_pci_matches(board, &tmp))
2884                         moan_device("Redundant entry in serial pci_table.",
2885                                     dev);
2886         }
2887
2888         priv = pciserial_init_ports(dev, board);
2889         if (!IS_ERR(priv)) {
2890                 pci_set_drvdata(dev, priv);
2891                 return 0;
2892         }
2893
2894         rc = PTR_ERR(priv);
2895
2896  disable:
2897         pci_disable_device(dev);
2898         return rc;
2899 }
2900
2901 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2902 {
2903         struct serial_private *priv = pci_get_drvdata(dev);
2904
2905         pci_set_drvdata(dev, NULL);
2906
2907         pciserial_remove_ports(priv);
2908
2909         pci_disable_device(dev);
2910 }
2911
2912 #ifdef CONFIG_PM
2913 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
2914 {
2915         struct serial_private *priv = pci_get_drvdata(dev);
2916
2917         if (priv)
2918                 pciserial_suspend_ports(priv);
2919
2920         pci_save_state(dev);
2921         pci_set_power_state(dev, pci_choose_state(dev, state));
2922         return 0;
2923 }
2924
2925 static int pciserial_resume_one(struct pci_dev *dev)
2926 {
2927         int err;
2928         struct serial_private *priv = pci_get_drvdata(dev);
2929
2930         pci_set_power_state(dev, PCI_D0);
2931         pci_restore_state(dev);
2932
2933         if (priv) {
2934                 /*
2935                  * The device may have been disabled.  Re-enable it.
2936                  */
2937                 err = pci_enable_device(dev);
2938                 /* FIXME: We cannot simply error out here */
2939                 if (err)
2940                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
2941                 pciserial_resume_ports(priv);
2942         }
2943         return 0;
2944 }
2945 #endif
2946
2947 static struct pci_device_id serial_pci_tbl[] = {
2948         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2949         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
2950                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
2951                 pbn_b2_8_921600 },
2952         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2953                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2954                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2955                 pbn_b1_8_1382400 },
2956         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2957                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2958                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2959                 pbn_b1_4_1382400 },
2960         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
2961                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2962                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2963                 pbn_b1_2_1382400 },
2964         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2965                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2966                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
2967                 pbn_b1_8_1382400 },
2968         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2969                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2970                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
2971                 pbn_b1_4_1382400 },
2972         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2973                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2974                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
2975                 pbn_b1_2_1382400 },
2976         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2977                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2978                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
2979                 pbn_b1_8_921600 },
2980         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2981                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2982                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
2983                 pbn_b1_8_921600 },
2984         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2985                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2986                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
2987                 pbn_b1_4_921600 },
2988         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2989                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2990                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
2991                 pbn_b1_4_921600 },
2992         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2993                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2994                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
2995                 pbn_b1_2_921600 },
2996         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
2997                 PCI_SUBVENDOR_ID_CONNECT_TECH,
2998                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
2999                 pbn_b1_8_921600 },
3000         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3001                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3002                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3003                 pbn_b1_8_921600 },
3004         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3005                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3006                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3007                 pbn_b1_4_921600 },
3008         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3009                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3010                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3011                 pbn_b1_2_1250000 },
3012         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3013                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3014                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3015                 pbn_b0_2_1843200 },
3016         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3017                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3018                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3019                 pbn_b0_4_1843200 },
3020         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3021                 PCI_VENDOR_ID_AFAVLAB,
3022                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3023                 pbn_b0_4_1152000 },
3024         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3025                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3026                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3027                 pbn_b0_2_1843200_200 },
3028         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3029                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3030                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3031                 pbn_b0_4_1843200_200 },
3032         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3033                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3034                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3035                 pbn_b0_8_1843200_200 },
3036         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3037                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3038                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3039                 pbn_b0_2_1843200_200 },
3040         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3041                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3042                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3043                 pbn_b0_4_1843200_200 },
3044         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3045                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3046                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3047                 pbn_b0_8_1843200_200 },
3048         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3049                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3050                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3051                 pbn_b0_2_1843200_200 },
3052         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3053                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3054                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3055                 pbn_b0_4_1843200_200 },
3056         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3057                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3058                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3059                 pbn_b0_8_1843200_200 },
3060         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3061                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3062                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3063                 pbn_b0_2_1843200_200 },
3064         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3065                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3066                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3067                 pbn_b0_4_1843200_200 },
3068         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3069                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3070                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3071                 pbn_b0_8_1843200_200 },
3072         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3073                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3074                 0, 0, pbn_exar_ibm_saturn },
3075
3076         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3077                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3078                 pbn_b2_bt_1_115200 },
3079         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3080                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3081                 pbn_b2_bt_2_115200 },
3082         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3083                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3084                 pbn_b2_bt_4_115200 },
3085         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3086                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3087                 pbn_b2_bt_2_115200 },
3088         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3090                 pbn_b2_bt_4_115200 },
3091         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3092                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3093                 pbn_b2_8_115200 },
3094         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3095                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3096                 pbn_b2_8_460800 },
3097         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3098                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3099                 pbn_b2_8_115200 },
3100
3101         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3102                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3103                 pbn_b2_bt_2_115200 },
3104         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3105                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3106                 pbn_b2_bt_2_921600 },
3107         /*
3108          * VScom SPCOM800, from sl@s.pl
3109          */
3110         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3111                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3112                 pbn_b2_8_921600 },
3113         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3114                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3115                 pbn_b2_4_921600 },
3116         /* Unknown card - subdevice 0x1584 */
3117         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3118                 PCI_VENDOR_ID_PLX,
3119                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3120                 pbn_b2_4_115200 },
3121         /* Unknown card - subdevice 0x1588 */
3122         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3123                 PCI_VENDOR_ID_PLX,
3124                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3125                 pbn_b2_8_115200 },
3126         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3127                 PCI_SUBVENDOR_ID_KEYSPAN,
3128                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3129                 pbn_panacom },
3130         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3131                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3132                 pbn_panacom4 },
3133         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3134                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3135                 pbn_panacom2 },
3136         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3137                 PCI_VENDOR_ID_ESDGMBH,
3138                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3139                 pbn_b2_4_115200 },
3140         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3141                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3142                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3143                 pbn_b2_4_460800 },
3144         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3145                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3146                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3147                 pbn_b2_8_460800 },
3148         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3149                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3150                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3151                 pbn_b2_16_460800 },
3152         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3153                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3154                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3155                 pbn_b2_16_460800 },
3156         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3157                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3158                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3159                 pbn_b2_4_460800 },
3160         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3161                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3162                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3163                 pbn_b2_8_460800 },
3164         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3165                 PCI_SUBVENDOR_ID_EXSYS,
3166                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3167                 pbn_exsys_4055 },
3168         /*
3169          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3170          * (Exoray@isys.ca)
3171          */
3172         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3173                 0x10b5, 0x106a, 0, 0,
3174                 pbn_plx_romulus },
3175         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3176                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3177                 pbn_b1_4_115200 },
3178         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3179                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3180                 pbn_b1_2_115200 },
3181         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3182                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3183                 pbn_b1_8_115200 },
3184         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3185                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3186                 pbn_b1_8_115200 },
3187         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3188                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3189                 0, 0,
3190                 pbn_b0_4_921600 },
3191         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3192                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3193                 0, 0,
3194                 pbn_b0_4_1152000 },
3195         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3196                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3197                 pbn_b0_bt_2_921600 },
3198
3199                 /*
3200                  * The below card is a little controversial since it is the
3201                  * subject of a PCI vendor/device ID clash.  (See
3202                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3203                  * For now just used the hex ID 0x950a.
3204                  */
3205         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3206                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3207                 0, 0, pbn_b0_2_115200 },
3208         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3209                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3210                 0, 0, pbn_b0_2_115200 },
3211         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3212                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3213                 pbn_b0_2_1130000 },
3214         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3215                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3216                 pbn_b0_1_921600 },
3217         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3218                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3219                 pbn_b0_4_115200 },
3220         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3221                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3222                 pbn_b0_bt_2_921600 },
3223         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3224                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3225                 pbn_b2_8_1152000 },
3226
3227         /*
3228          * Oxford Semiconductor Inc. Tornado PCI express device range.
3229          */
3230         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3231                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3232                 pbn_b0_1_4000000 },
3233         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3234                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3235                 pbn_b0_1_4000000 },
3236         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3237                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3238                 pbn_oxsemi_1_4000000 },
3239         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3240                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3241                 pbn_oxsemi_1_4000000 },
3242         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3243                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3244                 pbn_b0_1_4000000 },
3245         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3246                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3247                 pbn_b0_1_4000000 },
3248         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3249                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3250                 pbn_oxsemi_1_4000000 },
3251         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3252                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3253                 pbn_oxsemi_1_4000000 },
3254         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3255                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3256                 pbn_b0_1_4000000 },
3257         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3258                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3259                 pbn_b0_1_4000000 },
3260         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3261                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3262                 pbn_b0_1_4000000 },
3263         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3264                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3265                 pbn_b0_1_4000000 },
3266         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3267                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3268                 pbn_oxsemi_2_4000000 },
3269         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3270                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3271                 pbn_oxsemi_2_4000000 },
3272         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3273                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3274                 pbn_oxsemi_4_4000000 },
3275         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3276                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3277                 pbn_oxsemi_4_4000000 },
3278         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3279                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3280                 pbn_oxsemi_8_4000000 },
3281         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3282                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3283                 pbn_oxsemi_8_4000000 },
3284         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3285                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3286                 pbn_oxsemi_1_4000000 },
3287         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3288                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3289                 pbn_oxsemi_1_4000000 },
3290         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3291                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3292                 pbn_oxsemi_1_4000000 },
3293         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3294                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3295                 pbn_oxsemi_1_4000000 },
3296         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3297                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3298                 pbn_oxsemi_1_4000000 },
3299         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3300                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3301                 pbn_oxsemi_1_4000000 },
3302         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3303                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3304                 pbn_oxsemi_1_4000000 },
3305         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3306                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3307                 pbn_oxsemi_1_4000000 },
3308         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3309                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3310                 pbn_oxsemi_1_4000000 },
3311         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3312                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3313                 pbn_oxsemi_1_4000000 },
3314         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3315                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3316                 pbn_oxsemi_1_4000000 },
3317         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3318                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3319                 pbn_oxsemi_1_4000000 },
3320         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3321                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3322                 pbn_oxsemi_1_4000000 },
3323         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3324                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3325                 pbn_oxsemi_1_4000000 },
3326         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3328                 pbn_oxsemi_1_4000000 },
3329         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3330                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3331                 pbn_oxsemi_1_4000000 },
3332         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3333                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3334                 pbn_oxsemi_1_4000000 },
3335         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3336                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3337                 pbn_oxsemi_1_4000000 },
3338         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3339                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3340                 pbn_oxsemi_1_4000000 },
3341         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3342                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3343                 pbn_oxsemi_1_4000000 },
3344         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3345                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3346                 pbn_oxsemi_1_4000000 },
3347         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3348                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3349                 pbn_oxsemi_1_4000000 },
3350         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3351                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3352                 pbn_oxsemi_1_4000000 },
3353         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3354                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3355                 pbn_oxsemi_1_4000000 },
3356         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3357                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3358                 pbn_oxsemi_1_4000000 },
3359         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3360                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3361                 pbn_oxsemi_1_4000000 },
3362         /*
3363          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3364          */
3365         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3366                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3367                 pbn_oxsemi_1_4000000 },
3368         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3369                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3370                 pbn_oxsemi_2_4000000 },
3371         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3372                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3373                 pbn_oxsemi_4_4000000 },
3374         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3375                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3376                 pbn_oxsemi_8_4000000 },
3377
3378         /*
3379          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3380          */
3381         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3382                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3383                 pbn_oxsemi_2_4000000 },
3384
3385         /*
3386          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3387          * from skokodyn@yahoo.com
3388          */
3389         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3390                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3391                 pbn_sbsxrsio },
3392         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3393                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3394                 pbn_sbsxrsio },
3395         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3396                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3397                 pbn_sbsxrsio },
3398         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3399                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3400                 pbn_sbsxrsio },
3401
3402         /*
3403          * Digitan DS560-558, from jimd@esoft.com
3404          */
3405         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3406                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3407                 pbn_b1_1_115200 },
3408
3409         /*
3410          * Titan Electronic cards
3411          *  The 400L and 800L have a custom setup quirk.
3412          */
3413         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3414                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3415                 pbn_b0_1_921600 },
3416         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3417                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3418                 pbn_b0_2_921600 },
3419         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3420                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3421                 pbn_b0_4_921600 },
3422         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3423                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3424                 pbn_b0_4_921600 },
3425         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3426                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3427                 pbn_b1_1_921600 },
3428         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3429                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3430                 pbn_b1_bt_2_921600 },
3431         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3432                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3433                 pbn_b0_bt_4_921600 },
3434         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3435                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3436                 pbn_b0_bt_8_921600 },
3437         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3438                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3439                 pbn_b4_bt_2_921600 },
3440         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3441                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3442                 pbn_b4_bt_4_921600 },
3443         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3444                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3445                 pbn_b4_bt_8_921600 },
3446         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3447                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3448                 pbn_b0_4_921600 },
3449         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3450                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,