2 * Driver for 8250/16550-type serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright (C) 2001 Russell King.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * A note about mapbase / membase
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
60 static struct uart_driver serial8250_reg;
62 static int serial_index(struct uart_port *port)
64 return (serial8250_reg.minor - 64) + port->line;
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
79 #define DEBUG_INTR(fmt...) printk(fmt)
81 #define DEBUG_INTR(fmt...) do { } while (0)
84 #define PASS_LIMIT 512
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
94 #define is_real_interrupt(irq) ((irq) != 0)
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
107 #define CONFIG_HUB6 1
109 #include <asm/serial.h>
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
119 static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
125 #ifdef CONFIG_SERIAL_8250_RSA
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA */
132 struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
159 struct hlist_node node;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
170 * Here we define the default xmit fifo size used for each type of UART.
172 static const struct serial8250_config uart_config[] = {
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
233 .name = "16C950/954",
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
316 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
319 [PORT_BRCM_TRUMANAGE] = {
323 .flags = UART_CAP_HFIFO,
325 [PORT_ALTR_16550_F32] = {
326 .name = "Altera 16550 FIFO32",
329 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
330 .flags = UART_CAP_FIFO | UART_CAP_AFE,
332 [PORT_ALTR_16550_F64] = {
333 .name = "Altera 16550 FIFO64",
336 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
337 .flags = UART_CAP_FIFO | UART_CAP_AFE,
339 [PORT_ALTR_16550_F128] = {
340 .name = "Altera 16550 FIFO128",
343 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
344 .flags = UART_CAP_FIFO | UART_CAP_AFE,
348 #if defined(CONFIG_MIPS_ALCHEMY)
350 /* Au1x00 UART hardware has a weird register layout */
351 static const u8 au_io_in_map[] = {
361 static const u8 au_io_out_map[] = {
369 /* sane hardware needs no mapping */
370 static inline int map_8250_in_reg(struct uart_port *p, int offset)
372 if (p->iotype != UPIO_AU)
374 return au_io_in_map[offset];
377 static inline int map_8250_out_reg(struct uart_port *p, int offset)
379 if (p->iotype != UPIO_AU)
381 return au_io_out_map[offset];
384 #elif defined(CONFIG_SERIAL_8250_RM9K)
408 static inline int map_8250_in_reg(struct uart_port *p, int offset)
410 if (p->iotype != UPIO_RM9000)
412 return regmap_in[offset];
415 static inline int map_8250_out_reg(struct uart_port *p, int offset)
417 if (p->iotype != UPIO_RM9000)
419 return regmap_out[offset];
424 /* sane hardware needs no mapping */
425 #define map_8250_in_reg(up, offset) (offset)
426 #define map_8250_out_reg(up, offset) (offset)
430 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
432 offset = map_8250_in_reg(p, offset) << p->regshift;
433 outb(p->hub6 - 1 + offset, p->iobase);
434 return inb(p->iobase + 1);
437 static void hub6_serial_out(struct uart_port *p, int offset, int value)
439 offset = map_8250_out_reg(p, offset) << p->regshift;
440 outb(p->hub6 - 1 + offset, p->iobase);
441 outb(value, p->iobase + 1);
444 static unsigned int mem_serial_in(struct uart_port *p, int offset)
446 offset = map_8250_in_reg(p, offset) << p->regshift;
447 return readb(p->membase + offset);
450 static void mem_serial_out(struct uart_port *p, int offset, int value)
452 offset = map_8250_out_reg(p, offset) << p->regshift;
453 writeb(value, p->membase + offset);
456 static void mem32_serial_out(struct uart_port *p, int offset, int value)
458 offset = map_8250_out_reg(p, offset) << p->regshift;
459 writel(value, p->membase + offset);
462 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
464 offset = map_8250_in_reg(p, offset) << p->regshift;
465 return readl(p->membase + offset);
468 static unsigned int au_serial_in(struct uart_port *p, int offset)
470 offset = map_8250_in_reg(p, offset) << p->regshift;
471 return __raw_readl(p->membase + offset);
474 static void au_serial_out(struct uart_port *p, int offset, int value)
476 offset = map_8250_out_reg(p, offset) << p->regshift;
477 __raw_writel(value, p->membase + offset);
480 static unsigned int io_serial_in(struct uart_port *p, int offset)
482 offset = map_8250_in_reg(p, offset) << p->regshift;
483 return inb(p->iobase + offset);
486 static void io_serial_out(struct uart_port *p, int offset, int value)
488 offset = map_8250_out_reg(p, offset) << p->regshift;
489 outb(value, p->iobase + offset);
492 static int serial8250_default_handle_irq(struct uart_port *port);
494 static void set_io_from_upio(struct uart_port *p)
496 struct uart_8250_port *up =
497 container_of(p, struct uart_8250_port, port);
500 p->serial_in = hub6_serial_in;
501 p->serial_out = hub6_serial_out;
505 p->serial_in = mem_serial_in;
506 p->serial_out = mem_serial_out;
511 p->serial_in = mem32_serial_in;
512 p->serial_out = mem32_serial_out;
516 p->serial_in = au_serial_in;
517 p->serial_out = au_serial_out;
521 p->serial_in = io_serial_in;
522 p->serial_out = io_serial_out;
525 /* Remember loaded iotype */
526 up->cur_iotype = p->iotype;
527 p->handle_irq = serial8250_default_handle_irq;
531 serial_out_sync(struct uart_8250_port *up, int offset, int value)
533 struct uart_port *p = &up->port;
538 p->serial_out(p, offset, value);
539 p->serial_in(p, UART_LCR); /* safe, no side-effects */
542 p->serial_out(p, offset, value);
546 #define serial_in(up, offset) \
547 (up->port.serial_in(&(up)->port, (offset)))
548 #define serial_out(up, offset, value) \
549 (up->port.serial_out(&(up)->port, (offset), (value)))
551 * We used to support using pause I/O for certain machines. We
552 * haven't supported this for a while, but just in case it's badly
553 * needed for certain old 386 machines, I've left these #define's
556 #define serial_inp(up, offset) serial_in(up, offset)
557 #define serial_outp(up, offset, value) serial_out(up, offset, value)
559 /* Uart divisor latch read */
560 static inline int _serial_dl_read(struct uart_8250_port *up)
562 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
565 /* Uart divisor latch write */
566 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
568 serial_outp(up, UART_DLL, value & 0xff);
569 serial_outp(up, UART_DLM, value >> 8 & 0xff);
572 #if defined(CONFIG_MIPS_ALCHEMY)
573 /* Au1x00 haven't got a standard divisor latch */
574 static int serial_dl_read(struct uart_8250_port *up)
576 if (up->port.iotype == UPIO_AU)
577 return __raw_readl(up->port.membase + 0x28);
579 return _serial_dl_read(up);
582 static void serial_dl_write(struct uart_8250_port *up, int value)
584 if (up->port.iotype == UPIO_AU)
585 __raw_writel(value, up->port.membase + 0x28);
587 _serial_dl_write(up, value);
589 #elif defined(CONFIG_SERIAL_8250_RM9K)
590 static int serial_dl_read(struct uart_8250_port *up)
592 return (up->port.iotype == UPIO_RM9000) ?
593 (((__raw_readl(up->port.membase + 0x10) << 8) |
594 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
598 static void serial_dl_write(struct uart_8250_port *up, int value)
600 if (up->port.iotype == UPIO_RM9000) {
601 __raw_writel(value, up->port.membase + 0x08);
602 __raw_writel(value >> 8, up->port.membase + 0x10);
604 _serial_dl_write(up, value);
608 #define serial_dl_read(up) _serial_dl_read(up)
609 #define serial_dl_write(up, value) _serial_dl_write(up, value)
615 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
617 serial_out(up, UART_SCR, offset);
618 serial_out(up, UART_ICR, value);
621 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
625 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
626 serial_out(up, UART_SCR, offset);
627 value = serial_in(up, UART_ICR);
628 serial_icr_write(up, UART_ACR, up->acr);
636 static void serial8250_clear_fifos(struct uart_8250_port *p)
638 if (p->capabilities & UART_CAP_FIFO) {
639 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
640 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
641 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
642 serial_outp(p, UART_FCR, 0);
647 * IER sleep support. UARTs which have EFRs need the "extended
648 * capability" bit enabled. Note that on XR16C850s, we need to
649 * reset LCR to write to IER.
651 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
653 if (p->capabilities & UART_CAP_SLEEP) {
654 if (p->capabilities & UART_CAP_EFR) {
655 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
656 serial_outp(p, UART_EFR, UART_EFR_ECB);
657 serial_outp(p, UART_LCR, 0);
659 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
660 if (p->capabilities & UART_CAP_EFR) {
661 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
662 serial_outp(p, UART_EFR, 0);
663 serial_outp(p, UART_LCR, 0);
668 #ifdef CONFIG_SERIAL_8250_RSA
670 * Attempts to turn on the RSA FIFO. Returns zero on failure.
671 * We set the port uart clock rate if we succeed.
673 static int __enable_rsa(struct uart_8250_port *up)
678 mode = serial_inp(up, UART_RSA_MSR);
679 result = mode & UART_RSA_MSR_FIFO;
682 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
683 mode = serial_inp(up, UART_RSA_MSR);
684 result = mode & UART_RSA_MSR_FIFO;
688 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
693 static void enable_rsa(struct uart_8250_port *up)
695 if (up->port.type == PORT_RSA) {
696 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
697 spin_lock_irq(&up->port.lock);
699 spin_unlock_irq(&up->port.lock);
701 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
702 serial_outp(up, UART_RSA_FRR, 0);
707 * Attempts to turn off the RSA FIFO. Returns zero on failure.
708 * It is unknown why interrupts were disabled in here. However,
709 * the caller is expected to preserve this behaviour by grabbing
710 * the spinlock before calling this function.
712 static void disable_rsa(struct uart_8250_port *up)
717 if (up->port.type == PORT_RSA &&
718 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
719 spin_lock_irq(&up->port.lock);
721 mode = serial_inp(up, UART_RSA_MSR);
722 result = !(mode & UART_RSA_MSR_FIFO);
725 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
726 mode = serial_inp(up, UART_RSA_MSR);
727 result = !(mode & UART_RSA_MSR_FIFO);
731 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
732 spin_unlock_irq(&up->port.lock);
735 #endif /* CONFIG_SERIAL_8250_RSA */
738 * This is a quickie test to see how big the FIFO is.
739 * It doesn't work at all the time, more's the pity.
741 static int size_fifo(struct uart_8250_port *up)
743 unsigned char old_fcr, old_mcr, old_lcr;
744 unsigned short old_dl;
747 old_lcr = serial_inp(up, UART_LCR);
748 serial_outp(up, UART_LCR, 0);
749 old_fcr = serial_inp(up, UART_FCR);
750 old_mcr = serial_inp(up, UART_MCR);
751 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
752 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
753 serial_outp(up, UART_MCR, UART_MCR_LOOP);
754 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
755 old_dl = serial_dl_read(up);
756 serial_dl_write(up, 0x0001);
757 serial_outp(up, UART_LCR, 0x03);
758 for (count = 0; count < 256; count++)
759 serial_outp(up, UART_TX, count);
760 mdelay(20);/* FIXME - schedule_timeout */
761 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
762 (count < 256); count++)
763 serial_inp(up, UART_RX);
764 serial_outp(up, UART_FCR, old_fcr);
765 serial_outp(up, UART_MCR, old_mcr);
766 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
767 serial_dl_write(up, old_dl);
768 serial_outp(up, UART_LCR, old_lcr);
774 * Read UART ID using the divisor method - set DLL and DLM to zero
775 * and the revision will be in DLL and device type in DLM. We
776 * preserve the device state across this.
778 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
780 unsigned char old_dll, old_dlm, old_lcr;
783 old_lcr = serial_inp(p, UART_LCR);
784 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
786 old_dll = serial_inp(p, UART_DLL);
787 old_dlm = serial_inp(p, UART_DLM);
789 serial_outp(p, UART_DLL, 0);
790 serial_outp(p, UART_DLM, 0);
792 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
794 serial_outp(p, UART_DLL, old_dll);
795 serial_outp(p, UART_DLM, old_dlm);
796 serial_outp(p, UART_LCR, old_lcr);
802 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
803 * When this function is called we know it is at least a StarTech
804 * 16650 V2, but it might be one of several StarTech UARTs, or one of
805 * its clones. (We treat the broken original StarTech 16650 V1 as a
806 * 16550, and why not? Startech doesn't seem to even acknowledge its
809 * What evil have men's minds wrought...
811 static void autoconfig_has_efr(struct uart_8250_port *up)
813 unsigned int id1, id2, id3, rev;
816 * Everything with an EFR has SLEEP
818 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
821 * First we check to see if it's an Oxford Semiconductor UART.
823 * If we have to do this here because some non-National
824 * Semiconductor clone chips lock up if you try writing to the
825 * LSR register (which serial_icr_read does)
829 * Check for Oxford Semiconductor 16C950.
831 * EFR [4] must be set else this test fails.
833 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
834 * claims that it's needed for 952 dual UART's (which are not
835 * recommended for new designs).
838 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
839 serial_out(up, UART_EFR, UART_EFR_ECB);
840 serial_out(up, UART_LCR, 0x00);
841 id1 = serial_icr_read(up, UART_ID1);
842 id2 = serial_icr_read(up, UART_ID2);
843 id3 = serial_icr_read(up, UART_ID3);
844 rev = serial_icr_read(up, UART_REV);
846 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
848 if (id1 == 0x16 && id2 == 0xC9 &&
849 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
850 up->port.type = PORT_16C950;
853 * Enable work around for the Oxford Semiconductor 952 rev B
854 * chip which causes it to seriously miscalculate baud rates
857 if (id3 == 0x52 && rev == 0x01)
858 up->bugs |= UART_BUG_QUOT;
863 * We check for a XR16C850 by setting DLL and DLM to 0, and then
864 * reading back DLL and DLM. The chip type depends on the DLM
866 * 0x10 - XR16C850 and the DLL contains the chip revision.
870 id1 = autoconfig_read_divisor_id(up);
871 DEBUG_AUTOCONF("850id=%04x ", id1);
874 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
875 up->port.type = PORT_16850;
880 * It wasn't an XR16C850.
882 * We distinguish between the '654 and the '650 by counting
883 * how many bytes are in the FIFO. I'm using this for now,
884 * since that's the technique that was sent to me in the
885 * serial driver update, but I'm not convinced this works.
886 * I've had problems doing this in the past. -TYT
888 if (size_fifo(up) == 64)
889 up->port.type = PORT_16654;
891 up->port.type = PORT_16650V2;
895 * We detected a chip without a FIFO. Only two fall into
896 * this category - the original 8250 and the 16450. The
897 * 16450 has a scratch register (accessible with LCR=0)
899 static void autoconfig_8250(struct uart_8250_port *up)
901 unsigned char scratch, status1, status2;
903 up->port.type = PORT_8250;
905 scratch = serial_in(up, UART_SCR);
906 serial_outp(up, UART_SCR, 0xa5);
907 status1 = serial_in(up, UART_SCR);
908 serial_outp(up, UART_SCR, 0x5a);
909 status2 = serial_in(up, UART_SCR);
910 serial_outp(up, UART_SCR, scratch);
912 if (status1 == 0xa5 && status2 == 0x5a)
913 up->port.type = PORT_16450;
916 static int broken_efr(struct uart_8250_port *up)
919 * Exar ST16C2550 "A2" devices incorrectly detect as
920 * having an EFR, and report an ID of 0x0201. See
921 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
923 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
929 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
931 unsigned char status;
933 status = serial_in(up, 0x04); /* EXCR2 */
934 #define PRESL(x) ((x) & 0x30)
935 if (PRESL(status) == 0x10) {
936 /* already in high speed mode */
939 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
940 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
941 serial_outp(up, 0x04, status);
947 * We know that the chip has FIFOs. Does it have an EFR? The
948 * EFR is located in the same register position as the IIR and
949 * we know the top two bits of the IIR are currently set. The
950 * EFR should contain zero. Try to read the EFR.
952 static void autoconfig_16550a(struct uart_8250_port *up)
954 unsigned char status1, status2;
955 unsigned int iersave;
957 up->port.type = PORT_16550A;
958 up->capabilities |= UART_CAP_FIFO;
961 * Check for presence of the EFR when DLAB is set.
962 * Only ST16C650V1 UARTs pass this test.
964 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
965 if (serial_in(up, UART_EFR) == 0) {
966 serial_outp(up, UART_EFR, 0xA8);
967 if (serial_in(up, UART_EFR) != 0) {
968 DEBUG_AUTOCONF("EFRv1 ");
969 up->port.type = PORT_16650;
970 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
972 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
974 serial_outp(up, UART_EFR, 0);
979 * Maybe it requires 0xbf to be written to the LCR.
980 * (other ST16C650V2 UARTs, TI16C752A, etc)
982 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
983 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
984 DEBUG_AUTOCONF("EFRv2 ");
985 autoconfig_has_efr(up);
990 * Check for a National Semiconductor SuperIO chip.
991 * Attempt to switch to bank 2, read the value of the LOOP bit
992 * from EXCR1. Switch back to bank 0, change it in MCR. Then
993 * switch back to bank 2, read it from EXCR1 again and check
994 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
996 serial_outp(up, UART_LCR, 0);
997 status1 = serial_in(up, UART_MCR);
998 serial_outp(up, UART_LCR, 0xE0);
999 status2 = serial_in(up, 0x02); /* EXCR1 */
1001 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1002 serial_outp(up, UART_LCR, 0);
1003 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
1004 serial_outp(up, UART_LCR, 0xE0);
1005 status2 = serial_in(up, 0x02); /* EXCR1 */
1006 serial_outp(up, UART_LCR, 0);
1007 serial_outp(up, UART_MCR, status1);
1009 if ((status2 ^ status1) & UART_MCR_LOOP) {
1010 unsigned short quot;
1012 serial_outp(up, UART_LCR, 0xE0);
1014 quot = serial_dl_read(up);
1017 if (ns16550a_goto_highspeed(up))
1018 serial_dl_write(up, quot);
1020 serial_outp(up, UART_LCR, 0);
1022 up->port.uartclk = 921600*16;
1023 up->port.type = PORT_NS16550A;
1024 up->capabilities |= UART_NATSEMI;
1030 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1031 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1032 * Try setting it with and without DLAB set. Cheap clones
1033 * set bit 5 without DLAB set.
1035 serial_outp(up, UART_LCR, 0);
1036 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1037 status1 = serial_in(up, UART_IIR) >> 5;
1038 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1039 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1040 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1041 status2 = serial_in(up, UART_IIR) >> 5;
1042 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1043 serial_outp(up, UART_LCR, 0);
1045 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1047 if (status1 == 6 && status2 == 7) {
1048 up->port.type = PORT_16750;
1049 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1054 * Try writing and reading the UART_IER_UUE bit (b6).
1055 * If it works, this is probably one of the Xscale platform's
1057 * We're going to explicitly set the UUE bit to 0 before
1058 * trying to write and read a 1 just to make sure it's not
1059 * already a 1 and maybe locked there before we even start start.
1061 iersave = serial_in(up, UART_IER);
1062 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1063 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1065 * OK it's in a known zero state, try writing and reading
1066 * without disturbing the current state of the other bits.
1068 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1069 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1072 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1074 DEBUG_AUTOCONF("Xscale ");
1075 up->port.type = PORT_XSCALE;
1076 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1081 * If we got here we couldn't force the IER_UUE bit to 0.
1082 * Log it and continue.
1084 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1086 serial_outp(up, UART_IER, iersave);
1089 * Exar uarts have EFR in a weird location
1091 if (up->port.flags & UPF_EXAR_EFR) {
1092 up->port.type = PORT_XR17D15X;
1093 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1097 * We distinguish between 16550A and U6 16550A by counting
1098 * how many bytes are in the FIFO.
1100 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1101 up->port.type = PORT_U6_16550A;
1102 up->capabilities |= UART_CAP_AFE;
1107 * This routine is called by rs_init() to initialize a specific serial
1108 * port. It determines what type of UART chip this serial port is
1109 * using: 8250, 16450, 16550, 16550A. The important question is
1110 * whether or not this UART is a 16550A or not, since this will
1111 * determine whether or not we can use its FIFO features or not.
1113 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1115 unsigned char status1, scratch, scratch2, scratch3;
1116 unsigned char save_lcr, save_mcr;
1117 unsigned long flags;
1119 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1122 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1123 serial_index(&up->port), up->port.iobase, up->port.membase);
1126 * We really do need global IRQs disabled here - we're going to
1127 * be frobbing the chips IRQ enable register to see if it exists.
1129 spin_lock_irqsave(&up->port.lock, flags);
1131 up->capabilities = 0;
1134 if (!(up->port.flags & UPF_BUGGY_UART)) {
1136 * Do a simple existence test first; if we fail this,
1137 * there's no point trying anything else.
1139 * 0x80 is used as a nonsense port to prevent against
1140 * false positives due to ISA bus float. The
1141 * assumption is that 0x80 is a non-existent port;
1142 * which should be safe since include/asm/io.h also
1143 * makes this assumption.
1145 * Note: this is safe as long as MCR bit 4 is clear
1146 * and the device is in "PC" mode.
1148 scratch = serial_inp(up, UART_IER);
1149 serial_outp(up, UART_IER, 0);
1154 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1155 * 16C754B) allow only to modify them if an EFR bit is set.
1157 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1158 serial_outp(up, UART_IER, 0x0F);
1162 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1163 serial_outp(up, UART_IER, scratch);
1164 if (scratch2 != 0 || scratch3 != 0x0F) {
1166 * We failed; there's nothing here
1168 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1169 scratch2, scratch3);
1174 save_mcr = serial_in(up, UART_MCR);
1175 save_lcr = serial_in(up, UART_LCR);
1178 * Check to see if a UART is really there. Certain broken
1179 * internal modems based on the Rockwell chipset fail this
1180 * test, because they apparently don't implement the loopback
1181 * test mode. So this test is skipped on the COM 1 through
1182 * COM 4 ports. This *should* be safe, since no board
1183 * manufacturer would be stupid enough to design a board
1184 * that conflicts with COM 1-4 --- we hope!
1186 if (!(up->port.flags & UPF_SKIP_TEST)) {
1187 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1188 status1 = serial_inp(up, UART_MSR) & 0xF0;
1189 serial_outp(up, UART_MCR, save_mcr);
1190 if (status1 != 0x90) {
1191 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1198 * We're pretty sure there's a port here. Lets find out what
1199 * type of port it is. The IIR top two bits allows us to find
1200 * out if it's 8250 or 16450, 16550, 16550A or later. This
1201 * determines what we test for next.
1203 * We also initialise the EFR (if any) to zero for later. The
1204 * EFR occupies the same register location as the FCR and IIR.
1206 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1207 serial_outp(up, UART_EFR, 0);
1208 serial_outp(up, UART_LCR, 0);
1210 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1211 scratch = serial_in(up, UART_IIR) >> 6;
1213 DEBUG_AUTOCONF("iir=%d ", scratch);
1217 autoconfig_8250(up);
1220 up->port.type = PORT_UNKNOWN;
1223 up->port.type = PORT_16550;
1226 autoconfig_16550a(up);
1230 #ifdef CONFIG_SERIAL_8250_RSA
1232 * Only probe for RSA ports if we got the region.
1234 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1237 for (i = 0 ; i < probe_rsa_count; ++i) {
1238 if (probe_rsa[i] == up->port.iobase &&
1240 up->port.type = PORT_RSA;
1247 serial_outp(up, UART_LCR, save_lcr);
1249 if (up->capabilities != uart_config[up->port.type].flags) {
1251 "ttyS%d: detected caps %08x should be %08x\n",
1252 serial_index(&up->port), up->capabilities,
1253 uart_config[up->port.type].flags);
1256 up->port.fifosize = uart_config[up->port.type].fifo_size;
1257 up->capabilities = uart_config[up->port.type].flags;
1258 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1260 if (up->port.type == PORT_UNKNOWN)
1266 #ifdef CONFIG_SERIAL_8250_RSA
1267 if (up->port.type == PORT_RSA)
1268 serial_outp(up, UART_RSA_FRR, 0);
1270 serial_outp(up, UART_MCR, save_mcr);
1271 serial8250_clear_fifos(up);
1272 serial_in(up, UART_RX);
1273 if (up->capabilities & UART_CAP_UUE)
1274 serial_outp(up, UART_IER, UART_IER_UUE);
1276 serial_outp(up, UART_IER, 0);
1279 spin_unlock_irqrestore(&up->port.lock, flags);
1280 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1283 static void autoconfig_irq(struct uart_8250_port *up)
1285 unsigned char save_mcr, save_ier;
1286 unsigned char save_ICP = 0;
1287 unsigned int ICP = 0;
1291 if (up->port.flags & UPF_FOURPORT) {
1292 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1293 save_ICP = inb_p(ICP);
1298 /* forget possible initially masked and pending IRQ */
1299 probe_irq_off(probe_irq_on());
1300 save_mcr = serial_inp(up, UART_MCR);
1301 save_ier = serial_inp(up, UART_IER);
1302 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1304 irqs = probe_irq_on();
1305 serial_outp(up, UART_MCR, 0);
1307 if (up->port.flags & UPF_FOURPORT) {
1308 serial_outp(up, UART_MCR,
1309 UART_MCR_DTR | UART_MCR_RTS);
1311 serial_outp(up, UART_MCR,
1312 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1314 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1315 (void)serial_inp(up, UART_LSR);
1316 (void)serial_inp(up, UART_RX);
1317 (void)serial_inp(up, UART_IIR);
1318 (void)serial_inp(up, UART_MSR);
1319 serial_outp(up, UART_TX, 0xFF);
1321 irq = probe_irq_off(irqs);
1323 serial_outp(up, UART_MCR, save_mcr);
1324 serial_outp(up, UART_IER, save_ier);
1326 if (up->port.flags & UPF_FOURPORT)
1327 outb_p(save_ICP, ICP);
1329 up->port.irq = (irq > 0) ? irq : 0;
1332 static inline void __stop_tx(struct uart_8250_port *p)
1334 if (p->ier & UART_IER_THRI) {
1335 p->ier &= ~UART_IER_THRI;
1336 serial_out(p, UART_IER, p->ier);
1340 static void serial8250_stop_tx(struct uart_port *port)
1342 struct uart_8250_port *up =
1343 container_of(port, struct uart_8250_port, port);
1348 * We really want to stop the transmitter from sending.
1350 if (up->port.type == PORT_16C950) {
1351 up->acr |= UART_ACR_TXDIS;
1352 serial_icr_write(up, UART_ACR, up->acr);
1356 static void transmit_chars(struct uart_8250_port *up);
1358 static void serial8250_start_tx(struct uart_port *port)
1360 struct uart_8250_port *up =
1361 container_of(port, struct uart_8250_port, port);
1363 if (!(up->ier & UART_IER_THRI)) {
1364 up->ier |= UART_IER_THRI;
1365 serial_out(up, UART_IER, up->ier);
1367 if (up->bugs & UART_BUG_TXEN) {
1369 lsr = serial_in(up, UART_LSR);
1370 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1371 if ((up->port.type == PORT_RM9000) ?
1372 (lsr & UART_LSR_THRE) :
1373 (lsr & UART_LSR_TEMT))
1379 * Re-enable the transmitter if we disabled it.
1381 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1382 up->acr &= ~UART_ACR_TXDIS;
1383 serial_icr_write(up, UART_ACR, up->acr);
1387 static void serial8250_stop_rx(struct uart_port *port)
1389 struct uart_8250_port *up =
1390 container_of(port, struct uart_8250_port, port);
1392 up->ier &= ~UART_IER_RLSI;
1393 up->port.read_status_mask &= ~UART_LSR_DR;
1394 serial_out(up, UART_IER, up->ier);
1397 static void serial8250_enable_ms(struct uart_port *port)
1399 struct uart_8250_port *up =
1400 container_of(port, struct uart_8250_port, port);
1402 /* no MSR capabilities */
1403 if (up->bugs & UART_BUG_NOMSR)
1406 up->ier |= UART_IER_MSI;
1407 serial_out(up, UART_IER, up->ier);
1411 * Clear the Tegra rx fifo after a break
1413 * FIXME: This needs to become a port specific callback once we have a
1414 * framework for this
1416 static void clear_rx_fifo(struct uart_8250_port *up)
1418 unsigned int status, tmout = 10000;
1420 status = serial_in(up, UART_LSR);
1421 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1422 status = serial_in(up, UART_RX);
1432 receive_chars(struct uart_8250_port *up, unsigned int *status)
1434 struct tty_struct *tty = up->port.state->port.tty;
1435 unsigned char ch, lsr = *status;
1436 int max_count = 256;
1440 if (likely(lsr & UART_LSR_DR))
1441 ch = serial_inp(up, UART_RX);
1444 * Intel 82571 has a Serial Over Lan device that will
1445 * set UART_LSR_BI without setting UART_LSR_DR when
1446 * it receives a break. To avoid reading from the
1447 * receive buffer without UART_LSR_DR bit set, we
1448 * just force the read character to be 0
1453 up->port.icount.rx++;
1455 lsr |= up->lsr_saved_flags;
1456 up->lsr_saved_flags = 0;
1458 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1460 * For statistics only
1462 if (lsr & UART_LSR_BI) {
1463 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1464 up->port.icount.brk++;
1466 * If tegra port then clear the rx fifo to
1467 * accept another break/character.
1469 if (up->port.type == PORT_TEGRA)
1473 * We do the SysRQ and SAK checking
1474 * here because otherwise the break
1475 * may get masked by ignore_status_mask
1476 * or read_status_mask.
1478 if (uart_handle_break(&up->port))
1480 } else if (lsr & UART_LSR_PE)
1481 up->port.icount.parity++;
1482 else if (lsr & UART_LSR_FE)
1483 up->port.icount.frame++;
1484 if (lsr & UART_LSR_OE)
1485 up->port.icount.overrun++;
1488 * Mask off conditions which should be ignored.
1490 lsr &= up->port.read_status_mask;
1492 if (lsr & UART_LSR_BI) {
1493 DEBUG_INTR("handling break....");
1495 } else if (lsr & UART_LSR_PE)
1497 else if (lsr & UART_LSR_FE)
1500 if (uart_handle_sysrq_char(&up->port, ch))
1503 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1506 lsr = serial_inp(up, UART_LSR);
1507 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1508 spin_unlock(&up->port.lock);
1509 tty_flip_buffer_push(tty);
1510 spin_lock(&up->port.lock);
1514 static void transmit_chars(struct uart_8250_port *up)
1516 struct circ_buf *xmit = &up->port.state->xmit;
1519 if (up->port.x_char) {
1520 serial_outp(up, UART_TX, up->port.x_char);
1521 up->port.icount.tx++;
1522 up->port.x_char = 0;
1525 if (uart_tx_stopped(&up->port)) {
1526 serial8250_stop_tx(&up->port);
1529 if (uart_circ_empty(xmit)) {
1534 count = up->tx_loadsz;
1536 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1537 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1538 up->port.icount.tx++;
1539 if (uart_circ_empty(xmit))
1541 if (up->capabilities & UART_CAP_HFIFO) {
1542 if ((serial_in(up, UART_LSR) & BOTH_EMPTY) !=
1546 } while (--count > 0);
1548 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1549 uart_write_wakeup(&up->port);
1551 DEBUG_INTR("THRE...");
1553 if (uart_circ_empty(xmit))
1557 static unsigned int check_modem_status(struct uart_8250_port *up)
1559 unsigned int status = serial_in(up, UART_MSR);
1561 status |= up->msr_saved_flags;
1562 up->msr_saved_flags = 0;
1563 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1564 up->port.state != NULL) {
1565 if (status & UART_MSR_TERI)
1566 up->port.icount.rng++;
1567 if (status & UART_MSR_DDSR)
1568 up->port.icount.dsr++;
1569 if (status & UART_MSR_DDCD)
1570 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1571 if (status & UART_MSR_DCTS)
1572 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1574 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1581 * This handles the interrupt from one port.
1583 static void serial8250_handle_port(struct uart_8250_port *up)
1585 unsigned int status;
1586 unsigned long flags;
1588 spin_lock_irqsave(&up->port.lock, flags);
1590 status = serial_inp(up, UART_LSR);
1592 DEBUG_INTR("status = %x...", status);
1594 if (status & (UART_LSR_DR | UART_LSR_BI))
1595 receive_chars(up, &status);
1596 check_modem_status(up);
1597 if (status & UART_LSR_THRE)
1600 spin_unlock_irqrestore(&up->port.lock, flags);
1603 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1605 struct uart_8250_port *up =
1606 container_of(port, struct uart_8250_port, port);
1608 if (!(iir & UART_IIR_NO_INT)) {
1609 serial8250_handle_port(up);
1615 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1617 static int serial8250_default_handle_irq(struct uart_port *port)
1619 struct uart_8250_port *up =
1620 container_of(port, struct uart_8250_port, port);
1621 unsigned int iir = serial_in(up, UART_IIR);
1623 return serial8250_handle_irq(port, iir);
1627 * This is the serial driver's interrupt routine.
1629 * Arjan thinks the old way was overly complex, so it got simplified.
1630 * Alan disagrees, saying that need the complexity to handle the weird
1631 * nature of ISA shared interrupts. (This is a special exception.)
1633 * In order to handle ISA shared interrupts properly, we need to check
1634 * that all ports have been serviced, and therefore the ISA interrupt
1635 * line has been de-asserted.
1637 * This means we need to loop through all ports. checking that they
1638 * don't have an interrupt pending.
1640 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1642 struct irq_info *i = dev_id;
1643 struct list_head *l, *end = NULL;
1644 int pass_counter = 0, handled = 0;
1646 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1648 spin_lock(&i->lock);
1652 struct uart_8250_port *up;
1653 struct uart_port *port;
1655 up = list_entry(l, struct uart_8250_port, list);
1658 if (port->handle_irq(port)) {
1661 } else if (end == NULL)
1666 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1667 /* If we hit this, we're dead. */
1668 printk_ratelimited(KERN_ERR
1669 "serial8250: too much work for irq%d\n", irq);
1674 spin_unlock(&i->lock);
1676 DEBUG_INTR("end.\n");
1678 return IRQ_RETVAL(handled);
1682 * To support ISA shared interrupts, we need to have one interrupt
1683 * handler that ensures that the IRQ line has been deasserted
1684 * before returning. Failing to do this will result in the IRQ
1685 * line being stuck active, and, since ISA irqs are edge triggered,
1686 * no more IRQs will be seen.
1688 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1690 spin_lock_irq(&i->lock);
1692 if (!list_empty(i->head)) {
1693 if (i->head == &up->list)
1694 i->head = i->head->next;
1695 list_del(&up->list);
1697 BUG_ON(i->head != &up->list);
1700 spin_unlock_irq(&i->lock);
1701 /* List empty so throw away the hash node */
1702 if (i->head == NULL) {
1703 hlist_del(&i->node);
1708 static int serial_link_irq_chain(struct uart_8250_port *up)
1710 struct hlist_head *h;
1711 struct hlist_node *n;
1713 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1715 mutex_lock(&hash_mutex);
1717 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1719 hlist_for_each(n, h) {
1720 i = hlist_entry(n, struct irq_info, node);
1721 if (i->irq == up->port.irq)
1726 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1728 mutex_unlock(&hash_mutex);
1731 spin_lock_init(&i->lock);
1732 i->irq = up->port.irq;
1733 hlist_add_head(&i->node, h);
1735 mutex_unlock(&hash_mutex);
1737 spin_lock_irq(&i->lock);
1740 list_add(&up->list, i->head);
1741 spin_unlock_irq(&i->lock);
1745 INIT_LIST_HEAD(&up->list);
1746 i->head = &up->list;
1747 spin_unlock_irq(&i->lock);
1748 irq_flags |= up->port.irqflags;
1749 ret = request_irq(up->port.irq, serial8250_interrupt,
1750 irq_flags, "serial", i);
1752 serial_do_unlink(i, up);
1758 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1761 struct hlist_node *n;
1762 struct hlist_head *h;
1764 mutex_lock(&hash_mutex);
1766 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1768 hlist_for_each(n, h) {
1769 i = hlist_entry(n, struct irq_info, node);
1770 if (i->irq == up->port.irq)
1775 BUG_ON(i->head == NULL);
1777 if (list_empty(i->head))
1778 free_irq(up->port.irq, i);
1780 serial_do_unlink(i, up);
1781 mutex_unlock(&hash_mutex);
1785 * This function is used to handle ports that do not have an
1786 * interrupt. This doesn't work very well for 16450's, but gives
1787 * barely passable results for a 16550A. (Although at the expense
1788 * of much CPU overhead).
1790 static void serial8250_timeout(unsigned long data)
1792 struct uart_8250_port *up = (struct uart_8250_port *)data;
1795 iir = serial_in(up, UART_IIR);
1796 if (!(iir & UART_IIR_NO_INT))
1797 serial8250_handle_port(up);
1798 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1801 static void serial8250_backup_timeout(unsigned long data)
1803 struct uart_8250_port *up = (struct uart_8250_port *)data;
1804 unsigned int iir, ier = 0, lsr;
1805 unsigned long flags;
1807 spin_lock_irqsave(&up->port.lock, flags);
1810 * Must disable interrupts or else we risk racing with the interrupt
1813 if (is_real_interrupt(up->port.irq)) {
1814 ier = serial_in(up, UART_IER);
1815 serial_out(up, UART_IER, 0);
1818 iir = serial_in(up, UART_IIR);
1821 * This should be a safe test for anyone who doesn't trust the
1822 * IIR bits on their UART, but it's specifically designed for
1823 * the "Diva" UART used on the management processor on many HP
1824 * ia64 and parisc boxes.
1826 lsr = serial_in(up, UART_LSR);
1827 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1828 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1829 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1830 (lsr & UART_LSR_THRE)) {
1831 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1832 iir |= UART_IIR_THRI;
1835 if (!(iir & UART_IIR_NO_INT))
1838 if (is_real_interrupt(up->port.irq))
1839 serial_out(up, UART_IER, ier);
1841 spin_unlock_irqrestore(&up->port.lock, flags);
1843 /* Standard timer interval plus 0.2s to keep the port running */
1844 mod_timer(&up->timer,
1845 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1848 static unsigned int serial8250_tx_empty(struct uart_port *port)
1850 struct uart_8250_port *up =
1851 container_of(port, struct uart_8250_port, port);
1852 unsigned long flags;
1855 spin_lock_irqsave(&up->port.lock, flags);
1856 lsr = serial_in(up, UART_LSR);
1857 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1858 spin_unlock_irqrestore(&up->port.lock, flags);
1860 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1863 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1865 struct uart_8250_port *up =
1866 container_of(port, struct uart_8250_port, port);
1867 unsigned int status;
1870 status = check_modem_status(up);
1873 if (status & UART_MSR_DCD)
1875 if (status & UART_MSR_RI)
1877 if (status & UART_MSR_DSR)
1879 if (status & UART_MSR_CTS)
1884 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1886 struct uart_8250_port *up =
1887 container_of(port, struct uart_8250_port, port);
1888 unsigned char mcr = 0;
1890 if (mctrl & TIOCM_RTS)
1891 mcr |= UART_MCR_RTS;
1892 if (mctrl & TIOCM_DTR)
1893 mcr |= UART_MCR_DTR;
1894 if (mctrl & TIOCM_OUT1)
1895 mcr |= UART_MCR_OUT1;
1896 if (mctrl & TIOCM_OUT2)
1897 mcr |= UART_MCR_OUT2;
1898 if (mctrl & TIOCM_LOOP)
1899 mcr |= UART_MCR_LOOP;
1901 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1903 serial_out(up, UART_MCR, mcr);
1906 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1908 struct uart_8250_port *up =
1909 container_of(port, struct uart_8250_port, port);
1910 unsigned long flags;
1912 spin_lock_irqsave(&up->port.lock, flags);
1913 if (break_state == -1)
1914 up->lcr |= UART_LCR_SBC;
1916 up->lcr &= ~UART_LCR_SBC;
1917 serial_out(up, UART_LCR, up->lcr);
1918 spin_unlock_irqrestore(&up->port.lock, flags);
1922 * Wait for transmitter & holding register to empty
1924 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1926 unsigned int status, tmout = 10000;
1928 /* Wait up to 10ms for the character(s) to be sent. */
1930 status = serial_in(up, UART_LSR);
1932 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1934 if ((status & bits) == bits)
1941 /* Wait up to 1s for flow control if necessary */
1942 if (up->port.flags & UPF_CONS_FLOW) {
1944 for (tmout = 1000000; tmout; tmout--) {
1945 unsigned int msr = serial_in(up, UART_MSR);
1946 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1947 if (msr & UART_MSR_CTS)
1950 touch_nmi_watchdog();
1955 #ifdef CONFIG_CONSOLE_POLL
1957 * Console polling routines for writing and reading from the uart while
1958 * in an interrupt or debug context.
1961 static int serial8250_get_poll_char(struct uart_port *port)
1963 struct uart_8250_port *up =
1964 container_of(port, struct uart_8250_port, port);
1965 unsigned char lsr = serial_inp(up, UART_LSR);
1967 if (!(lsr & UART_LSR_DR))
1968 return NO_POLL_CHAR;
1970 return serial_inp(up, UART_RX);
1974 static void serial8250_put_poll_char(struct uart_port *port,
1978 struct uart_8250_port *up =
1979 container_of(port, struct uart_8250_port, port);
1982 * First save the IER then disable the interrupts
1984 ier = serial_in(up, UART_IER);
1985 if (up->capabilities & UART_CAP_UUE)
1986 serial_out(up, UART_IER, UART_IER_UUE);
1988 serial_out(up, UART_IER, 0);
1990 wait_for_xmitr(up, BOTH_EMPTY);
1992 * Send the character out.
1993 * If a LF, also do CR...
1995 serial_out(up, UART_TX, c);
1997 wait_for_xmitr(up, BOTH_EMPTY);
1998 serial_out(up, UART_TX, 13);
2002 * Finally, wait for transmitter to become empty
2003 * and restore the IER
2005 wait_for_xmitr(up, BOTH_EMPTY);
2006 serial_out(up, UART_IER, ier);
2009 #endif /* CONFIG_CONSOLE_POLL */
2011 static int serial8250_startup(struct uart_port *port)
2013 struct uart_8250_port *up =
2014 container_of(port, struct uart_8250_port, port);
2015 unsigned long flags;
2016 unsigned char lsr, iir;
2019 up->port.fifosize = uart_config[up->port.type].fifo_size;
2020 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
2021 up->capabilities = uart_config[up->port.type].flags;
2024 if (up->port.iotype != up->cur_iotype)
2025 set_io_from_upio(port);
2027 if (up->port.type == PORT_16C950) {
2028 /* Wake up and initialize UART */
2030 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2031 serial_outp(up, UART_EFR, UART_EFR_ECB);
2032 serial_outp(up, UART_IER, 0);
2033 serial_outp(up, UART_LCR, 0);
2034 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2035 serial_outp(up, UART_LCR, 0xBF);
2036 serial_outp(up, UART_EFR, UART_EFR_ECB);
2037 serial_outp(up, UART_LCR, 0);
2040 #ifdef CONFIG_SERIAL_8250_RSA
2042 * If this is an RSA port, see if we can kick it up to the
2043 * higher speed clock.
2049 * Clear the FIFO buffers and disable them.
2050 * (they will be reenabled in set_termios())
2052 serial8250_clear_fifos(up);
2055 * Clear the interrupt registers.
2057 (void) serial_inp(up, UART_LSR);
2058 (void) serial_inp(up, UART_RX);
2059 (void) serial_inp(up, UART_IIR);
2060 (void) serial_inp(up, UART_MSR);
2063 * At this point, there's no way the LSR could still be 0xff;
2064 * if it is, then bail out, because there's likely no UART
2067 if (!(up->port.flags & UPF_BUGGY_UART) &&
2068 (serial_inp(up, UART_LSR) == 0xff)) {
2069 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2070 serial_index(&up->port));
2075 * For a XR16C850, we need to set the trigger levels
2077 if (up->port.type == PORT_16850) {
2080 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2082 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2083 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2084 serial_outp(up, UART_TRG, UART_TRG_96);
2085 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2086 serial_outp(up, UART_TRG, UART_TRG_96);
2088 serial_outp(up, UART_LCR, 0);
2091 if (is_real_interrupt(up->port.irq)) {
2094 * Test for UARTs that do not reassert THRE when the
2095 * transmitter is idle and the interrupt has already
2096 * been cleared. Real 16550s should always reassert
2097 * this interrupt whenever the transmitter is idle and
2098 * the interrupt is enabled. Delays are necessary to
2099 * allow register changes to become visible.
2101 spin_lock_irqsave(&up->port.lock, flags);
2102 if (up->port.irqflags & IRQF_SHARED)
2103 disable_irq_nosync(up->port.irq);
2105 wait_for_xmitr(up, UART_LSR_THRE);
2106 serial_out_sync(up, UART_IER, UART_IER_THRI);
2107 udelay(1); /* allow THRE to set */
2108 iir1 = serial_in(up, UART_IIR);
2109 serial_out(up, UART_IER, 0);
2110 serial_out_sync(up, UART_IER, UART_IER_THRI);
2111 udelay(1); /* allow a working UART time to re-assert THRE */
2112 iir = serial_in(up, UART_IIR);
2113 serial_out(up, UART_IER, 0);
2115 if (up->port.irqflags & IRQF_SHARED)
2116 enable_irq(up->port.irq);
2117 spin_unlock_irqrestore(&up->port.lock, flags);
2120 * If the interrupt is not reasserted, setup a timer to
2121 * kick the UART on a regular basis.
2123 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2124 up->bugs |= UART_BUG_THRE;
2125 pr_debug("ttyS%d - using backup timer\n",
2126 serial_index(port));
2131 * The above check will only give an accurate result the first time
2132 * the port is opened so this value needs to be preserved.
2134 if (up->bugs & UART_BUG_THRE) {
2135 up->timer.function = serial8250_backup_timeout;
2136 up->timer.data = (unsigned long)up;
2137 mod_timer(&up->timer, jiffies +
2138 uart_poll_timeout(port) + HZ / 5);
2142 * If the "interrupt" for this port doesn't correspond with any
2143 * hardware interrupt, we use a timer-based system. The original
2144 * driver used to do this with IRQ0.
2146 if (!is_real_interrupt(up->port.irq)) {
2147 up->timer.data = (unsigned long)up;
2148 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2150 retval = serial_link_irq_chain(up);
2156 * Now, initialize the UART
2158 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2160 spin_lock_irqsave(&up->port.lock, flags);
2161 if (up->port.flags & UPF_FOURPORT) {
2162 if (!is_real_interrupt(up->port.irq))
2163 up->port.mctrl |= TIOCM_OUT1;
2166 * Most PC uarts need OUT2 raised to enable interrupts.
2168 if (is_real_interrupt(up->port.irq))
2169 up->port.mctrl |= TIOCM_OUT2;
2171 serial8250_set_mctrl(&up->port, up->port.mctrl);
2173 /* Serial over Lan (SoL) hack:
2174 Intel 8257x Gigabit ethernet chips have a
2175 16550 emulation, to be used for Serial Over Lan.
2176 Those chips take a longer time than a normal
2177 serial device to signalize that a transmission
2178 data was queued. Due to that, the above test generally
2179 fails. One solution would be to delay the reading of
2180 iir. However, this is not reliable, since the timeout
2181 is variable. So, let's just don't test if we receive
2182 TX irq. This way, we'll never enable UART_BUG_TXEN.
2184 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2185 goto dont_test_tx_en;
2188 * Do a quick test to see if we receive an
2189 * interrupt when we enable the TX irq.
2191 serial_outp(up, UART_IER, UART_IER_THRI);
2192 lsr = serial_in(up, UART_LSR);
2193 iir = serial_in(up, UART_IIR);
2194 serial_outp(up, UART_IER, 0);
2196 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2197 if (!(up->bugs & UART_BUG_TXEN)) {
2198 up->bugs |= UART_BUG_TXEN;
2199 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2200 serial_index(port));
2203 up->bugs &= ~UART_BUG_TXEN;
2207 spin_unlock_irqrestore(&up->port.lock, flags);
2210 * Clear the interrupt registers again for luck, and clear the
2211 * saved flags to avoid getting false values from polling
2212 * routines or the previous session.
2214 serial_inp(up, UART_LSR);
2215 serial_inp(up, UART_RX);
2216 serial_inp(up, UART_IIR);
2217 serial_inp(up, UART_MSR);
2218 up->lsr_saved_flags = 0;
2219 up->msr_saved_flags = 0;
2222 * Finally, enable interrupts. Note: Modem status interrupts
2223 * are set via set_termios(), which will be occurring imminently
2224 * anyway, so we don't enable them here.
2226 up->ier = UART_IER_RLSI | UART_IER_RDI;
2227 serial_outp(up, UART_IER, up->ier);
2229 if (up->port.flags & UPF_FOURPORT) {
2232 * Enable interrupts on the AST Fourport board
2234 icp = (up->port.iobase & 0xfe0) | 0x01f;
2242 static void serial8250_shutdown(struct uart_port *port)
2244 struct uart_8250_port *up =
2245 container_of(port, struct uart_8250_port, port);
2246 unsigned long flags;
2249 * Disable interrupts from this port
2252 serial_outp(up, UART_IER, 0);
2254 spin_lock_irqsave(&up->port.lock, flags);
2255 if (up->port.flags & UPF_FOURPORT) {
2256 /* reset interrupts on the AST Fourport board */
2257 inb((up->port.iobase & 0xfe0) | 0x1f);
2258 up->port.mctrl |= TIOCM_OUT1;
2260 up->port.mctrl &= ~TIOCM_OUT2;
2262 serial8250_set_mctrl(&up->port, up->port.mctrl);
2263 spin_unlock_irqrestore(&up->port.lock, flags);
2266 * Disable break condition and FIFOs
2268 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2269 serial8250_clear_fifos(up);
2271 #ifdef CONFIG_SERIAL_8250_RSA
2273 * Reset the RSA board back to 115kbps compat mode.
2279 * Read data port to reset things, and then unlink from
2282 (void) serial_in(up, UART_RX);
2284 del_timer_sync(&up->timer);
2285 up->timer.function = serial8250_timeout;
2286 if (is_real_interrupt(up->port.irq))
2287 serial_unlink_irq_chain(up);
2290 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2295 * Handle magic divisors for baud rates above baud_base on
2296 * SMSC SuperIO chips.
2298 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2299 baud == (port->uartclk/4))
2301 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2302 baud == (port->uartclk/8))
2305 quot = uart_get_divisor(port, baud);
2311 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2312 struct ktermios *old)
2314 struct uart_8250_port *up =
2315 container_of(port, struct uart_8250_port, port);
2316 unsigned char cval, fcr = 0;
2317 unsigned long flags;
2318 unsigned int baud, quot;
2320 switch (termios->c_cflag & CSIZE) {
2322 cval = UART_LCR_WLEN5;
2325 cval = UART_LCR_WLEN6;
2328 cval = UART_LCR_WLEN7;
2332 cval = UART_LCR_WLEN8;
2336 if (termios->c_cflag & CSTOPB)
2337 cval |= UART_LCR_STOP;
2338 if (termios->c_cflag & PARENB)
2339 cval |= UART_LCR_PARITY;
2340 if (!(termios->c_cflag & PARODD))
2341 cval |= UART_LCR_EPAR;
2343 if (termios->c_cflag & CMSPAR)
2344 cval |= UART_LCR_SPAR;
2348 * Ask the core to calculate the divisor for us.
2350 baud = uart_get_baud_rate(port, termios, old,
2351 port->uartclk / 16 / 0xffff,
2352 port->uartclk / 16);
2353 quot = serial8250_get_divisor(port, baud);
2356 * Oxford Semi 952 rev B workaround
2358 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2361 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2362 fcr = uart_config[up->port.type].fcr;
2364 fcr &= ~UART_FCR_TRIGGER_MASK;
2365 fcr |= UART_FCR_TRIGGER_1;
2370 * MCR-based auto flow control. When AFE is enabled, RTS will be
2371 * deasserted when the receive FIFO contains more characters than
2372 * the trigger, or the MCR RTS bit is cleared. In the case where
2373 * the remote UART is not using CTS auto flow control, we must
2374 * have sufficient FIFO entries for the latency of the remote
2375 * UART to respond. IOW, at least 32 bytes of FIFO.
2377 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2378 up->mcr &= ~UART_MCR_AFE;
2379 if (termios->c_cflag & CRTSCTS)
2380 up->mcr |= UART_MCR_AFE;
2384 * Ok, we're now changing the port state. Do it with
2385 * interrupts disabled.
2387 spin_lock_irqsave(&up->port.lock, flags);
2390 * Update the per-port timeout.
2392 uart_update_timeout(port, termios->c_cflag, baud);
2394 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2395 if (termios->c_iflag & INPCK)
2396 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2397 if (termios->c_iflag & (BRKINT | PARMRK))
2398 up->port.read_status_mask |= UART_LSR_BI;
2401 * Characteres to ignore
2403 up->port.ignore_status_mask = 0;
2404 if (termios->c_iflag & IGNPAR)
2405 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2406 if (termios->c_iflag & IGNBRK) {
2407 up->port.ignore_status_mask |= UART_LSR_BI;
2409 * If we're ignoring parity and break indicators,
2410 * ignore overruns too (for real raw support).
2412 if (termios->c_iflag & IGNPAR)
2413 up->port.ignore_status_mask |= UART_LSR_OE;
2417 * ignore all characters if CREAD is not set
2419 if ((termios->c_cflag & CREAD) == 0)
2420 up->port.ignore_status_mask |= UART_LSR_DR;
2423 * CTS flow control flag and modem status interrupts
2425 up->ier &= ~UART_IER_MSI;
2426 if (!(up->bugs & UART_BUG_NOMSR) &&
2427 UART_ENABLE_MS(&up->port, termios->c_cflag))
2428 up->ier |= UART_IER_MSI;
2429 if (up->capabilities & UART_CAP_UUE)
2430 up->ier |= UART_IER_UUE;
2431 if (up->capabilities & UART_CAP_RTOIE)
2432 up->ier |= UART_IER_RTOIE;
2434 serial_out(up, UART_IER, up->ier);
2436 if (up->capabilities & UART_CAP_EFR) {
2437 unsigned char efr = 0;
2439 * TI16C752/Startech hardware flow control. FIXME:
2440 * - TI16C752 requires control thresholds to be set.
2441 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2443 if (termios->c_cflag & CRTSCTS)
2444 efr |= UART_EFR_CTS;
2446 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2447 if (up->port.flags & UPF_EXAR_EFR)
2448 serial_outp(up, UART_XR_EFR, efr);
2450 serial_outp(up, UART_EFR, efr);
2453 #ifdef CONFIG_ARCH_OMAP
2454 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2455 if (cpu_is_omap1510() && is_omap_port(up)) {
2456 if (baud == 115200) {
2458 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2460 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2464 if (up->capabilities & UART_NATSEMI) {
2465 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2466 serial_outp(up, UART_LCR, 0xe0);
2468 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2471 serial_dl_write(up, quot);
2474 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2475 * is written without DLAB set, this mode will be disabled.
2477 if (up->port.type == PORT_16750)
2478 serial_outp(up, UART_FCR, fcr);
2480 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2481 up->lcr = cval; /* Save LCR */
2482 if (up->port.type != PORT_16750) {
2483 if (fcr & UART_FCR_ENABLE_FIFO) {
2484 /* emulated UARTs (Lucent Venus 167x) need two steps */
2485 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2487 serial_outp(up, UART_FCR, fcr); /* set fcr */
2489 serial8250_set_mctrl(&up->port, up->port.mctrl);
2490 spin_unlock_irqrestore(&up->port.lock, flags);
2491 /* Don't rewrite B0 */
2492 if (tty_termios_baud_rate(termios))
2493 tty_termios_encode_baud_rate(termios, baud, baud);
2495 EXPORT_SYMBOL(serial8250_do_set_termios);
2498 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2499 struct ktermios *old)
2501 if (port->set_termios)
2502 port->set_termios(port, termios, old);
2504 serial8250_do_set_termios(port, termios, old);
2508 serial8250_set_ldisc(struct uart_port *port, int new)
2511 port->flags |= UPF_HARDPPS_CD;
2512 serial8250_enable_ms(port);
2514 port->flags &= ~UPF_HARDPPS_CD;
2518 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2519 unsigned int oldstate)
2521 struct uart_8250_port *p =
2522 container_of(port, struct uart_8250_port, port);
2524 serial8250_set_sleep(p, state != 0);
2526 EXPORT_SYMBOL(serial8250_do_pm);
2529 serial8250_pm(struct uart_port *port, unsigned int state,
2530 unsigned int oldstate)
2533 port->pm(port, state, oldstate);
2535 serial8250_do_pm(port, state, oldstate);
2538 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2540 if (pt->port.iotype == UPIO_AU)
2542 #ifdef CONFIG_ARCH_OMAP
2543 if (is_omap_port(pt))
2544 return 0x16 << pt->port.regshift;
2546 return 8 << pt->port.regshift;
2550 * Resource handling.
2552 static int serial8250_request_std_resource(struct uart_8250_port *up)
2554 unsigned int size = serial8250_port_size(up);
2557 switch (up->port.iotype) {
2562 if (!up->port.mapbase)
2565 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2570 if (up->port.flags & UPF_IOREMAP) {
2571 up->port.membase = ioremap_nocache(up->port.mapbase,
2573 if (!up->port.membase) {
2574 release_mem_region(up->port.mapbase, size);
2582 if (!request_region(up->port.iobase, size, "serial"))
2589 static void serial8250_release_std_resource(struct uart_8250_port *up)
2591 unsigned int size = serial8250_port_size(up);
2593 switch (up->port.iotype) {
2598 if (!up->port.mapbase)
2601 if (up->port.flags & UPF_IOREMAP) {
2602 iounmap(up->port.membase);
2603 up->port.membase = NULL;
2606 release_mem_region(up->port.mapbase, size);
2611 release_region(up->port.iobase, size);
2616 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2618 unsigned long start = UART_RSA_BASE << up->port.regshift;
2619 unsigned int size = 8 << up->port.regshift;
2622 switch (up->port.iotype) {
2625 start += up->port.iobase;
2626 if (request_region(start, size, "serial-rsa"))
2636 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2638 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2639 unsigned int size = 8 << up->port.regshift;
2641 switch (up->port.iotype) {
2644 release_region(up->port.iobase + offset, size);
2649 static void serial8250_release_port(struct uart_port *port)
2651 struct uart_8250_port *up =
2652 container_of(port, struct uart_8250_port, port);
2654 serial8250_release_std_resource(up);
2655 if (up->port.type == PORT_RSA)
2656 serial8250_release_rsa_resource(up);
2659 static int serial8250_request_port(struct uart_port *port)
2661 struct uart_8250_port *up =
2662 container_of(port, struct uart_8250_port, port);
2665 ret = serial8250_request_std_resource(up);
2666 if (ret == 0 && up->port.type == PORT_RSA) {
2667 ret = serial8250_request_rsa_resource(up);
2669 serial8250_release_std_resource(up);
2675 static void serial8250_config_port(struct uart_port *port, int flags)
2677 struct uart_8250_port *up =
2678 container_of(port, struct uart_8250_port, port);
2679 int probeflags = PROBE_ANY;
2683 * Find the region that we can probe for. This in turn
2684 * tells us whether we can probe for the type of port.
2686 ret = serial8250_request_std_resource(up);
2690 ret = serial8250_request_rsa_resource(up);
2692 probeflags &= ~PROBE_RSA;
2694 if (up->port.iotype != up->cur_iotype)
2695 set_io_from_upio(port);
2697 if (flags & UART_CONFIG_TYPE)
2698 autoconfig(up, probeflags);
2700 /* if access method is AU, it is a 16550 with a quirk */
2701 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2702 up->bugs |= UART_BUG_NOMSR;
2704 /* HW bugs may trigger IRQ while IIR == NO_INT */
2705 if (up->port.type == PORT_TEGRA)
2706 up->bugs |= UART_BUG_NOMSR;
2708 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2711 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2712 serial8250_release_rsa_resource(up);
2713 if (up->port.type == PORT_UNKNOWN)
2714 serial8250_release_std_resource(up);
2718 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2720 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2721 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2722 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2723 ser->type == PORT_STARTECH || uart_config[ser->type].name == NULL)
2729 serial8250_type(struct uart_port *port)
2731 int type = port->type;
2733 if (type >= ARRAY_SIZE(uart_config) || uart_config[type].name == NULL)
2735 return uart_config[type].name;
2738 static struct uart_ops serial8250_pops = {
2739 .tx_empty = serial8250_tx_empty,
2740 .set_mctrl = serial8250_set_mctrl,
2741 .get_mctrl = serial8250_get_mctrl,
2742 .stop_tx = serial8250_stop_tx,
2743 .start_tx = serial8250_start_tx,
2744 .stop_rx = serial8250_stop_rx,
2745 .enable_ms = serial8250_enable_ms,
2746 .break_ctl = serial8250_break_ctl,
2747 .startup = serial8250_startup,
2748 .shutdown = serial8250_shutdown,
2749 .set_termios = serial8250_set_termios,
2750 .set_ldisc = serial8250_set_ldisc,
2751 .pm = serial8250_pm,
2752 .type = serial8250_type,
2753 .release_port = serial8250_release_port,
2754 .request_port = serial8250_request_port,
2755 .config_port = serial8250_config_port,
2756 .verify_port = serial8250_verify_port,
2757 #ifdef CONFIG_CONSOLE_POLL
2758 .poll_get_char = serial8250_get_poll_char,
2759 .poll_put_char = serial8250_put_poll_char,
2763 static struct uart_8250_port serial8250_ports[UART_NR];
2765 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2766 unsigned short *capabilities);
2768 void serial8250_set_isa_configurator(
2769 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2771 serial8250_isa_config = v;
2773 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2775 static void __init serial8250_isa_init_ports(void)
2777 struct uart_8250_port *up;
2778 static int first = 1;
2785 for (i = 0; i < nr_uarts; i++) {
2786 struct uart_8250_port *up = &serial8250_ports[i];
2789 spin_lock_init(&up->port.lock);
2791 init_timer(&up->timer);
2792 up->timer.function = serial8250_timeout;
2795 * ALPHA_KLUDGE_MCR needs to be killed.
2797 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2798 up->mcr_force = ALPHA_KLUDGE_MCR;
2800 up->port.ops = &serial8250_pops;
2804 irqflag = IRQF_SHARED;
2806 for (i = 0, up = serial8250_ports;
2807 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2809 up->port.iobase = old_serial_port[i].port;
2810 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2811 up->port.irqflags = old_serial_port[i].irqflags;
2812 up->port.uartclk = old_serial_port[i].baud_base * 16;
2813 up->port.flags = old_serial_port[i].flags;
2814 up->port.hub6 = old_serial_port[i].hub6;
2815 up->port.membase = old_serial_port[i].iomem_base;
2816 up->port.iotype = old_serial_port[i].io_type;
2817 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2818 set_io_from_upio(&up->port);
2819 up->port.irqflags |= irqflag;
2820 if (serial8250_isa_config != NULL)
2821 serial8250_isa_config(i, &up->port, &up->capabilities);
2827 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2829 up->port.type = type;
2830 up->port.fifosize = uart_config[type].fifo_size;
2831 up->capabilities = uart_config[type].flags;
2832 up->tx_loadsz = uart_config[type].tx_loadsz;
2836 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2840 for (i = 0; i < nr_uarts; i++) {
2841 struct uart_8250_port *up = &serial8250_ports[i];
2842 up->cur_iotype = 0xFF;
2845 serial8250_isa_init_ports();
2847 for (i = 0; i < nr_uarts; i++) {
2848 struct uart_8250_port *up = &serial8250_ports[i];
2852 if (up->port.flags & UPF_FIXED_TYPE)
2853 serial8250_init_fixed_type_port(up, up->port.type);
2855 uart_add_one_port(drv, &up->port);
2859 #ifdef CONFIG_SERIAL_8250_CONSOLE
2861 static void serial8250_console_putchar(struct uart_port *port, int ch)
2863 struct uart_8250_port *up =
2864 container_of(port, struct uart_8250_port, port);
2866 wait_for_xmitr(up, UART_LSR_THRE);
2867 serial_out(up, UART_TX, ch);
2871 * Print a string to the serial port trying not to disturb
2872 * any possible real use of the port...
2874 * The console_lock must be held when we get here.
2877 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2879 struct uart_8250_port *up = &serial8250_ports[co->index];
2880 unsigned long flags;
2884 touch_nmi_watchdog();
2886 local_irq_save(flags);
2887 if (up->port.sysrq) {
2888 /* serial8250_handle_port() already took the lock */
2890 } else if (oops_in_progress) {
2891 locked = spin_trylock(&up->port.lock);
2893 spin_lock(&up->port.lock);
2896 * First save the IER then disable the interrupts
2898 ier = serial_in(up, UART_IER);
2900 if (up->capabilities & UART_CAP_UUE)
2901 serial_out(up, UART_IER, UART_IER_UUE);
2903 serial_out(up, UART_IER, 0);
2905 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2908 * Finally, wait for transmitter to become empty
2909 * and restore the IER
2911 wait_for_xmitr(up, BOTH_EMPTY);
2912 serial_out(up, UART_IER, ier);
2915 * The receive handling will happen properly because the
2916 * receive ready bit will still be set; it is not cleared
2917 * on read. However, modem control will not, we must
2918 * call it if we have saved something in the saved flags
2919 * while processing with interrupts off.
2921 if (up->msr_saved_flags)
2922 check_modem_status(up);
2925 spin_unlock(&up->port.lock);
2926 local_irq_restore(flags);
2929 static int __init serial8250_console_setup(struct console *co, char *options)
2931 struct uart_port *port;
2938 * Check whether an invalid uart number has been specified, and
2939 * if so, search for the first available port that does have
2942 if (co->index >= nr_uarts)
2944 port = &serial8250_ports[co->index].port;
2945 if (!port->iobase && !port->membase)
2949 uart_parse_options(options, &baud, &parity, &bits, &flow);
2951 return uart_set_options(port, co, baud, parity, bits, flow);
2954 static int serial8250_console_early_setup(void)
2956 return serial8250_find_port_for_earlycon();
2959 static struct console serial8250_console = {
2961 .write = serial8250_console_write,
2962 .device = uart_console_device,
2963 .setup = serial8250_console_setup,
2964 .early_setup = serial8250_console_early_setup,
2965 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2967 .data = &serial8250_reg,
2970 static int __init serial8250_console_init(void)
2972 if (nr_uarts > UART_NR)
2975 serial8250_isa_init_ports();
2976 register_console(&serial8250_console);
2979 console_initcall(serial8250_console_init);
2981 int serial8250_find_port(struct uart_port *p)
2984 struct uart_port *port;
2986 for (line = 0; line < nr_uarts; line++) {
2987 port = &serial8250_ports[line].port;
2988 if (uart_match_port(p, port))
2994 #define SERIAL8250_CONSOLE &serial8250_console
2996 #define SERIAL8250_CONSOLE NULL
2999 static struct uart_driver serial8250_reg = {
3000 .owner = THIS_MODULE,
3001 .driver_name = "serial",
3005 .cons = SERIAL8250_CONSOLE,
3009 * early_serial_setup - early registration for 8250 ports
3011 * Setup an 8250 port structure prior to console initialisation. Use
3012 * after console initialisation will cause undefined behaviour.
3014 int __init early_serial_setup(struct uart_port *port)
3016 struct uart_port *p;
3018 if (port->line >= ARRAY_SIZE(serial8250_ports))
3021 serial8250_isa_init_ports();
3022 p = &serial8250_ports[port->line].port;
3023 p->iobase = port->iobase;
3024 p->membase = port->membase;
3026 p->irqflags = port->irqflags;
3027 p->uartclk = port->uartclk;
3028 p->fifosize = port->fifosize;
3029 p->regshift = port->regshift;
3030 p->iotype = port->iotype;
3031 p->flags = port->flags;
3032 p->mapbase = port->mapbase;
3033 p->private_data = port->private_data;
3034 p->type = port->type;
3035 p->line = port->line;
3037 set_io_from_upio(p);
3038 if (port->serial_in)
3039 p->serial_in = port->serial_in;
3040 if (port->serial_out)
3041 p->serial_out = port->serial_out;
3042 if (port->handle_irq)
3043 p->handle_irq = port->handle_irq;
3045 p->handle_irq = serial8250_default_handle_irq;
3051 * serial8250_suspend_port - suspend one serial port
3052 * @line: serial line number
3054 * Suspend one serial port.
3056 void serial8250_suspend_port(int line)
3058 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3062 * serial8250_resume_port - resume one serial port
3063 * @line: serial line number
3065 * Resume one serial port.
3067 void serial8250_resume_port(int line)
3069 struct uart_8250_port *up = &serial8250_ports[line];
3071 if (up->capabilities & UART_NATSEMI) {
3072 /* Ensure it's still in high speed mode */
3073 serial_outp(up, UART_LCR, 0xE0);
3075 ns16550a_goto_highspeed(up);
3077 serial_outp(up, UART_LCR, 0);
3078 up->port.uartclk = 921600*16;
3080 uart_resume_port(&serial8250_reg, &up->port);
3084 * Register a set of serial devices attached to a platform device. The
3085 * list is terminated with a zero flags entry, which means we expect
3086 * all entries to have at least UPF_BOOT_AUTOCONF set.
3088 static int __devinit serial8250_probe(struct platform_device *dev)
3090 struct plat_serial8250_port *p = dev->dev.platform_data;
3091 struct uart_port port;
3092 int ret, i, irqflag = 0;
3094 memset(&port, 0, sizeof(struct uart_port));
3097 irqflag = IRQF_SHARED;
3099 for (i = 0; p && p->flags != 0; p++, i++) {
3100 port.iobase = p->iobase;
3101 port.membase = p->membase;
3103 port.irqflags = p->irqflags;
3104 port.uartclk = p->uartclk;
3105 port.regshift = p->regshift;
3106 port.iotype = p->iotype;
3107 port.flags = p->flags;
3108 port.mapbase = p->mapbase;
3109 port.hub6 = p->hub6;
3110 port.private_data = p->private_data;
3111 port.type = p->type;
3112 port.serial_in = p->serial_in;
3113 port.serial_out = p->serial_out;
3114 port.handle_irq = p->handle_irq;
3115 port.set_termios = p->set_termios;
3117 port.dev = &dev->dev;
3118 port.irqflags |= irqflag;
3119 ret = serial8250_register_port(&port);
3121 dev_err(&dev->dev, "unable to register port at index %d "
3122 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3123 p->iobase, (unsigned long long)p->mapbase,
3131 * Remove serial ports registered against a platform device.
3133 static int __devexit serial8250_remove(struct platform_device *dev)
3137 for (i = 0; i < nr_uarts; i++) {
3138 struct uart_8250_port *up = &serial8250_ports[i];
3140 if (up->port.dev == &dev->dev)
3141 serial8250_unregister_port(i);
3146 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3150 for (i = 0; i < UART_NR; i++) {
3151 struct uart_8250_port *up = &serial8250_ports[i];
3153 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3154 uart_suspend_port(&serial8250_reg, &up->port);
3160 static int serial8250_resume(struct platform_device *dev)
3164 for (i = 0; i < UART_NR; i++) {
3165 struct uart_8250_port *up = &serial8250_ports[i];
3167 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3168 serial8250_resume_port(i);
3174 static struct platform_driver serial8250_isa_driver = {
3175 .probe = serial8250_probe,
3176 .remove = __devexit_p(serial8250_remove),
3177 .suspend = serial8250_suspend,
3178 .resume = serial8250_resume,
3180 .name = "serial8250",
3181 .owner = THIS_MODULE,
3186 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3187 * in the table in include/asm/serial.h
3189 static struct platform_device *serial8250_isa_devs;
3192 * serial8250_register_port and serial8250_unregister_port allows for
3193 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3194 * modems and PCI multiport cards.
3196 static DEFINE_MUTEX(serial_mutex);
3198 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3203 * First, find a port entry which matches.
3205 for (i = 0; i < nr_uarts; i++)
3206 if (uart_match_port(&serial8250_ports[i].port, port))
3207 return &serial8250_ports[i];
3210 * We didn't find a matching entry, so look for the first
3211 * free entry. We look for one which hasn't been previously
3212 * used (indicated by zero iobase).
3214 for (i = 0; i < nr_uarts; i++)
3215 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3216 serial8250_ports[i].port.iobase == 0)
3217 return &serial8250_ports[i];
3220 * That also failed. Last resort is to find any entry which
3221 * doesn't have a real port associated with it.
3223 for (i = 0; i < nr_uarts; i++)
3224 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3225 return &serial8250_ports[i];
3231 * serial8250_register_port - register a serial port
3232 * @port: serial port template
3234 * Configure the serial port specified by the request. If the
3235 * port exists and is in use, it is hung up and unregistered
3238 * The port is then probed and if necessary the IRQ is autodetected
3239 * If this fails an error is returned.
3241 * On success the port is ready to use and the line number is returned.
3243 int serial8250_register_port(struct uart_port *port)
3245 struct uart_8250_port *uart;
3248 if (port->uartclk == 0)
3251 mutex_lock(&serial_mutex);
3253 uart = serial8250_find_match_or_unused(port);
3255 uart_remove_one_port(&serial8250_reg, &uart->port);
3257 uart->port.iobase = port->iobase;
3258 uart->port.membase = port->membase;
3259 uart->port.irq = port->irq;
3260 uart->port.irqflags = port->irqflags;
3261 uart->port.uartclk = port->uartclk;
3262 uart->port.fifosize = port->fifosize;
3263 uart->port.regshift = port->regshift;
3264 uart->port.iotype = port->iotype;
3265 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3266 uart->port.mapbase = port->mapbase;
3267 uart->port.private_data = port->private_data;
3269 uart->port.dev = port->dev;
3271 if (port->flags & UPF_FIXED_TYPE)
3272 serial8250_init_fixed_type_port(uart, port->type);
3274 set_io_from_upio(&uart->port);
3275 /* Possibly override default I/O functions. */
3276 if (port->serial_in)
3277 uart->port.serial_in = port->serial_in;
3278 if (port->serial_out)
3279 uart->port.serial_out = port->serial_out;
3280 if (port->handle_irq)
3281 uart->port.handle_irq = port->handle_irq;
3282 /* Possibly override set_termios call */
3283 if (port->set_termios)
3284 uart->port.set_termios = port->set_termios;
3286 uart->port.pm = port->pm;
3288 if (serial8250_isa_config != NULL)
3289 serial8250_isa_config(0, &uart->port,
3290 &uart->capabilities);
3292 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3294 ret = uart->port.line;
3296 mutex_unlock(&serial_mutex);
3300 EXPORT_SYMBOL(serial8250_register_port);
3303 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3304 * @line: serial line number
3306 * Remove one serial port. This may not be called from interrupt
3307 * context. We hand the port back to the our control.
3309 void serial8250_unregister_port(int line)
3311 struct uart_8250_port *uart = &serial8250_ports[line];
3313 mutex_lock(&serial_mutex);
3314 uart_remove_one_port(&serial8250_reg, &uart->port);
3315 if (serial8250_isa_devs) {
3316 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3317 uart->port.type = PORT_UNKNOWN;
3318 uart->port.dev = &serial8250_isa_devs->dev;
3319 uart->capabilities = uart_config[uart->port.type].flags;
3320 uart_add_one_port(&serial8250_reg, &uart->port);
3322 uart->port.dev = NULL;
3324 mutex_unlock(&serial_mutex);
3326 EXPORT_SYMBOL(serial8250_unregister_port);
3328 static int __init serial8250_init(void)
3332 if (nr_uarts > UART_NR)
3335 printk(KERN_INFO "Serial: 8250/16550 driver, "
3336 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3337 share_irqs ? "en" : "dis");
3340 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3342 serial8250_reg.nr = UART_NR;
3343 ret = uart_register_driver(&serial8250_reg);
3348 serial8250_isa_devs = platform_device_alloc("serial8250",
3349 PLAT8250_DEV_LEGACY);
3350 if (!serial8250_isa_devs) {
3352 goto unreg_uart_drv;
3355 ret = platform_device_add(serial8250_isa_devs);
3359 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3361 ret = platform_driver_register(&serial8250_isa_driver);
3365 platform_device_del(serial8250_isa_devs);
3367 platform_device_put(serial8250_isa_devs);
3370 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3372 uart_unregister_driver(&serial8250_reg);
3378 static void __exit serial8250_exit(void)
3380 struct platform_device *isa_dev = serial8250_isa_devs;
3383 * This tells serial8250_unregister_port() not to re-register
3384 * the ports (thereby making serial8250_isa_driver permanently
3387 serial8250_isa_devs = NULL;
3389 platform_driver_unregister(&serial8250_isa_driver);
3390 platform_device_unregister(isa_dev);
3393 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3395 uart_unregister_driver(&serial8250_reg);
3399 module_init(serial8250_init);
3400 module_exit(serial8250_exit);
3402 EXPORT_SYMBOL(serial8250_suspend_port);
3403 EXPORT_SYMBOL(serial8250_resume_port);
3405 MODULE_LICENSE("GPL");
3406 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3408 module_param(share_irqs, uint, 0644);
3409 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3412 module_param(nr_uarts, uint, 0644);
3413 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3415 module_param(skip_txen_test, uint, 0644);
3416 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3418 #ifdef CONFIG_SERIAL_8250_RSA
3419 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3420 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3422 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);