drivers/staging/winbond/wbhal_s.h

   1 //[20040722 WK]
   2 #define HAL_LED_SET_MASK                0x001c  //20060901 Extend
   3 #define HAL_LED_SET_SHIFT               2
   4
   5 //supported RF type
   6 #define RF_MAXIM_2825           0
   7 #define RF_MAXIM_2827           1
   8 #define RF_MAXIM_2828           2
   9 #define RF_MAXIM_2829           3
  10 #define RF_MAXIM_V1                     15
  11 #define RF_AIROHA_2230          16
  12 #define RF_AIROHA_7230          17
  13 #define RF_AIROHA_2230S         18      // 20060420 Add this
  14 // #define RF_RFMD_2959         32      // 20060626 Remove all about RFMD
  15 #define RF_WB_242                       33
  16 #define RF_WB_242_1                     34      // 20060619.5 Add
  17 #define RF_DECIDE_BY_INF        255
  18
  19 //----------------------------------------------------------------
  20 // The follow define connect to upper layer
  21 //      User must modify for connection between HAL and upper layer
  22 //----------------------------------------------------------------
  23
  24
  25
  26
  27 /////////////////////////////////////////////////////////////////////////////////////////////////////
  28 //================================================================================================
  29 // Common define
  30 //================================================================================================
  31 #define HAL_USB_MODE_BURST( _H )        (_H->SoftwareSet & 0x20 ) // Bit 5 20060901 Modify
  32
  33 // Scan interval
  34 #define SCAN_MAX_CHNL_TIME                              (50)
  35
  36 // For TxL2 Frame typr recognise
  37 #define FRAME_TYPE_802_3_DATA                   0
  38 #define FRAME_TYPE_802_11_MANAGEMENT            1
  39 #define FRAME_TYPE_802_11_MANAGEMENT_CHALLENGE  2
  40 #define FRAME_TYPE_802_11_CONTROL               3
  41 #define FRAME_TYPE_802_11_DATA                  4
  42 #define FRAME_TYPE_PROMISCUOUS                  5
  43
  44 // The follow definition is used for convert the frame--------------------
  45 #define DOT_11_SEQUENCE_OFFSET          22 //Sequence control offset
  46 #define DOT_3_TYPE_OFFSET                       12
  47 #define DOT_11_MAC_HEADER_SIZE          24
  48 #define DOT_11_SNAP_SIZE                        6
  49 #define DOT_11_TYPE_OFFSET                      30 //The start offset of 802.11 Frame. Type encapsulatuin.
  50 #define DEFAULT_SIFSTIME                        10
  51 #define DEFAULT_FRAGMENT_THRESHOLD              2346 // No fragment
  52 #define DEFAULT_MSDU_LIFE_TIME                  0xffff
  53
  54 #define LONG_PREAMBLE_PLUS_PLCPHEADER_TIME                                              (144+48)
  55 #define SHORT_PREAMBLE_PLUS_PLCPHEADER_TIME                                     (72+24)
  56 #define PREAMBLE_PLUS_SIGNAL_PLUS_SIGNALEXTENSION                               (16+4+6)
  57 #define Tsym 4
  58
  59 //  Frame Type of Bits (2, 3)---------------------------------------------
  60 #define MAC_TYPE_MANAGEMENT                     0x00
  61 #define MAC_TYPE_CONTROL                        0x04
  62 #define MAC_TYPE_DATA                           0x08
  63 #define MASK_FRAGMENT_NUMBER            0x000F
  64 #define SEQUENCE_NUMBER_SHIFT           4
  65
  66 #define  HAL_WOL_TYPE_WAKEUP_FRAME              0x01
  67 #define  HAL_WOL_TYPE_MAGIC_PACKET              0x02
  68
  69 // 20040106 ADDED
  70 #define HAL_KEYTYPE_WEP40                       0
  71 #define HAL_KEYTYPE_WEP104                      1
  72 #define HAL_KEYTYPE_TKIP                        2 // 128 bit key
  73 #define HAL_KEYTYPE_AES_CCMP                    3 // 128 bit key
  74
  75 // For VM state
  76 enum {
  77         VM_STOP = 0,
  78         VM_RUNNING,
  79         VM_COMPLETED
  80 };
  81
  82 // Be used for 802.11 mac header
  83 typedef struct _MAC_FRAME_CONTROL {
  84         u8      mac_frame_info; // this is a combination of the protovl version, type and subtype
  85         u8      to_ds:1;
  86         u8      from_ds:1;
  87         u8      more_frag:1;
  88         u8      retry:1;
  89         u8      pwr_mgt:1;
  90         u8      more_data:1;
  91         u8      WEP:1;
  92         u8      order:1;
  93 } MAC_FRAME_CONTROL, *PMAC_FRAME_CONTROL;
  94
  95 //-----------------------------------------------------
  96 // Normal Key table format
  97 //-----------------------------------------------------
  98 // The order of KEY index is MAPPING_KEY_START_INDEX > GROUP_KEY_START_INDEX
  99 #define MAX_KEY_TABLE                           24      // 24 entry for storing key data
 100 #define GROUP_KEY_START_INDEX           4
 101 #define MAPPING_KEY_START_INDEX         8
 102 typedef struct _KEY_TABLE
 103 {
 104         u32     DW0_Valid:1;
 105         u32     DW0_NullKey:1;
 106         u32     DW0_Security_Mode:2;//0:WEP 40 bit 1:WEP 104 bit 2:TKIP 128 bit 3:CCMP 128 bit
 107         u32     DW0_WEPON:1;
 108         u32     DW0_RESERVED:11;
 109         u32     DW0_Address1:16;
 110
 111         u32     DW1_Address2;
 112
 113         u32     DW2_RxSequenceCount1;
 114
 115         u32     DW3_RxSequenceCount2:16;
 116         u32     DW3_RESERVED:16;
 117
 118         u32     DW4_TxSequenceCount1;
 119
 120         u32     DW5_TxSequenceCount2:16;
 121         u32     DW5_RESERVED:16;
 122
 123 } KEY_TABLE, *PKEY_TABLE;
 124
 125 //--------------------------------------------------------
 126 //                       Descriptor
 127 //--------------------------------------------------------
 128 #define MAX_DESCRIPTOR_BUFFER_INDEX     8       // Have to multiple of 2
 129 //#define FLAG_ERROR_TX_MASK                    cpu_to_le32(0x000000bf) //20061009 marked by anson's endian
 130 #define FLAG_ERROR_TX_MASK                      0x000000bf  //20061009 anson's endian
 131 //#define FLAG_ERROR_RX_MASK                    0x00000c3f
 132 //#define FLAG_ERROR_RX_MASK                    cpu_to_le32(0x0000083f) //20061009 marked by anson's endian
 133                                                                         //Don't care replay error,
 134                                                                                                 //it is handled by S/W
 135 #define FLAG_ERROR_RX_MASK                      0x0000083f      //20060926 anson's endian
 136
 137 #define FLAG_BAND_RX_MASK                       0x10000000      //Bit 28
 138
 139 typedef struct _R00_DESCRIPTOR
 140 {
 141         union
 142         {
 143                 u32     value;
 144                 #ifdef _BIG_ENDIAN_  //20060926 anson's endian
 145                 struct
 146                 {
 147                         u32     R00_packet_or_buffer_status:1;
 148                         u32     R00_packet_in_fifo:1;
 149                         u32     R00_RESERVED:2;
 150                         u32     R00_receive_byte_count:12;
 151                         u32     R00_receive_time_index:16;
 152                 };
 153                 #else
 154                 struct
 155                 {
 156                         u32     R00_receive_time_index:16;
 157                         u32     R00_receive_byte_count:12;
 158                         u32     R00_RESERVED:2;
 159                         u32     R00_packet_in_fifo:1;
 160                         u32     R00_packet_or_buffer_status:1;
 161                 };
 162                 #endif
 163         };
 164 } R00_DESCRIPTOR, *PR00_DESCRIPTOR;
 165
 166 typedef struct _T00_DESCRIPTOR
 167 {
 168         union
 169         {
 170                 u32     value;
 171                 #ifdef _BIG_ENDIAN_  //20061009 anson's endian
 172                 struct
 173                 {
 174                         u32     T00_first_mpdu:1; // for hardware use
 175                         u32     T00_last_mpdu:1; // for hardware use
 176                         u32     T00_IsLastMpdu:1;// 0: not   1:Yes for software used
 177                         u32     T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
 178                         u32     T00_RESERVED_ID:2;//3 bit ID reserved
 179                         u32     T00_tx_packet_id:4;//930519.4.e 930810.3.c
 180                         u32     T00_RESERVED:4;
 181                         u32     T00_header_length:6;
 182                         u32     T00_frame_length:12;
 183                 };
 184                 #else
 185                 struct
 186                 {
 187                         u32     T00_frame_length:12;
 188                         u32     T00_header_length:6;
 189                         u32     T00_RESERVED:4;
 190                         u32     T00_tx_packet_id:4;//930519.4.e 930810.3.c
 191                         u32     T00_RESERVED_ID:2;//3 bit ID reserved
 192                         u32     T00_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
 193                         u32     T00_IsLastMpdu:1;// 0: not   1:Yes for software used
 194                         u32     T00_last_mpdu:1; // for hardware use
 195                         u32     T00_first_mpdu:1; // for hardware use
 196                 };
 197                 #endif
 198         };
 199 } T00_DESCRIPTOR, *PT00_DESCRIPTOR;
 200
 201 typedef struct _R01_DESCRIPTOR
 202 {
 203         union
 204         {
 205                 u32     value;
 206                 #ifdef _BIG_ENDIAN_ //20060926 add by anson's endian
 207                 struct
 208                 {
 209                         u32     R01_RESERVED:3;
 210                         u32     R01_mod_type:1;
 211                         u32     R01_pre_type:1;
 212                         u32     R01_data_rate:3;
 213                         u32     R01_AGC_state:8;
 214                         u32     R01_LNA_state:2;
 215                         u32     R01_decryption_method:2;
 216                         u32     R01_mic_error:1;
 217                         u32     R01_replay:1;
 218                         u32     R01_broadcast_frame:1;
 219                         u32     R01_multicast_frame:1;
 220                         u32     R01_directed_frame:1;
 221                         u32     R01_receive_frame_antenna_selection:1;
 222                         u32     R01_frame_receive_during_atim_window:1;
 223                         u32     R01_protocol_version_error:1;
 224                         u32     R01_authentication_frame_icv_error:1;
 225                         u32     R01_null_key_to_authentication_frame:1;
 226                         u32     R01_icv_error:1;
 227                         u32     R01_crc_error:1;
 228                 };
 229                 #else
 230                 struct
 231                 {
 232                         u32     R01_crc_error:1;
 233                         u32     R01_icv_error:1;
 234                         u32     R01_null_key_to_authentication_frame:1;
 235                         u32     R01_authentication_frame_icv_error:1;
 236                         u32     R01_protocol_version_error:1;
 237                         u32     R01_frame_receive_during_atim_window:1;
 238                         u32     R01_receive_frame_antenna_selection:1;
 239                         u32     R01_directed_frame:1;
 240                         u32     R01_multicast_frame:1;
 241                         u32     R01_broadcast_frame:1;
 242                         u32     R01_replay:1;
 243                         u32     R01_mic_error:1;
 244                         u32     R01_decryption_method:2;
 245                         u32     R01_LNA_state:2;
 246                         u32     R01_AGC_state:8;
 247                         u32     R01_data_rate:3;
 248                         u32     R01_pre_type:1;
 249                         u32     R01_mod_type:1;
 250                         u32     R01_RESERVED:3;
 251                 };
 252                 #endif
 253         };
 254 } R01_DESCRIPTOR, *PR01_DESCRIPTOR;
 255
 256 typedef struct _T01_DESCRIPTOR
 257 {
 258         union
 259         {
 260                 u32     value;
 261                 #ifdef _BIG_ENDIAN_ //20061009 anson's endian
 262                 struct
 263                 {
 264                         u32     T01_rts_cts_duration:16;
 265                         u32     T01_fall_back_rate:3;
 266                         u32     T01_add_rts:1;
 267                         u32     T01_add_cts:1;
 268                         u32     T01_modulation_type:1;
 269                         u32     T01_plcp_header_length:1;
 270                         u32     T01_transmit_rate:3;
 271                         u32     T01_wep_id:2;
 272                         u32     T01_add_challenge_text:1;
 273                         u32     T01_inhibit_crc:1;
 274                         u32     T01_loop_back_wep_mode:1;
 275                         u32     T01_retry_abort_ebable:1;
 276                 };
 277                 #else
 278                 struct
 279                 {
 280                         u32     T01_retry_abort_ebable:1;
 281                         u32     T01_loop_back_wep_mode:1;
 282                         u32     T01_inhibit_crc:1;
 283                         u32     T01_add_challenge_text:1;
 284                         u32     T01_wep_id:2;
 285                         u32     T01_transmit_rate:3;
 286                         u32     T01_plcp_header_length:1;
 287                         u32     T01_modulation_type:1;
 288                         u32     T01_add_cts:1;
 289                         u32     T01_add_rts:1;
 290                         u32     T01_fall_back_rate:3;
 291                         u32     T01_rts_cts_duration:16;
 292                 };
 293                 #endif
 294         };
 295 } T01_DESCRIPTOR, *PT01_DESCRIPTOR;
 296
 297 typedef struct _T02_DESCRIPTOR
 298 {
 299         union
 300         {
 301                 u32     value;
 302                 #ifdef _BIG_ENDIAN_  //20061009 add by anson's endian
 303                 struct
 304                 {
 305                         u32     T02_IsLastMpdu:1;// The same mechanism with T00 setting
 306                         u32     T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
 307                         u32     T02_RESERVED_ID:2;// The same mechanism with T00 setting
 308                         u32     T02_Tx_PktID:4;
 309                         u32     T02_MPDU_Cnt:4;
 310                         u32     T02_RTS_Cnt:4;
 311                         u32     T02_RESERVED:7;
 312                         u32     T02_transmit_complete:1;
 313                         u32     T02_transmit_abort_due_to_TBTT:1;
 314                         u32     T02_effective_transmission_rate:1;
 315                         u32     T02_transmit_without_encryption_due_to_wep_on_false:1;
 316                         u32     T02_discard_due_to_null_wep_key:1;
 317                         u32     T02_RESERVED_1:1;
 318                         u32     T02_out_of_MaxTxMSDULiftTime:1;
 319                         u32     T02_transmit_abort:1;
 320                         u32     T02_transmit_fail:1;
 321                 };
 322                 #else
 323                 struct
 324                 {
 325                         u32     T02_transmit_fail:1;
 326                         u32     T02_transmit_abort:1;
 327                         u32     T02_out_of_MaxTxMSDULiftTime:1;
 328                         u32     T02_RESERVED_1:1;
 329                         u32     T02_discard_due_to_null_wep_key:1;
 330                         u32     T02_transmit_without_encryption_due_to_wep_on_false:1;
 331                         u32     T02_effective_transmission_rate:1;
 332                         u32     T02_transmit_abort_due_to_TBTT:1;
 333                         u32     T02_transmit_complete:1;
 334                         u32     T02_RESERVED:7;
 335                         u32     T02_RTS_Cnt:4;
 336                         u32     T02_MPDU_Cnt:4;
 337                         u32     T02_Tx_PktID:4;
 338                         u32     T02_RESERVED_ID:2;// The same mechanism with T00 setting
 339                         u32     T02_IgnoreResult:1;// The same mechanism with T00 setting. 050111 Modify for TS
 340                         u32     T02_IsLastMpdu:1;// The same mechanism with T00 setting
 341                 };
 342                 #endif
 343         };
 344 } T02_DESCRIPTOR, *PT02_DESCRIPTOR;
 345
 346 typedef struct _DESCRIPTOR {            // Skip length = 8 DWORD
 347         // ID for descriptor ---, The field doesn't be cleard in the operation of Descriptor definition
 348         u8      Descriptor_ID;
 349         //----------------------The above region doesn't be cleared by DESCRIPTOR_RESET------
 350         u8      RESERVED[3];
 351
 352         u16     FragmentThreshold;
 353         u8      InternalUsed;//Only can be used by operation of descriptor definition
 354         u8      Type;// 0: 802.3        1:802.11 data frame     2:802.11 management frame
 355
 356         u8      PreambleMode;// 0: short 1:long
 357         u8      TxRate;
 358         u8      FragmentCount;
 359         u8      EapFix; // For speed up key install
 360
 361         // For R00 and T00 ----------------------------------------------
 362         union
 363         {
 364                 R00_DESCRIPTOR  R00;
 365                 T00_DESCRIPTOR  T00;
 366         };
 367
 368         // For R01 and T01 ----------------------------------------------
 369         union
 370         {
 371                 R01_DESCRIPTOR  R01;
 372                 T01_DESCRIPTOR  T01;
 373         };
 374
 375         // For R02 and T02 ----------------------------------------------
 376         union
 377         {
 378                 u32                     R02;
 379                 T02_DESCRIPTOR  T02;
 380         };
 381
 382         // For R03 and T03 ----------------------------------------------
 383         // For software used
 384         union
 385         {
 386                 u32     R03;
 387                 u32     T03;
 388                 struct
 389                 {
 390                         u8      buffer_number;
 391                         u8      buffer_start_index;
 392                         u16     buffer_total_size;
 393                 };
 394         };
 395
 396         // For storing the buffer
 397         u16     buffer_size[ MAX_DESCRIPTOR_BUFFER_INDEX ];
 398         void*   buffer_address[ MAX_DESCRIPTOR_BUFFER_INDEX ];//931130.4.q
 399
 400 } DESCRIPTOR, *PDESCRIPTOR;
 401
 402
 403 #define DEFAULT_NULL_PACKET_COUNT               180000  //20060828.1 Add. 180 seconds
 404
 405 #define MAX_TXVGA_EEPROM        9       //How many word(u16) of EEPROM will be used for TxVGA
 406 #define MAX_RF_PARAMETER        32
 407
 408 typedef struct _TXVGA_FOR_50 {
 409         u8      ChanNo;
 410         u8      TxVgaValue;
 411 } TXVGA_FOR_50;
 412
 413
 414 //=====================================================================
 415 // Device related include
 416 //=====================================================================
 417
 418 #include "linux/wbusb_s.h"
 419 #include "linux/wb35reg_s.h"
 420 #include "linux/wb35tx_s.h"
 421 #include "linux/wb35rx_s.h"
 422
 423
 424 // For Hal using ==================================================================
 425 typedef struct _HW_DATA_T
 426 {
 427         // For compatible with 33
 428         u32     revision;
 429         u32     BB3c_cal; // The value for Tx calibration comes from EEPROM
 430         u32     BB54_cal; // The value for Rx calibration comes from EEPROM
 431
 432
 433         // For surprise remove
 434         u32     SurpriseRemove; // 0: Normal 1: Surprise remove
 435         u8      InitialResource;
 436         u8      IsKeyPreSet;
 437         u8      CalOneTime; // 20060630.1
 438
 439         u8      VCO_trim;
 440
 441         // For Fix 1'st DMA bug
 442         u32     FragCount;
 443         u32     DMAFix; //V1_DMA_FIX The variable can be removed if driver want to save mem space for V2.
 444
 445         //=======================================================================================
 446         // For USB driver, hal need more variables. Due to
 447         //      1. NDIS-WDM operation
 448         //      2. The SME, MLME and OLD MDS need Adapter structure, but the driver under HAL doesn't
 449         //              have that parameter when receiving and indicating packet.
 450         //              The MDS must input the Adapter pointer as the second parameter of hal_init_hardware.
 451         //              The function usage is different than PCI driver.
 452         //=======================================================================================
 453         void* Adapter;
 454
 455         //===============================================
 456         // Definition for MAC address
 457         //===============================================
 458         u8              PermanentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are stored in EEPROM.  + 2 to 8-byte alignment
 459         u8              CurrentMacAddress[ETH_LENGTH_OF_ADDRESS + 2]; // The Enthernet addr that are in used.  + 2 to 8-byte alignment
 460
 461         //=====================================================================
 462         // Definition for 802.11
 463         //=====================================================================
 464         PUCHAR  bssid_pointer; // Used by hal_get_bssid for return value
 465         u8      bssid[8];// Only 6 byte will be used. 8 byte is required for read buffer
 466         u8      ssid[32];// maximum ssid length is 32 byte
 467
 468         u16     AID;
 469         u8      ssid_length;
 470         u8      Channel;
 471
 472         u16     ListenInterval;
 473         u16     CapabilityInformation;
 474
 475         u16     BeaconPeriod;
 476         u16     ProbeDelay;
 477
 478         u8      bss_type;// 0: IBSS_NET or 1:ESS_NET
 479         u8      preamble;// 0: short preamble, 1: long preamble
 480         u8      slot_time_select;// 9 or 20 value
 481         u8      phy_type;// Phy select
 482
 483         u32     phy_para[MAX_RF_PARAMETER];
 484         u32     phy_number;
 485
 486         u32     CurrentRadioSw; // 20060320.2 0:On 1:Off
 487         u32     CurrentRadioHw; // 20060825 0:On 1:Off
 488
 489         PUCHAR  power_save_point;  // Used by hal_get_power_save_mode for return value
 490         u8      cwmin;
 491         u8      desired_power_save;
 492         u8      dtim;// Is running dtim
 493         u8      mapping_key_replace_index;//In Key table, the next index be replaced 931130.4.r
 494
 495         u16     MaxReceiveLifeTime;
 496         u16     FragmentThreshold;
 497         u16     FragmentThreshold_tmp;
 498         u16     cwmax;
 499
 500         u8      Key_slot[MAX_KEY_TABLE][8]; //Ownership record for key slot. For Alignment
 501         u32     Key_content[MAX_KEY_TABLE][12]; // 10DW for each entry + 2 for burst command( Off and On valid bit)
 502         u8      CurrentDefaultKeyIndex;
 503         u32     CurrentDefaultKeyLength;
 504
 505         //========================================================================
 506         // Variable for each module
 507         //========================================================================
 508         WBUSB           WbUsb; // Need WbUsb.h
 509         WB35REG         Wb35Reg; // Need Wb35Reg.h
 510         WB35TX          Wb35Tx; // Need Wb35Tx.h
 511         WB35RX          Wb35Rx; // Need Wb35Rx.h
 512
 513         OS_TIMER        LEDTimer;// For LED
 514
 515         u32             LEDpoint;// For LED
 516
 517     u32         dto_tx_retry_count;         // LA20040210_DTO kevin
 518     u32         dto_tx_frag_count;          // LA20040210_DTO kevin
 519     u32         rx_ok_count[13];    // index=0: total rx ok
 520     //u32         rx_ok_bytes[13];    // index=0, total rx ok bytes
 521     u32         rx_err_count[13];   // index=0: total rx err
 522
 523         //for Tx debug
 524         u32                     tx_TBTT_start_count;
 525         u32                     tx_ETR_count;
 526         u32                     tx_WepOn_false_count;
 527         u32                     tx_Null_key_count;
 528         u32                     tx_retry_count[8];
 529
 530         u8              PowerIndexFromEEPROM; // For 2412MHz
 531         u8              power_index;
 532         u8              IsWaitJoinComplete;     // TRUE: set join request
 533         u8              band;
 534
 535         u16             SoftwareSet;
 536         u16             Reserved_s;
 537
 538         u32             IsInitOK; // 0: Driver starting   1: Driver init OK
 539
 540         // For Phy calibration
 541     s32         iq_rsdl_gain_tx_d2;
 542     s32         iq_rsdl_phase_tx_d2;
 543         u32             txvga_setting_for_cal; // 20060703.1 Add
 544
 545         u8              TxVgaSettingInEEPROM[ (((MAX_TXVGA_EEPROM*2)+3) & ~0x03) ]; // 20060621 For backup EEPROM value
 546         u8              TxVgaFor24[16]; // Max is 14, 2 for alignment
 547         TXVGA_FOR_50    TxVgaFor50[36]; // 35 channels in 5G. 35x2 = 70 byte. 2 for alignments
 548
 549         u16             Scan_Interval;
 550         u16             RESERVED6;
 551
 552         // LED control
 553         u32             LED_control;
 554                 // LED_control 4 byte: Gray_Led_1[3]            Gray_Led_0[2]           Led[1]                  Led[0]
 555                 // Gray_Led
 556                 //              For Led gray setting
 557                 // Led
 558                 //              0: normal control, LED behavior will decide by EEPROM setting
 559                 //              1: Turn off specific LED
 560                 //              2: Always on specific LED
 561                 //              3: slow blinking specific LED
 562                 //              4: fast blinking specific LED
 563                 //              5: WPS led control is set. Led0 is Red, Led1 id Green
 564                 //                      Led[1] is parameter for WPS LED mode
 565                 //                               // 1:InProgress  2: Error 3: Session overlap 4: Success 20061108 control
 566
 567         u32             LED_LinkOn;             //Turn LED on control
 568         u32             LED_Scanning;   // Let LED in scan process control
 569         u32             LED_Blinking; // Temp variable for shining
 570         u32             RxByteCountLast;
 571         u32             TxByteCountLast;
 572
 573         s32             SurpriseRemoveCount;
 574
 575         // For global timer
 576         u32             time_count;//TICK_TIME_100ms 1 = 100ms
 577
 578         // For error recover
 579         u32             HwStop;
 580
 581         // 20060828.1 for avoid AP disconnect
 582         u32             NullPacketCount;
 583
 584 } hw_data_t, *phw_data_t;
 585
 586 // The mapping of Rx and Tx descriptor field
 587 typedef struct _HAL_RATE
 588 {
 589         // DSSS
 590         u32     RESERVED_0;
 591         u32   NumRate2MS;
 592         u32   NumRate55MS;
 593         u32   NumRate11MS;
 594
 595         u32     RESERVED_1[4];
 596
 597         u32   NumRate1M;
 598         u32   NumRate2ML;
 599         u32   NumRate55ML;
 600         u32   NumRate11ML;
 601
 602         u32     RESERVED_2[4];
 603
 604         // OFDM
 605         u32   NumRate6M;
 606         u32   NumRate9M;
 607         u32   NumRate12M;
 608         u32   NumRate18M;
 609         u32   NumRate24M;
 610         u32   NumRate36M;
 611         u32   NumRate48M;
 612         u32   NumRate54M;
 613 } HAL_RATE, *PHAL_RATE;
 614
 615