drivers/staging/gma500/psb_drv.c

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX., USA.
   5  * All Rights Reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  **************************************************************************/
  21
  22 #include <drm/drmP.h>
  23 #include <drm/drm.h>
  24 #include "psb_drm.h"
  25 #include "psb_drv.h"
  26 #include "psb_fb.h"
  27 #include "psb_reg.h"
  28 #include "psb_intel_reg.h"
  29 #include "psb_intel_bios.h"
  30 #include <drm/drm_pciids.h>
  31 #include "psb_powermgmt.h"
  32 #include <linux/cpu.h>
  33 #include <linux/notifier.h>
  34 #include <linux/spinlock.h>
  35 #include <linux/pm_runtime.h>
  36 #include <acpi/video.h>
  37
  38 static int drm_psb_trap_pagefaults;
  39
  40 int drm_psb_no_fb;
  41
  42 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
  43
  44 MODULE_PARM_DESC(no_fb, "Disable FBdev");
  45 MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
  46 module_param_named(no_fb, drm_psb_no_fb, int, 0600);
  47 module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
  48
  49
  50 static DEFINE_PCI_DEVICE_TABLE(pciidlist) = {
  51         { 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
  52         { 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
  53         { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  54         { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  55         { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  56         { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  57         { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  58         { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  59         { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  60         { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
  61         { 0, 0, 0}
  62 };
  63 MODULE_DEVICE_TABLE(pci, pciidlist);
  64
  65 /*
  66  * Standard IOCTLs.
  67  */
  68
  69 #define DRM_IOCTL_PSB_KMS_OFF   \
  70                 DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
  71 #define DRM_IOCTL_PSB_KMS_ON    \
  72                 DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
  73 #define DRM_IOCTL_PSB_SIZES     \
  74                 DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
  75                         struct drm_psb_sizes_arg)
  76 #define DRM_IOCTL_PSB_FUSE_REG  \
  77                 DRM_IOWR(DRM_PSB_FUSE_REG + DRM_COMMAND_BASE, uint32_t)
  78 #define DRM_IOCTL_PSB_DC_STATE  \
  79                 DRM_IOW(DRM_PSB_DC_STATE + DRM_COMMAND_BASE, \
  80                         struct drm_psb_dc_state_arg)
  81 #define DRM_IOCTL_PSB_ADB       \
  82                 DRM_IOWR(DRM_PSB_ADB + DRM_COMMAND_BASE, uint32_t)
  83 #define DRM_IOCTL_PSB_MODE_OPERATION    \
  84                 DRM_IOWR(DRM_PSB_MODE_OPERATION + DRM_COMMAND_BASE, \
  85                          struct drm_psb_mode_operation_arg)
  86 #define DRM_IOCTL_PSB_STOLEN_MEMORY     \
  87                 DRM_IOWR(DRM_PSB_STOLEN_MEMORY + DRM_COMMAND_BASE, \
  88                          struct drm_psb_stolen_memory_arg)
  89 #define DRM_IOCTL_PSB_REGISTER_RW       \
  90                 DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
  91                          struct drm_psb_register_rw_arg)
  92 #define DRM_IOCTL_PSB_DPST      \
  93                 DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
  94                          uint32_t)
  95 #define DRM_IOCTL_PSB_GAMMA     \
  96                 DRM_IOWR(DRM_PSB_GAMMA + DRM_COMMAND_BASE, \
  97                          struct drm_psb_dpst_lut_arg)
  98 #define DRM_IOCTL_PSB_DPST_BL   \
  99                 DRM_IOWR(DRM_PSB_DPST_BL + DRM_COMMAND_BASE, \
 100                          uint32_t)
 101 #define DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID     \
 102                 DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
 103                          struct drm_psb_get_pipe_from_crtc_id_arg)
 104
 105 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
 106                            struct drm_file *file_priv);
 107 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
 108                               struct drm_file *file_priv);
 109 static int psb_adb_ioctl(struct drm_device *dev, void *data,
 110                          struct drm_file *file_priv);
 111 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
 112                                     struct drm_file *file_priv);
 113 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
 114                                    struct drm_file *file_priv);
 115 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
 116                                  struct drm_file *file_priv);
 117 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
 118                           struct drm_file *file_priv);
 119 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
 120                            struct drm_file *file_priv);
 121 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
 122                              struct drm_file *file_priv);
 123
 124 #define PSB_IOCTL_DEF(ioctl, func, flags) \
 125         [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func}
 126
 127 static struct drm_ioctl_desc psb_ioctls[] = {
 128         PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_OFF, psbfb_kms_off_ioctl,
 129                       DRM_ROOT_ONLY),
 130         PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON,
 131                         psbfb_kms_on_ioctl,
 132                         DRM_ROOT_ONLY),
 133         PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
 134         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
 135         PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
 136         PSB_IOCTL_DEF(DRM_IOCTL_PSB_MODE_OPERATION, psb_mode_operation_ioctl,
 137                       DRM_AUTH),
 138         PSB_IOCTL_DEF(DRM_IOCTL_PSB_STOLEN_MEMORY, psb_stolen_memory_ioctl,
 139                       DRM_AUTH),
 140         PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
 141                       DRM_AUTH),
 142         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
 143         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
 144         PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
 145         PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
 146                                         psb_intel_get_pipe_from_crtc_id, 0),
 147
 148 };
 149
 150 static void psb_lastclose(struct drm_device *dev)
 151 {
 152         return;
 153 }
 154
 155 static void psb_do_takedown(struct drm_device *dev)
 156 {
 157         /* FIXME: do we need to clean up the gtt here ? */
 158 }
 159
 160 void mrst_get_fuse_settings(struct drm_device *dev)
 161 {
 162         struct drm_psb_private *dev_priv = dev->dev_private;
 163         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 164         uint32_t fuse_value = 0;
 165         uint32_t fuse_value_tmp = 0;
 166
 167 #define FB_REG06 0xD0810600
 168 #define FB_MIPI_DISABLE  (1 << 11)
 169 #define FB_REG09 0xD0810900
 170 #define FB_REG09 0xD0810900
 171 #define FB_SKU_MASK  0x7000
 172 #define FB_SKU_SHIFT 12
 173 #define FB_SKU_100 0
 174 #define FB_SKU_100L 1
 175 #define FB_SKU_83 2
 176         pci_write_config_dword(pci_root, 0xD0, FB_REG06);
 177         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
 178
 179         dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
 180
 181         DRM_INFO("internal display is %s\n",
 182                  dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
 183
 184          /*prevent Runtime suspend at start*/
 185          if (dev_priv->iLVDS_enable) {
 186                 dev_priv->is_lvds_on = true;
 187                 dev_priv->is_mipi_on = false;
 188         } else {
 189                 dev_priv->is_mipi_on = true;
 190                 dev_priv->is_lvds_on = false;
 191         }
 192
 193         dev_priv->video_device_fuse = fuse_value;
 194
 195         pci_write_config_dword(pci_root, 0xD0, FB_REG09);
 196         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
 197
 198         DRM_INFO("SKU values is 0x%x.\n", fuse_value);
 199         fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
 200
 201         dev_priv->fuse_reg_value = fuse_value;
 202
 203         switch (fuse_value_tmp) {
 204         case FB_SKU_100:
 205                 dev_priv->core_freq = 200;
 206                 break;
 207         case FB_SKU_100L:
 208                 dev_priv->core_freq = 100;
 209                 break;
 210         case FB_SKU_83:
 211                 dev_priv->core_freq = 166;
 212                 break;
 213         default:
 214                 dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
 215                                                                 fuse_value_tmp);
 216                 dev_priv->core_freq = 0;
 217         }
 218         DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
 219         pci_dev_put(pci_root);
 220 }
 221
 222 void mid_get_pci_revID(struct drm_psb_private *dev_priv)
 223 {
 224         uint32_t platform_rev_id = 0;
 225         struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
 226
 227         /*get the revison ID, B0:D2:F0;0x08 */
 228         pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
 229         dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
 230         pci_dev_put(pci_gfx_root);
 231         dev_info(dev_priv->dev->dev, "platform_rev_id is %x\n",
 232                                         dev_priv->platform_rev_id);
 233 }
 234
 235 void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
 236 {
 237         struct mrst_vbt *vbt = &dev_priv->vbt_data;
 238         u32 platform_config_address;
 239         u16 new_size;
 240         u8 *vbt_virtual;
 241         u8 bpi;
 242         u8 number_desc = 0;
 243         struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
 244         struct gct_r10_timing_info ti;
 245         void *pGCT;
 246         struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
 247
 248         /*get the address of the platform config vbt, B0:D2:F0;0xFC */
 249         pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
 250         pci_dev_put(pci_gfx_root);
 251         DRM_INFO("drm platform config address is %x\n",
 252                         platform_config_address);
 253
 254         /* check for platform config address == 0. */
 255         /* this means fw doesn't support vbt */
 256
 257         if (platform_config_address == 0) {
 258                 vbt->size = 0;
 259                 return;
 260         }
 261
 262         /* get the virtual address of the vbt */
 263         vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
 264
 265         memcpy(vbt, vbt_virtual, sizeof(*vbt));
 266         iounmap(vbt_virtual); /* Free virtual address space */
 267
 268         printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
 269
 270         switch (vbt->revision) {
 271         case 0:
 272                 vbt->mrst_gct = NULL;
 273                 vbt->mrst_gct = \
 274                         ioremap(platform_config_address + sizeof(*vbt) - 4,
 275                                         vbt->size - sizeof(*vbt) + 4);
 276                 pGCT = vbt->mrst_gct;
 277                 bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
 278                 dev_priv->gct_data.bpi = bpi;
 279                 dev_priv->gct_data.pt =
 280                         ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
 281                 memcpy(&dev_priv->gct_data.DTD,
 282                         &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
 283                                 sizeof(struct mrst_timing_info));
 284                 dev_priv->gct_data.Panel_Port_Control =
 285                   ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
 286                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 287                         ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
 288                 break;
 289         case 1:
 290                 vbt->mrst_gct = NULL;
 291                 vbt->mrst_gct = \
 292                         ioremap(platform_config_address + sizeof(*vbt) - 4,
 293                                         vbt->size - sizeof(*vbt) + 4);
 294                 pGCT = vbt->mrst_gct;
 295                 bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
 296                 dev_priv->gct_data.bpi = bpi;
 297                 dev_priv->gct_data.pt =
 298                         ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
 299                 memcpy(&dev_priv->gct_data.DTD,
 300                         &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
 301                                 sizeof(struct mrst_timing_info));
 302                 dev_priv->gct_data.Panel_Port_Control =
 303                   ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
 304                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 305                         ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
 306                 break;
 307         case 0x10:
 308                 /*header definition changed from rev 01 (v2) to rev 10h. */
 309                 /*so, some values have changed location*/
 310                 new_size = vbt->checksum; /*checksum contains lo size byte*/
 311                 /*LSB of mrst_gct contains hi size byte*/
 312                 new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
 313
 314                 vbt->checksum = vbt->size; /*size contains the checksum*/
 315                 if (new_size > 0xff)
 316                         vbt->size = 0xff; /*restrict size to 255*/
 317                 else
 318                         vbt->size = new_size;
 319
 320                 /* number of descriptors defined in the GCT */
 321                 number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
 322                 bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
 323                 vbt->mrst_gct = NULL;
 324                 vbt->mrst_gct = \
 325                         ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
 326                                 GCT_R10_DISPLAY_DESC_SIZE * number_desc);
 327                 pGCT = vbt->mrst_gct;
 328                 pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
 329                 dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
 330
 331                 /*copy the GCT display timings into a temp structure*/
 332                 memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
 333
 334                 /*now copy the temp struct into the dev_priv->gct_data*/
 335                 dp_ti->pixel_clock = ti.pixel_clock;
 336                 dp_ti->hactive_hi = ti.hactive_hi;
 337                 dp_ti->hactive_lo = ti.hactive_lo;
 338                 dp_ti->hblank_hi = ti.hblank_hi;
 339                 dp_ti->hblank_lo = ti.hblank_lo;
 340                 dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
 341                 dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
 342                 dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
 343                 dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
 344                 dp_ti->vactive_hi = ti.vactive_hi;
 345                 dp_ti->vactive_lo = ti.vactive_lo;
 346                 dp_ti->vblank_hi = ti.vblank_hi;
 347                 dp_ti->vblank_lo = ti.vblank_lo;
 348                 dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
 349                 dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
 350                 dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
 351                 dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
 352
 353                 /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
 354                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 355                                                         *((u8 *)pGCT + 0x0d);
 356                 dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
 357                                                 (*((u8 *)pGCT + 0x0e)) << 8;
 358                 break;
 359         default:
 360                 printk(KERN_ERR "Unknown revision of GCT!\n");
 361                 vbt->size = 0;
 362         }
 363 }
 364
 365 static void psb_get_core_freq(struct drm_device *dev)
 366 {
 367         uint32_t clock;
 368         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 369         struct drm_psb_private *dev_priv = dev->dev_private;
 370
 371         /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
 372         /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
 373
 374         pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
 375         pci_read_config_dword(pci_root, 0xD4, &clock);
 376         pci_dev_put(pci_root);
 377
 378         switch (clock & 0x07) {
 379         case 0:
 380                 dev_priv->core_freq = 100;
 381                 break;
 382         case 1:
 383                 dev_priv->core_freq = 133;
 384                 break;
 385         case 2:
 386                 dev_priv->core_freq = 150;
 387                 break;
 388         case 3:
 389                 dev_priv->core_freq = 178;
 390                 break;
 391         case 4:
 392                 dev_priv->core_freq = 200;
 393                 break;
 394         case 5:
 395         case 6:
 396         case 7:
 397                 dev_priv->core_freq = 266;
 398         default:
 399                 dev_priv->core_freq = 0;
 400         }
 401 }
 402
 403 static int psb_do_init(struct drm_device *dev)
 404 {
 405         struct drm_psb_private *dev_priv =
 406             (struct drm_psb_private *) dev->dev_private;
 407         struct psb_gtt *pg = dev_priv->pg;
 408
 409         uint32_t stolen_gtt;
 410
 411         int ret = -ENOMEM;
 412
 413         if (pg->mmu_gatt_start & 0x0FFFFFFF) {
 414                 dev_err(dev->dev, "Gatt must be 256M aligned. This is a bug.\n");
 415                 ret = -EINVAL;
 416                 goto out_err;
 417         }
 418
 419
 420         stolen_gtt = (pg->stolen_size >> PAGE_SHIFT) * 4;
 421         stolen_gtt = (stolen_gtt + PAGE_SIZE - 1) >> PAGE_SHIFT;
 422         stolen_gtt =
 423             (stolen_gtt < pg->gtt_pages) ? stolen_gtt : pg->gtt_pages;
 424
 425         dev_priv->gatt_free_offset = pg->mmu_gatt_start +
 426             (stolen_gtt << PAGE_SHIFT) * 1024;
 427
 428         if (1 || drm_debug) {
 429                 uint32_t core_id = PSB_RSGX32(PSB_CR_CORE_ID);
 430                 uint32_t core_rev = PSB_RSGX32(PSB_CR_CORE_REVISION);
 431                 DRM_INFO("SGX core id = 0x%08x\n", core_id);
 432                 DRM_INFO("SGX core rev major = 0x%02x, minor = 0x%02x\n",
 433                          (core_rev & _PSB_CC_REVISION_MAJOR_MASK) >>
 434                          _PSB_CC_REVISION_MAJOR_SHIFT,
 435                          (core_rev & _PSB_CC_REVISION_MINOR_MASK) >>
 436                          _PSB_CC_REVISION_MINOR_SHIFT);
 437                 DRM_INFO
 438                     ("SGX core rev maintenance = 0x%02x, designer = 0x%02x\n",
 439                      (core_rev & _PSB_CC_REVISION_MAINTENANCE_MASK) >>
 440                      _PSB_CC_REVISION_MAINTENANCE_SHIFT,
 441                      (core_rev & _PSB_CC_REVISION_DESIGNER_MASK) >>
 442                      _PSB_CC_REVISION_DESIGNER_SHIFT);
 443         }
 444
 445
 446         spin_lock_init(&dev_priv->irqmask_lock);
 447
 448         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
 449         PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK1);
 450         PSB_RSGX32(PSB_CR_BIF_BANK1);
 451         PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
 452                                                         PSB_CR_BIF_CTRL);
 453         psb_spank(dev_priv);
 454
 455         /* mmu_gatt ?? */
 456         PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
 457         return 0;
 458 out_err:
 459         psb_do_takedown(dev);
 460         return ret;
 461 }
 462
 463 static int psb_driver_unload(struct drm_device *dev)
 464 {
 465         struct drm_psb_private *dev_priv =
 466             (struct drm_psb_private *) dev->dev_private;
 467
 468         /* Kill vblank etc here */
 469
 470         psb_backlight_exit(); /*writes minimum value to backlight HW reg */
 471
 472         if (drm_psb_no_fb == 0)
 473                 psb_modeset_cleanup(dev);
 474
 475         if (dev_priv) {
 476                 psb_lid_timer_takedown(dev_priv);
 477
 478                 psb_do_takedown(dev);
 479
 480
 481                 if (dev_priv->pf_pd) {
 482                         psb_mmu_free_pagedir(dev_priv->pf_pd);
 483                         dev_priv->pf_pd = NULL;
 484                 }
 485                 if (dev_priv->mmu) {
 486                         struct psb_gtt *pg = dev_priv->pg;
 487
 488                         down_read(&pg->sem);
 489                         psb_mmu_remove_pfn_sequence(
 490                                 psb_mmu_get_default_pd
 491                                 (dev_priv->mmu),
 492                                 pg->mmu_gatt_start,
 493                                 dev_priv->vram_stolen_size >> PAGE_SHIFT);
 494                         up_read(&pg->sem);
 495                         psb_mmu_driver_takedown(dev_priv->mmu);
 496                         dev_priv->mmu = NULL;
 497                 }
 498                 psb_gtt_takedown(dev);
 499                 if (dev_priv->scratch_page) {
 500                         __free_page(dev_priv->scratch_page);
 501                         dev_priv->scratch_page = NULL;
 502                 }
 503                 if (dev_priv->vdc_reg) {
 504                         iounmap(dev_priv->vdc_reg);
 505                         dev_priv->vdc_reg = NULL;
 506                 }
 507                 if (dev_priv->sgx_reg) {
 508                         iounmap(dev_priv->sgx_reg);
 509                         dev_priv->sgx_reg = NULL;
 510                 }
 511
 512                 kfree(dev_priv);
 513                 dev->dev_private = NULL;
 514
 515                 /*destroy VBT data*/
 516                 psb_intel_destroy_bios(dev);
 517         }
 518
 519         gma_power_uninit(dev);
 520
 521         return 0;
 522 }
 523
 524
 525 static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
 526 {
 527         struct drm_psb_private *dev_priv;
 528         unsigned long resource_start;
 529         struct psb_gtt *pg;
 530         unsigned long irqflags;
 531         int ret = -ENOMEM;
 532         uint32_t tt_pages;
 533         struct drm_connector *connector;
 534         struct psb_intel_output *psb_intel_output;
 535
 536         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 537         if (dev_priv == NULL)
 538                 return -ENOMEM;
 539
 540         if (IS_MRST(dev))
 541                 dev_priv->num_pipe = 1;
 542         else
 543                 dev_priv->num_pipe = 2;
 544
 545         dev_priv->dev = dev;
 546
 547         dev->dev_private = (void *) dev_priv;
 548         dev_priv->chipset = chipset;
 549
 550         resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
 551
 552         dev_priv->vdc_reg =
 553             ioremap(resource_start + PSB_VDC_OFFSET, PSB_VDC_SIZE);
 554         if (!dev_priv->vdc_reg)
 555                 goto out_err;
 556
 557         if (IS_MRST(dev))
 558                 dev_priv->sgx_reg = ioremap(resource_start + MRST_SGX_OFFSET,
 559                                                         PSB_SGX_SIZE);
 560         else
 561                 dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
 562                                                         PSB_SGX_SIZE);
 563
 564         if (!dev_priv->sgx_reg)
 565                 goto out_err;
 566
 567         if (IS_MRST(dev)) {
 568                 mrst_get_fuse_settings(dev);
 569                 mrst_get_vbt_data(dev_priv);
 570                 mid_get_pci_revID(dev_priv);
 571         } else {
 572                 psb_get_core_freq(dev);
 573                 psb_intel_opregion_init(dev);
 574                 psb_intel_init_bios(dev);
 575         }
 576
 577         /* Init OSPM support */
 578         gma_power_init(dev);
 579
 580         ret = -ENOMEM;
 581
 582         dev_priv->scratch_page = alloc_page(GFP_DMA32 | __GFP_ZERO);
 583         if (!dev_priv->scratch_page)
 584                 goto out_err;
 585
 586         set_pages_uc(dev_priv->scratch_page, 1);
 587
 588         ret = psb_gtt_init(dev, 0);
 589         if (ret)
 590                 goto out_err;
 591
 592         dev_priv->mmu = psb_mmu_driver_init((void *)0,
 593                                         drm_psb_trap_pagefaults, 0,
 594                                         dev_priv);
 595         if (!dev_priv->mmu)
 596                 goto out_err;
 597
 598         pg = dev_priv->pg;
 599
 600         tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
 601                 (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
 602
 603
 604         dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
 605         if (!dev_priv->pf_pd)
 606                 goto out_err;
 607
 608         psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
 609         psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
 610
 611         ret = psb_do_init(dev);
 612         if (ret)
 613                 return ret;
 614
 615         PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
 616         PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
 617
 618 /*      igd_opregion_init(&dev_priv->opregion_dev); */
 619         acpi_video_register();
 620         if (dev_priv->lid_state)
 621                 psb_lid_timer_init(dev_priv);
 622
 623         ret = drm_vblank_init(dev, dev_priv->num_pipe);
 624         if (ret)
 625                 goto out_err;
 626
 627         /*
 628          * Install interrupt handlers prior to powering off SGX or else we will
 629          * crash.
 630          */
 631         dev_priv->vdc_irq_mask = 0;
 632         dev_priv->pipestat[0] = 0;
 633         dev_priv->pipestat[1] = 0;
 634         dev_priv->pipestat[2] = 0;
 635         spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
 636         PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
 637         PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
 638         PSB_WVDC32(0xFFFFFFFF, PSB_INT_MASK_R);
 639         spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
 640         if (drm_core_check_feature(dev, DRIVER_MODESET))
 641                 drm_irq_install(dev);
 642
 643         dev->vblank_disable_allowed = 1;
 644
 645         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 646
 647         dev->driver->get_vblank_counter = psb_get_vblank_counter;
 648
 649         if (drm_psb_no_fb == 0) {
 650                 psb_modeset_init(dev);
 651                 psb_fbdev_init(dev);
 652                 drm_kms_helper_poll_init(dev);
 653         }
 654
 655         /* Only add backlight support if we have LVDS output */
 656         list_for_each_entry(connector, &dev->mode_config.connector_list,
 657                             head) {
 658                 psb_intel_output = to_psb_intel_output(connector);
 659
 660                 switch (psb_intel_output->type) {
 661                 case INTEL_OUTPUT_LVDS:
 662                         ret = psb_backlight_init(dev);
 663                         break;
 664                 }
 665         }
 666
 667         if (ret)
 668                 return ret;
 669 #if 0
 670         /*enable runtime pm at last*/
 671         pm_runtime_enable(&dev->pdev->dev);
 672         pm_runtime_set_active(&dev->pdev->dev);
 673 #endif
 674         /*Intel drm driver load is done, continue doing pvr load*/
 675         return 0;
 676 out_err:
 677         psb_driver_unload(dev);
 678         return ret;
 679 }
 680
 681 int psb_driver_device_is_agp(struct drm_device *dev)
 682 {
 683         return 0;
 684 }
 685
 686
 687 static int psb_sizes_ioctl(struct drm_device *dev, void *data,
 688                            struct drm_file *file_priv)
 689 {
 690         struct drm_psb_private *dev_priv = psb_priv(dev);
 691         struct drm_psb_sizes_arg *arg =
 692                 (struct drm_psb_sizes_arg *) data;
 693
 694         *arg = dev_priv->sizes;
 695         return 0;
 696 }
 697
 698 static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
 699                                 struct drm_file *file_priv)
 700 {
 701         uint32_t flags;
 702         uint32_t obj_id;
 703         struct drm_mode_object *obj;
 704         struct drm_connector *connector;
 705         struct drm_crtc *crtc;
 706         struct drm_psb_dc_state_arg *arg =
 707                 (struct drm_psb_dc_state_arg *)data;
 708
 709         flags = arg->flags;
 710         obj_id = arg->obj_id;
 711
 712         if (flags & PSB_DC_CRTC_MASK) {
 713                 obj = drm_mode_object_find(dev, obj_id,
 714                                 DRM_MODE_OBJECT_CRTC);
 715                 if (!obj) {
 716                         dev_dbg(dev->dev, "Invalid CRTC object.\n");
 717                         return -EINVAL;
 718                 }
 719
 720                 crtc = obj_to_crtc(obj);
 721
 722                 mutex_lock(&dev->mode_config.mutex);
 723                 if (drm_helper_crtc_in_use(crtc)) {
 724                         if (flags & PSB_DC_CRTC_SAVE)
 725                                 crtc->funcs->save(crtc);
 726                         else
 727                                 crtc->funcs->restore(crtc);
 728                 }
 729                 mutex_unlock(&dev->mode_config.mutex);
 730
 731                 return 0;
 732         } else if (flags & PSB_DC_OUTPUT_MASK) {
 733                 obj = drm_mode_object_find(dev, obj_id,
 734                                 DRM_MODE_OBJECT_CONNECTOR);
 735                 if (!obj) {
 736                         dev_dbg(dev->dev, "Invalid connector id.\n");
 737                         return -EINVAL;
 738                 }
 739
 740                 connector = obj_to_connector(obj);
 741                 if (flags & PSB_DC_OUTPUT_SAVE)
 742                         connector->funcs->save(connector);
 743                 else
 744                         connector->funcs->restore(connector);
 745
 746                 return 0;
 747         }
 748         return -EINVAL;
 749 }
 750
 751 static int psb_dpst_bl_ioctl(struct drm_device *dev, void *data,
 752                        struct drm_file *file_priv)
 753 {
 754         struct drm_psb_private *dev_priv = psb_priv(dev);
 755         uint32_t *arg = data;
 756         struct backlight_device bd;
 757         dev_priv->blc_adj2 = *arg;
 758
 759 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 760         bd.props.brightness = psb_get_brightness(&bd);
 761         psb_set_brightness(&bd);
 762 #endif
 763         return 0;
 764 }
 765
 766 static int psb_adb_ioctl(struct drm_device *dev, void *data,
 767                         struct drm_file *file_priv)
 768 {
 769         struct drm_psb_private *dev_priv = psb_priv(dev);
 770         uint32_t *arg = data;
 771         struct backlight_device bd;
 772         dev_priv->blc_adj1 = *arg;
 773
 774 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 775         bd.props.brightness = psb_get_brightness(&bd);
 776         psb_set_brightness(&bd);
 777 #endif
 778         return 0;
 779 }
 780
 781 /* return the current mode to the dpst module */
 782 static int psb_dpst_ioctl(struct drm_device *dev, void *data,
 783                           struct drm_file *file_priv)
 784 {
 785         struct drm_psb_private *dev_priv = psb_priv(dev);
 786         uint32_t *arg = data;
 787         uint32_t x;
 788         uint32_t y;
 789         uint32_t reg;
 790
 791         if (!gma_power_begin(dev, 0))
 792                 return -EIO;
 793
 794         reg = PSB_RVDC32(PIPEASRC);
 795
 796         gma_power_end(dev);
 797
 798         /* horizontal is the left 16 bits */
 799         x = reg >> 16;
 800         /* vertical is the right 16 bits */
 801         y = reg & 0x0000ffff;
 802
 803         /* the values are the image size minus one */
 804         x++;
 805         y++;
 806
 807         *arg = (x << 16) | y;
 808
 809         return 0;
 810 }
 811 static int psb_gamma_ioctl(struct drm_device *dev, void *data,
 812                            struct drm_file *file_priv)
 813 {
 814         struct drm_psb_dpst_lut_arg *lut_arg = data;
 815         struct drm_mode_object *obj;
 816         struct drm_crtc *crtc;
 817         struct drm_connector *connector;
 818         struct psb_intel_crtc *psb_intel_crtc;
 819         int i = 0;
 820         int32_t obj_id;
 821
 822         obj_id = lut_arg->output_id;
 823         obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_CONNECTOR);
 824         if (!obj) {
 825                 dev_dbg(dev->dev, "Invalid Connector object.\n");
 826                 return -EINVAL;
 827         }
 828
 829         connector = obj_to_connector(obj);
 830         crtc = connector->encoder->crtc;
 831         psb_intel_crtc = to_psb_intel_crtc(crtc);
 832
 833         for (i = 0; i < 256; i++)
 834                 psb_intel_crtc->lut_adj[i] = lut_arg->lut[i];
 835
 836         psb_intel_crtc_load_lut(crtc);
 837
 838         return 0;
 839 }
 840
 841 static int psb_mode_operation_ioctl(struct drm_device *dev, void *data,
 842                                 struct drm_file *file_priv)
 843 {
 844         uint32_t obj_id;
 845         uint16_t op;
 846         struct drm_mode_modeinfo *umode;
 847         struct drm_display_mode *mode = NULL;
 848         struct drm_psb_mode_operation_arg *arg;
 849         struct drm_mode_object *obj;
 850         struct drm_connector *connector;
 851         struct drm_framebuffer *drm_fb;
 852         struct psb_framebuffer *psb_fb;
 853         struct drm_connector_helper_funcs *connector_funcs;
 854         int ret = 0;
 855         int resp = MODE_OK;
 856         struct drm_psb_private *dev_priv = psb_priv(dev);
 857
 858         arg = (struct drm_psb_mode_operation_arg *)data;
 859         obj_id = arg->obj_id;
 860         op = arg->operation;
 861
 862         switch (op) {
 863         case PSB_MODE_OPERATION_SET_DC_BASE:
 864                 obj = drm_mode_object_find(dev, obj_id, DRM_MODE_OBJECT_FB);
 865                 if (!obj) {
 866                         dev_dbg(dev->dev, "Invalid FB id %d\n", obj_id);
 867                         return -EINVAL;
 868                 }
 869
 870                 drm_fb = obj_to_fb(obj);
 871                 psb_fb = to_psb_fb(drm_fb);
 872
 873                 if (gma_power_begin(dev, 0)) {
 874                         REG_WRITE(DSPASURF, psb_fb->gtt->offset);
 875                         REG_READ(DSPASURF);
 876                         gma_power_end(dev);
 877                 } else {
 878                         dev_priv->saveDSPASURF = psb_fb->gtt->offset;
 879                 }
 880
 881                 return 0;
 882         case PSB_MODE_OPERATION_MODE_VALID:
 883                 umode = &arg->mode;
 884
 885                 mutex_lock(&dev->mode_config.mutex);
 886
 887                 obj = drm_mode_object_find(dev, obj_id,
 888                                         DRM_MODE_OBJECT_CONNECTOR);
 889                 if (!obj) {
 890                         ret = -EINVAL;
 891                         goto mode_op_out;
 892                 }
 893
 894                 connector = obj_to_connector(obj);
 895
 896                 mode = drm_mode_create(dev);
 897                 if (!mode) {
 898                         ret = -ENOMEM;
 899                         goto mode_op_out;
 900                 }
 901
 902                 /* drm_crtc_convert_umode(mode, umode); */
 903                 {
 904                         mode->clock = umode->clock;
 905                         mode->hdisplay = umode->hdisplay;
 906                         mode->hsync_start = umode->hsync_start;
 907                         mode->hsync_end = umode->hsync_end;
 908                         mode->htotal = umode->htotal;
 909                         mode->hskew = umode->hskew;
 910                         mode->vdisplay = umode->vdisplay;
 911                         mode->vsync_start = umode->vsync_start;
 912                         mode->vsync_end = umode->vsync_end;
 913                         mode->vtotal = umode->vtotal;
 914                         mode->vscan = umode->vscan;
 915                         mode->vrefresh = umode->vrefresh;
 916                         mode->flags = umode->flags;
 917                         mode->type = umode->type;
 918                         strncpy(mode->name, umode->name, DRM_DISPLAY_MODE_LEN);
 919                         mode->name[DRM_DISPLAY_MODE_LEN-1] = 0;
 920                 }
 921
 922                 connector_funcs = (struct drm_connector_helper_funcs *)
 923                                    connector->helper_private;
 924
 925                 if (connector_funcs->mode_valid) {
 926                         resp = connector_funcs->mode_valid(connector, mode);
 927                         arg->data = (void *)resp;
 928                 }
 929
 930                 /*do some clean up work*/
 931                 if (mode)
 932                         drm_mode_destroy(dev, mode);
 933 mode_op_out:
 934                 mutex_unlock(&dev->mode_config.mutex);
 935                 return ret;
 936
 937         default:
 938                 dev_dbg(dev->dev, "Unsupported psb mode operation\n");
 939                 return -EOPNOTSUPP;
 940         }
 941
 942         return 0;
 943 }
 944
 945 static int psb_stolen_memory_ioctl(struct drm_device *dev, void *data,
 946                                    struct drm_file *file_priv)
 947 {
 948         struct drm_psb_private *dev_priv = psb_priv(dev);
 949         struct drm_psb_stolen_memory_arg *arg = data;
 950
 951         arg->base = dev_priv->stolen_base;
 952         arg->size = dev_priv->vram_stolen_size;
 953
 954         return 0;
 955 }
 956
 957 static int psb_register_rw_ioctl(struct drm_device *dev, void *data,
 958                                  struct drm_file *file_priv)
 959 {
 960         struct drm_psb_private *dev_priv = psb_priv(dev);
 961         struct drm_psb_register_rw_arg *arg = data;
 962         bool usage = arg->b_force_hw_on ? true : false;
 963
 964         if (arg->display_write_mask != 0) {
 965                 if (gma_power_begin(dev, usage)) {
 966                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
 967                                 PSB_WVDC32(arg->display.pfit_controls,
 968                                            PFIT_CONTROL);
 969                         if (arg->display_write_mask &
 970                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 971                                 PSB_WVDC32(arg->display.pfit_autoscale_ratios,
 972                                            PFIT_AUTO_RATIOS);
 973                         if (arg->display_write_mask &
 974                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
 975                                 PSB_WVDC32(
 976                                    arg->display.pfit_programmed_scale_ratios,
 977                                    PFIT_PGM_RATIOS);
 978                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
 979                                 PSB_WVDC32(arg->display.pipeasrc,
 980                                            PIPEASRC);
 981                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
 982                                 PSB_WVDC32(arg->display.pipebsrc,
 983                                            PIPEBSRC);
 984                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
 985                                 PSB_WVDC32(arg->display.vtotal_a,
 986                                            VTOTAL_A);
 987                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
 988                                 PSB_WVDC32(arg->display.vtotal_b,
 989                                            VTOTAL_B);
 990                         gma_power_end(dev);
 991                 } else {
 992                         if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
 993                                 dev_priv->savePFIT_CONTROL =
 994                                                 arg->display.pfit_controls;
 995                         if (arg->display_write_mask &
 996                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
 997                                 dev_priv->savePFIT_AUTO_RATIOS =
 998                                         arg->display.pfit_autoscale_ratios;
 999                         if (arg->display_write_mask &
1000                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1001                                 dev_priv->savePFIT_PGM_RATIOS =
1002                                    arg->display.pfit_programmed_scale_ratios;
1003                         if (arg->display_write_mask & REGRWBITS_PIPEASRC)
1004                                 dev_priv->savePIPEASRC = arg->display.pipeasrc;
1005                         if (arg->display_write_mask & REGRWBITS_PIPEBSRC)
1006                                 dev_priv->savePIPEBSRC = arg->display.pipebsrc;
1007                         if (arg->display_write_mask & REGRWBITS_VTOTAL_A)
1008                                 dev_priv->saveVTOTAL_A = arg->display.vtotal_a;
1009                         if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
1010                                 dev_priv->saveVTOTAL_B = arg->display.vtotal_b;
1011                 }
1012         }
1013
1014         if (arg->display_read_mask != 0) {
1015                 if (gma_power_begin(dev, usage)) {
1016                         if (arg->display_read_mask &
1017                             REGRWBITS_PFIT_CONTROLS)
1018                                 arg->display.pfit_controls =
1019                                                 PSB_RVDC32(PFIT_CONTROL);
1020                         if (arg->display_read_mask &
1021                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1022                                 arg->display.pfit_autoscale_ratios =
1023                                                 PSB_RVDC32(PFIT_AUTO_RATIOS);
1024                         if (arg->display_read_mask &
1025                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1026                                 arg->display.pfit_programmed_scale_ratios =
1027                                                 PSB_RVDC32(PFIT_PGM_RATIOS);
1028                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1029                                 arg->display.pipeasrc = PSB_RVDC32(PIPEASRC);
1030                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1031                                 arg->display.pipebsrc = PSB_RVDC32(PIPEBSRC);
1032                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1033                                 arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
1034                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1035                                 arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
1036                         gma_power_end(dev);
1037                 } else {
1038                         if (arg->display_read_mask &
1039                             REGRWBITS_PFIT_CONTROLS)
1040                                 arg->display.pfit_controls =
1041                                                 dev_priv->savePFIT_CONTROL;
1042                         if (arg->display_read_mask &
1043                             REGRWBITS_PFIT_AUTOSCALE_RATIOS)
1044                                 arg->display.pfit_autoscale_ratios =
1045                                                 dev_priv->savePFIT_AUTO_RATIOS;
1046                         if (arg->display_read_mask &
1047                             REGRWBITS_PFIT_PROGRAMMED_SCALE_RATIOS)
1048                                 arg->display.pfit_programmed_scale_ratios =
1049                                                 dev_priv->savePFIT_PGM_RATIOS;
1050                         if (arg->display_read_mask & REGRWBITS_PIPEASRC)
1051                                 arg->display.pipeasrc = dev_priv->savePIPEASRC;
1052                         if (arg->display_read_mask & REGRWBITS_PIPEBSRC)
1053                                 arg->display.pipebsrc = dev_priv->savePIPEBSRC;
1054                         if (arg->display_read_mask & REGRWBITS_VTOTAL_A)
1055                                 arg->display.vtotal_a = dev_priv->saveVTOTAL_A;
1056                         if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
1057                                 arg->display.vtotal_b = dev_priv->saveVTOTAL_B;
1058                 }
1059         }
1060
1061         if (arg->overlay_write_mask != 0) {
1062                 if (gma_power_begin(dev, usage)) {
1063                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1064                                 PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
1065                                 PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
1066                                 PSB_WVDC32(arg->overlay.OGAMC3, OV_OGAMC3);
1067                                 PSB_WVDC32(arg->overlay.OGAMC2, OV_OGAMC2);
1068                                 PSB_WVDC32(arg->overlay.OGAMC1, OV_OGAMC1);
1069                                 PSB_WVDC32(arg->overlay.OGAMC0, OV_OGAMC0);
1070                         }
1071                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1072                                 PSB_WVDC32(arg->overlay.OGAMC5, OVC_OGAMC5);
1073                                 PSB_WVDC32(arg->overlay.OGAMC4, OVC_OGAMC4);
1074                                 PSB_WVDC32(arg->overlay.OGAMC3, OVC_OGAMC3);
1075                                 PSB_WVDC32(arg->overlay.OGAMC2, OVC_OGAMC2);
1076                                 PSB_WVDC32(arg->overlay.OGAMC1, OVC_OGAMC1);
1077                                 PSB_WVDC32(arg->overlay.OGAMC0, OVC_OGAMC0);
1078                         }
1079
1080                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD) {
1081                                 PSB_WVDC32(arg->overlay.OVADD, OV_OVADD);
1082
1083                                 if (arg->overlay.b_wait_vblank) {
1084                                         /* Wait for 20ms.*/
1085                                         unsigned long vblank_timeout = jiffies
1086                                                                 + HZ/50;
1087                                         uint32_t temp;
1088                                         while (time_before_eq(jiffies,
1089                                                         vblank_timeout)) {
1090                                                 temp = PSB_RVDC32(OV_DOVASTA);
1091                                                 if ((temp & (0x1 << 31)) != 0)
1092                                                         break;
1093                                                 cpu_relax();
1094                                         }
1095                                 }
1096                         }
1097                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD) {
1098                                 PSB_WVDC32(arg->overlay.OVADD, OVC_OVADD);
1099                                 if (arg->overlay.b_wait_vblank) {
1100                                         /* Wait for 20ms.*/
1101                                         unsigned long vblank_timeout =
1102                                                         jiffies + HZ/50;
1103                                         uint32_t temp;
1104                                         while (time_before_eq(jiffies,
1105                                                         vblank_timeout)) {
1106                                                 temp = PSB_RVDC32(OVC_DOVCSTA);
1107                                                 if ((temp & (0x1 << 31)) != 0)
1108                                                         break;
1109                                                 cpu_relax();
1110                                         }
1111                                 }
1112                         }
1113                         gma_power_end(dev);
1114                 } else {
1115                         if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
1116                                 dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
1117                                 dev_priv->saveOV_OGAMC4 = arg->overlay.OGAMC4;
1118                                 dev_priv->saveOV_OGAMC3 = arg->overlay.OGAMC3;
1119                                 dev_priv->saveOV_OGAMC2 = arg->overlay.OGAMC2;
1120                                 dev_priv->saveOV_OGAMC1 = arg->overlay.OGAMC1;
1121                                 dev_priv->saveOV_OGAMC0 = arg->overlay.OGAMC0;
1122                         }
1123                         if (arg->overlay_write_mask & OVC_REGRWBITS_OGAM_ALL) {
1124                                 dev_priv->saveOVC_OGAMC5 = arg->overlay.OGAMC5;
1125                                 dev_priv->saveOVC_OGAMC4 = arg->overlay.OGAMC4;
1126                                 dev_priv->saveOVC_OGAMC3 = arg->overlay.OGAMC3;
1127                                 dev_priv->saveOVC_OGAMC2 = arg->overlay.OGAMC2;
1128                                 dev_priv->saveOVC_OGAMC1 = arg->overlay.OGAMC1;
1129                                 dev_priv->saveOVC_OGAMC0 = arg->overlay.OGAMC0;
1130                         }
1131                         if (arg->overlay_write_mask & OV_REGRWBITS_OVADD)
1132                                 dev_priv->saveOV_OVADD = arg->overlay.OVADD;
1133                         if (arg->overlay_write_mask & OVC_REGRWBITS_OVADD)
1134                                 dev_priv->saveOVC_OVADD = arg->overlay.OVADD;
1135                 }
1136         }
1137
1138         if (arg->overlay_read_mask != 0) {
1139                 if (gma_power_begin(dev, usage)) {
1140                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1141                                 arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
1142                                 arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
1143                                 arg->overlay.OGAMC3 = PSB_RVDC32(OV_OGAMC3);
1144                                 arg->overlay.OGAMC2 = PSB_RVDC32(OV_OGAMC2);
1145                                 arg->overlay.OGAMC1 = PSB_RVDC32(OV_OGAMC1);
1146                                 arg->overlay.OGAMC0 = PSB_RVDC32(OV_OGAMC0);
1147                         }
1148                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1149                                 arg->overlay.OGAMC5 = PSB_RVDC32(OVC_OGAMC5);
1150                                 arg->overlay.OGAMC4 = PSB_RVDC32(OVC_OGAMC4);
1151                                 arg->overlay.OGAMC3 = PSB_RVDC32(OVC_OGAMC3);
1152                                 arg->overlay.OGAMC2 = PSB_RVDC32(OVC_OGAMC2);
1153                                 arg->overlay.OGAMC1 = PSB_RVDC32(OVC_OGAMC1);
1154                                 arg->overlay.OGAMC0 = PSB_RVDC32(OVC_OGAMC0);
1155                         }
1156                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1157                                 arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
1158                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1159                                 arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
1160                         gma_power_end(dev);
1161                 } else {
1162                         if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
1163                                 arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
1164                                 arg->overlay.OGAMC4 = dev_priv->saveOV_OGAMC4;
1165                                 arg->overlay.OGAMC3 = dev_priv->saveOV_OGAMC3;
1166                                 arg->overlay.OGAMC2 = dev_priv->saveOV_OGAMC2;
1167                                 arg->overlay.OGAMC1 = dev_priv->saveOV_OGAMC1;
1168                                 arg->overlay.OGAMC0 = dev_priv->saveOV_OGAMC0;
1169                         }
1170                         if (arg->overlay_read_mask & OVC_REGRWBITS_OGAM_ALL) {
1171                                 arg->overlay.OGAMC5 = dev_priv->saveOVC_OGAMC5;
1172                                 arg->overlay.OGAMC4 = dev_priv->saveOVC_OGAMC4;
1173                                 arg->overlay.OGAMC3 = dev_priv->saveOVC_OGAMC3;
1174                                 arg->overlay.OGAMC2 = dev_priv->saveOVC_OGAMC2;
1175                                 arg->overlay.OGAMC1 = dev_priv->saveOVC_OGAMC1;
1176                                 arg->overlay.OGAMC0 = dev_priv->saveOVC_OGAMC0;
1177                         }
1178                         if (arg->overlay_read_mask & OV_REGRWBITS_OVADD)
1179                                 arg->overlay.OVADD = dev_priv->saveOV_OVADD;
1180                         if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
1181                                 arg->overlay.OVADD = dev_priv->saveOVC_OVADD;
1182                 }
1183         }
1184
1185         if (arg->sprite_enable_mask != 0) {
1186                 if (gma_power_begin(dev, usage)) {
1187                         PSB_WVDC32(0x1F3E, DSPARB);
1188                         PSB_WVDC32(arg->sprite.dspa_control
1189                                         | PSB_RVDC32(DSPACNTR), DSPACNTR);
1190                         PSB_WVDC32(arg->sprite.dspa_key_value, DSPAKEYVAL);
1191                         PSB_WVDC32(arg->sprite.dspa_key_mask, DSPAKEYMASK);
1192                         PSB_WVDC32(PSB_RVDC32(DSPASURF), DSPASURF);
1193                         PSB_RVDC32(DSPASURF);
1194                         PSB_WVDC32(arg->sprite.dspc_control, DSPCCNTR);
1195                         PSB_WVDC32(arg->sprite.dspc_stride, DSPCSTRIDE);
1196                         PSB_WVDC32(arg->sprite.dspc_position, DSPCPOS);
1197                         PSB_WVDC32(arg->sprite.dspc_linear_offset, DSPCLINOFF);
1198                         PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
1199                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1200                         PSB_RVDC32(DSPCSURF);
1201                         gma_power_end(dev);
1202                 }
1203         }
1204
1205         if (arg->sprite_disable_mask != 0) {
1206                 if (gma_power_begin(dev, usage)) {
1207                         PSB_WVDC32(0x3F3E, DSPARB);
1208                         PSB_WVDC32(0x0, DSPCCNTR);
1209                         PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
1210                         PSB_RVDC32(DSPCSURF);
1211                         gma_power_end(dev);
1212                 }
1213         }
1214
1215         if (arg->subpicture_enable_mask != 0) {
1216                 if (gma_power_begin(dev, usage)) {
1217                         uint32_t temp;
1218                         if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
1219                                 temp =  PSB_RVDC32(DSPACNTR);
1220                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1221                                 temp &= ~DISPPLANE_BOTTOM;
1222                                 temp |= DISPPLANE_32BPP;
1223                                 PSB_WVDC32(temp, DSPACNTR);
1224
1225                                 temp =  PSB_RVDC32(DSPABASE);
1226                                 PSB_WVDC32(temp, DSPABASE);
1227                                 PSB_RVDC32(DSPABASE);
1228                                 temp =  PSB_RVDC32(DSPASURF);
1229                                 PSB_WVDC32(temp, DSPASURF);
1230                                 PSB_RVDC32(DSPASURF);
1231                         }
1232                         if (arg->subpicture_enable_mask & REGRWBITS_DSPBCNTR) {
1233                                 temp =  PSB_RVDC32(DSPBCNTR);
1234                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1235                                 temp &= ~DISPPLANE_BOTTOM;
1236                                 temp |= DISPPLANE_32BPP;
1237                                 PSB_WVDC32(temp, DSPBCNTR);
1238
1239                                 temp =  PSB_RVDC32(DSPBBASE);
1240                                 PSB_WVDC32(temp, DSPBBASE);
1241                                 PSB_RVDC32(DSPBBASE);
1242                                 temp =  PSB_RVDC32(DSPBSURF);
1243                                 PSB_WVDC32(temp, DSPBSURF);
1244                                 PSB_RVDC32(DSPBSURF);
1245                         }
1246                         if (arg->subpicture_enable_mask & REGRWBITS_DSPCCNTR) {
1247                                 temp =  PSB_RVDC32(DSPCCNTR);
1248                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1249                                 temp &= ~DISPPLANE_BOTTOM;
1250                                 temp |= DISPPLANE_32BPP;
1251                                 PSB_WVDC32(temp, DSPCCNTR);
1252
1253                                 temp =  PSB_RVDC32(DSPCBASE);
1254                                 PSB_WVDC32(temp, DSPCBASE);
1255                                 PSB_RVDC32(DSPCBASE);
1256                                 temp =  PSB_RVDC32(DSPCSURF);
1257                                 PSB_WVDC32(temp, DSPCSURF);
1258                                 PSB_RVDC32(DSPCSURF);
1259                         }
1260                         gma_power_end(dev);
1261                 }
1262         }
1263
1264         if (arg->subpicture_disable_mask != 0) {
1265                 if (gma_power_begin(dev, usage)) {
1266                         uint32_t temp;
1267                         if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
1268                                 temp =  PSB_RVDC32(DSPACNTR);
1269                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1270                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1271                                 PSB_WVDC32(temp, DSPACNTR);
1272
1273                                 temp =  PSB_RVDC32(DSPABASE);
1274                                 PSB_WVDC32(temp, DSPABASE);
1275                                 PSB_RVDC32(DSPABASE);
1276                                 temp =  PSB_RVDC32(DSPASURF);
1277                                 PSB_WVDC32(temp, DSPASURF);
1278                                 PSB_RVDC32(DSPASURF);
1279                         }
1280                         if (arg->subpicture_disable_mask & REGRWBITS_DSPBCNTR) {
1281                                 temp =  PSB_RVDC32(DSPBCNTR);
1282                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1283                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1284                                 PSB_WVDC32(temp, DSPBCNTR);
1285
1286                                 temp =  PSB_RVDC32(DSPBBASE);
1287                                 PSB_WVDC32(temp, DSPBBASE);
1288                                 PSB_RVDC32(DSPBBASE);
1289                                 temp =  PSB_RVDC32(DSPBSURF);
1290                                 PSB_WVDC32(temp, DSPBSURF);
1291                                 PSB_RVDC32(DSPBSURF);
1292                         }
1293                         if (arg->subpicture_disable_mask & REGRWBITS_DSPCCNTR) {
1294                                 temp =  PSB_RVDC32(DSPCCNTR);
1295                                 temp &= ~DISPPLANE_PIXFORMAT_MASK;
1296                                 temp |= DISPPLANE_32BPP_NO_ALPHA;
1297                                 PSB_WVDC32(temp, DSPCCNTR);
1298
1299                                 temp =  PSB_RVDC32(DSPCBASE);
1300                                 PSB_WVDC32(temp, DSPCBASE);
1301                                 PSB_RVDC32(DSPCBASE);
1302                                 temp =  PSB_RVDC32(DSPCSURF);
1303                                 PSB_WVDC32(temp, DSPCSURF);
1304                                 PSB_RVDC32(DSPCSURF);
1305                         }
1306                         gma_power_end(dev);
1307                 }
1308         }
1309
1310         return 0;
1311 }
1312
1313 static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
1314 {
1315         return 0;
1316 }
1317
1318 static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
1319 {
1320 }
1321
1322 static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
1323                                unsigned long arg)
1324 {
1325         struct drm_file *file_priv = filp->private_data;
1326         struct drm_device *dev = file_priv->minor->dev;
1327         struct drm_psb_private *dev_priv = dev->dev_private;
1328         static unsigned int runtime_allowed;
1329
1330         if (runtime_allowed == 1 && dev_priv->is_lvds_on) {
1331                 runtime_allowed++;
1332                 pm_runtime_allow(&dev->pdev->dev);
1333                 dev_priv->rpm_enabled = 1;
1334         }
1335         return drm_ioctl(filp, cmd, arg);
1336         /* FIXME: do we need to wrap the other side of this */
1337 }
1338
1339
1340 /* When a client dies:
1341  *    - Check for and clean up flipped page state
1342  */
1343 void psb_driver_preclose(struct drm_device *dev, struct drm_file *priv)
1344 {
1345 }
1346
1347 static void psb_remove(struct pci_dev *pdev)
1348 {
1349         struct drm_device *dev = pci_get_drvdata(pdev);
1350         drm_put_dev(dev);
1351 }
1352
1353 static const struct dev_pm_ops psb_pm_ops = {
1354         .runtime_suspend = psb_runtime_suspend,
1355         .runtime_resume = psb_runtime_resume,
1356         .runtime_idle = psb_runtime_idle,
1357 };
1358
1359 static struct vm_operations_struct psb_gem_vm_ops = {
1360         .fault = psb_gem_fault,
1361         .open = drm_gem_vm_open,
1362         .close = drm_gem_vm_close,
1363 };
1364
1365 static struct drm_driver driver = {
1366         .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
1367                            DRIVER_IRQ_VBL | DRIVER_MODESET | DRIVER_GEM ,
1368         .load = psb_driver_load,
1369         .unload = psb_driver_unload,
1370
1371         .ioctls = psb_ioctls,
1372         .num_ioctls = DRM_ARRAY_SIZE(psb_ioctls),
1373         .device_is_agp = psb_driver_device_is_agp,
1374         .irq_preinstall = psb_irq_preinstall,
1375         .irq_postinstall = psb_irq_postinstall,
1376         .irq_uninstall = psb_irq_uninstall,
1377         .irq_handler = psb_irq_handler,
1378         .enable_vblank = psb_enable_vblank,
1379         .disable_vblank = psb_disable_vblank,
1380         .get_vblank_counter = psb_get_vblank_counter,
1381         .lastclose = psb_lastclose,
1382         .open = psb_driver_open,
1383         .preclose = psb_driver_preclose,
1384         .postclose = psb_driver_close,
1385         .reclaim_buffers = drm_core_reclaim_buffers,
1386
1387         .gem_init_object = psb_gem_init_object,
1388         .gem_free_object = psb_gem_free_object,
1389         .gem_vm_ops = &psb_gem_vm_ops,
1390         .dumb_create = psb_gem_dumb_create,
1391         .dumb_map_offset = psb_gem_dumb_map_gtt,
1392         .dumb_destroy = psb_gem_dumb_destroy,
1393
1394         .fops = {
1395                  .owner = THIS_MODULE,
1396                  .open = drm_open,
1397                  .release = drm_release,
1398                  .unlocked_ioctl = psb_unlocked_ioctl,
1399                  .mmap = drm_gem_mmap,
1400                  .poll = drm_poll,
1401                  .fasync = drm_fasync,
1402                  .read = drm_read,
1403          },
1404         .name = DRIVER_NAME,
1405         .desc = DRIVER_DESC,
1406         .date = PSB_DRM_DRIVER_DATE,
1407         .major = PSB_DRM_DRIVER_MAJOR,
1408         .minor = PSB_DRM_DRIVER_MINOR,
1409         .patchlevel = PSB_DRM_DRIVER_PATCHLEVEL
1410 };
1411
1412 static struct pci_driver psb_pci_driver = {
1413         .name = DRIVER_NAME,
1414         .id_table = pciidlist,
1415         .resume = gma_power_resume,
1416         .suspend = gma_power_suspend,
1417         .probe = psb_probe,
1418         .remove = psb_remove,
1419 #ifdef CONFIG_PM
1420         .driver.pm = &psb_pm_ops,
1421 #endif
1422 };
1423
1424 static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1425 {
1426         /* MLD Added this from Inaky's patch */
1427         if (pci_enable_msi(pdev))
1428                 dev_warn(&pdev->dev, "Enable MSI failed!\n");
1429         return drm_get_pci_dev(pdev, ent, &driver);
1430 }
1431
1432 static int __init psb_init(void)
1433 {
1434         return drm_pci_init(&driver, &psb_pci_driver);
1435 }
1436
1437 static void __exit psb_exit(void)
1438 {
1439         drm_pci_exit(&driver, &psb_pci_driver);
1440 }
1441
1442 late_initcall(psb_init);
1443 module_exit(psb_exit);
1444
1445 MODULE_AUTHOR("Alan Cox <alan@linux.intel.com> and others");
1446 MODULE_DESCRIPTION(DRIVER_DESC);
1447 MODULE_LICENSE("GPL");