drivers/spi/spi-dw-mid.c

   1 /*
   2  * Special handling for DW core on Intel MID platform
   3  *
   4  * Copyright (c) 2009, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/dma-mapping.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/slab.h>
  24 #include <linux/spi/spi.h>
  25
  26 #include "spi-dw.h"
  27
  28 #ifdef CONFIG_SPI_DW_MID_DMA
  29 #include <linux/intel_mid_dma.h>
  30 #include <linux/pci.h>
  31
  32 struct mid_dma {
  33         struct intel_mid_dma_slave      dmas_tx;
  34         struct intel_mid_dma_slave      dmas_rx;
  35 };
  36
  37 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
  38 {
  39         struct dw_spi *dws = param;
  40
  41         return dws->dmac && (&dws->dmac->dev == chan->device->dev);
  42 }
  43
  44 static int mid_spi_dma_init(struct dw_spi *dws)
  45 {
  46         struct mid_dma *dw_dma = dws->dma_priv;
  47         struct intel_mid_dma_slave *rxs, *txs;
  48         dma_cap_mask_t mask;
  49
  50         /*
  51          * Get pci device for DMA controller, currently it could only
  52          * be the DMA controller of either Moorestown or Medfield
  53          */
  54         dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0813, NULL);
  55         if (!dws->dmac)
  56                 dws->dmac = pci_get_device(PCI_VENDOR_ID_INTEL, 0x0827, NULL);
  57
  58         dma_cap_zero(mask);
  59         dma_cap_set(DMA_SLAVE, mask);
  60
  61         /* 1. Init rx channel */
  62         dws->rxchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  63         if (!dws->rxchan)
  64                 goto err_exit;
  65         rxs = &dw_dma->dmas_rx;
  66         rxs->hs_mode = LNW_DMA_HW_HS;
  67         rxs->cfg_mode = LNW_DMA_PER_TO_MEM;
  68         dws->rxchan->private = rxs;
  69
  70         /* 2. Init tx channel */
  71         dws->txchan = dma_request_channel(mask, mid_spi_dma_chan_filter, dws);
  72         if (!dws->txchan)
  73                 goto free_rxchan;
  74         txs = &dw_dma->dmas_tx;
  75         txs->hs_mode = LNW_DMA_HW_HS;
  76         txs->cfg_mode = LNW_DMA_MEM_TO_PER;
  77         dws->txchan->private = txs;
  78
  79         dws->dma_inited = 1;
  80         return 0;
  81
  82 free_rxchan:
  83         dma_release_channel(dws->rxchan);
  84 err_exit:
  85         return -1;
  86
  87 }
  88
  89 static void mid_spi_dma_exit(struct dw_spi *dws)
  90 {
  91         if (!dws->dma_inited)
  92                 return;
  93         dma_release_channel(dws->txchan);
  94         dma_release_channel(dws->rxchan);
  95 }
  96
  97 /*
  98  * dws->dma_chan_done is cleared before the dma transfer starts,
  99  * callback for rx/tx channel will each increment it by 1.
 100  * Reaching 2 means the whole spi transaction is done.
 101  */
 102 static void dw_spi_dma_done(void *arg)
 103 {
 104         struct dw_spi *dws = arg;
 105
 106         if (++dws->dma_chan_done != 2)
 107                 return;
 108         dw_spi_xfer_done(dws);
 109 }
 110
 111 static int mid_spi_dma_transfer(struct dw_spi *dws, int cs_change)
 112 {
 113         struct dma_async_tx_descriptor *txdesc = NULL, *rxdesc = NULL;
 114         struct dma_chan *txchan, *rxchan;
 115         struct dma_slave_config txconf, rxconf;
 116         u16 dma_ctrl = 0;
 117
 118         /* 1. setup DMA related registers */
 119         if (cs_change) {
 120                 spi_enable_chip(dws, 0);
 121                 dw_writew(dws, DW_SPI_DMARDLR, 0xf);
 122                 dw_writew(dws, DW_SPI_DMATDLR, 0x10);
 123                 if (dws->tx_dma)
 124                         dma_ctrl |= 0x2;
 125                 if (dws->rx_dma)
 126                         dma_ctrl |= 0x1;
 127                 dw_writew(dws, DW_SPI_DMACR, dma_ctrl);
 128                 spi_enable_chip(dws, 1);
 129         }
 130
 131         dws->dma_chan_done = 0;
 132         txchan = dws->txchan;
 133         rxchan = dws->rxchan;
 134
 135         /* 2. Prepare the TX dma transfer */
 136         txconf.direction = DMA_TO_DEVICE;
 137         txconf.dst_addr = dws->dma_addr;
 138         txconf.dst_maxburst = LNW_DMA_MSIZE_16;
 139         txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 140         txconf.dst_addr_width = dws->dma_width;
 141
 142         txchan->device->device_control(txchan, DMA_SLAVE_CONFIG,
 143                                        (unsigned long) &txconf);
 144
 145         memset(&dws->tx_sgl, 0, sizeof(dws->tx_sgl));
 146         dws->tx_sgl.dma_address = dws->tx_dma;
 147         dws->tx_sgl.length = dws->len;
 148
 149         txdesc = txchan->device->device_prep_slave_sg(txchan,
 150                                 &dws->tx_sgl,
 151                                 1,
 152                                 DMA_TO_DEVICE,
 153                                 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
 154         txdesc->callback = dw_spi_dma_done;
 155         txdesc->callback_param = dws;
 156
 157         /* 3. Prepare the RX dma transfer */
 158         rxconf.direction = DMA_FROM_DEVICE;
 159         rxconf.src_addr = dws->dma_addr;
 160         rxconf.src_maxburst = LNW_DMA_MSIZE_16;
 161         rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 162         rxconf.src_addr_width = dws->dma_width;
 163
 164         rxchan->device->device_control(rxchan, DMA_SLAVE_CONFIG,
 165                                        (unsigned long) &rxconf);
 166
 167         memset(&dws->rx_sgl, 0, sizeof(dws->rx_sgl));
 168         dws->rx_sgl.dma_address = dws->rx_dma;
 169         dws->rx_sgl.length = dws->len;
 170
 171         rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
 172                                 &dws->rx_sgl,
 173                                 1,
 174                                 DMA_FROM_DEVICE,
 175                                 DMA_PREP_INTERRUPT | DMA_COMPL_SKIP_DEST_UNMAP);
 176         rxdesc->callback = dw_spi_dma_done;
 177         rxdesc->callback_param = dws;
 178
 179         /* rx must be started before tx due to spi instinct */
 180         rxdesc->tx_submit(rxdesc);
 181         txdesc->tx_submit(txdesc);
 182         return 0;
 183 }
 184
 185 static struct dw_spi_dma_ops mid_dma_ops = {
 186         .dma_init       = mid_spi_dma_init,
 187         .dma_exit       = mid_spi_dma_exit,
 188         .dma_transfer   = mid_spi_dma_transfer,
 189 };
 190 #endif
 191
 192 /* Some specific info for SPI0 controller on Moorestown */
 193
 194 /* HW info for MRST CLk Control Unit, one 32b reg */
 195 #define MRST_SPI_CLK_BASE       100000000       /* 100m */
 196 #define MRST_CLK_SPI0_REG       0xff11d86c
 197 #define CLK_SPI_BDIV_OFFSET     0
 198 #define CLK_SPI_BDIV_MASK       0x00000007
 199 #define CLK_SPI_CDIV_OFFSET     9
 200 #define CLK_SPI_CDIV_MASK       0x00000e00
 201 #define CLK_SPI_DISABLE_OFFSET  8
 202
 203 int dw_spi_mid_init(struct dw_spi *dws)
 204 {
 205         void __iomem *clk_reg;
 206         u32 clk_cdiv;
 207
 208         clk_reg = ioremap_nocache(MRST_CLK_SPI0_REG, 16);
 209         if (!clk_reg)
 210                 return -ENOMEM;
 211
 212         /* get SPI controller operating freq info */
 213         clk_cdiv  = (readl(clk_reg) & CLK_SPI_CDIV_MASK) >> CLK_SPI_CDIV_OFFSET;
 214         dws->max_freq = MRST_SPI_CLK_BASE / (clk_cdiv + 1);
 215         iounmap(clk_reg);
 216
 217         dws->num_cs = 16;
 218         dws->fifo_len = 40;     /* FIFO has 40 words buffer */
 219
 220 #ifdef CONFIG_SPI_DW_MID_DMA
 221         dws->dma_priv = kzalloc(sizeof(struct mid_dma), GFP_KERNEL);
 222         if (!dws->dma_priv)
 223                 return -ENOMEM;
 224         dws->dma_ops = &mid_dma_ops;
 225 #endif
 226         return 0;
 227 }