1 /******************************************************************************
3 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
29 #include <linux/sched.h>
30 #include <linux/wait.h>
31 #include <linux/gfp.h>
35 #include "iwl-trans-pcie-int.h"
36 #include "iwl-op-mode.h"
38 #ifdef CONFIG_IWLWIFI_IDI
42 /******************************************************************************
46 ******************************************************************************/
49 * Rx theory of operation
51 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
52 * each of which point to Receive Buffers to be filled by the NIC. These get
53 * used not only for Rx frames, but for any command response or notification
54 * from the NIC. The driver and NIC manage the Rx buffers by means
55 * of indexes into the circular buffer.
58 * The host/firmware share two index registers for managing the Rx buffers.
60 * The READ index maps to the first position that the firmware may be writing
61 * to -- the driver can read up to (but not including) this position and get
63 * The READ index is managed by the firmware once the card is enabled.
65 * The WRITE index maps to the last position the driver has read from -- the
66 * position preceding WRITE is the last slot the firmware can place a packet.
68 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
71 * During initialization, the host sets up the READ queue position to the first
72 * INDEX position, and WRITE to the last (READ - 1 wrapped)
74 * When the firmware places a packet in a buffer, it will advance the READ index
75 * and fire the RX interrupt. The driver can then query the READ index and
76 * process as many packets as possible, moving the WRITE index forward as it
77 * resets the Rx queue buffers with new memory.
79 * The management in the driver is as follows:
80 * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free. When
81 * iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
82 * to replenish the iwl->rxq->rx_free.
83 * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
84 * iwl->rxq is replenished and the READ INDEX is updated (updating the
85 * 'processed' and 'read' driver indexes as well)
86 * + A received packet is processed and handed to the kernel network stack,
87 * detached from the iwl->rxq. The driver 'processed' index is updated.
88 * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
89 * list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
90 * INDEX is not incremented and iwl->status(RX_STALLED) is set. If there
91 * were enough free buffers and RX_STALLED is set it is cleared.
96 * iwl_rx_queue_alloc() Allocates rx_free
97 * iwl_rx_replenish() Replenishes rx_free list from rx_used, and calls
98 * iwl_rx_queue_restock
99 * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
100 * queue, updates firmware pointers, and updates
101 * the WRITE index. If insufficient rx_free buffers
102 * are available, schedules iwl_rx_replenish
104 * -- enable interrupts --
105 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
106 * READ INDEX, detaching the SKB from the pool.
107 * Moves the packet buffer from queue to rx_used.
108 * Calls iwl_rx_queue_restock to refill any empty
115 * iwl_rx_queue_space - Return number of free slots available in queue.
117 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
119 int s = q->read - q->write;
122 /* keep some buffer to not confuse full and empty queue */
130 * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
132 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
133 struct iwl_rx_queue *q)
138 spin_lock_irqsave(&q->lock, flags);
140 if (q->need_update == 0)
143 if (cfg(trans)->base_params->shadow_reg_enable) {
144 /* shadow register enabled */
145 /* Device expects a multiple of 8 */
146 q->write_actual = (q->write & ~0x7);
147 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
149 /* If power-saving is in use, make sure device is awake */
150 if (test_bit(STATUS_POWER_PMI, &trans->shrd->status)) {
151 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
153 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
154 IWL_DEBUG_INFO(trans,
155 "Rx queue requesting wakeup,"
156 " GP1 = 0x%x\n", reg);
157 iwl_set_bit(trans, CSR_GP_CNTRL,
158 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
162 q->write_actual = (q->write & ~0x7);
163 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
166 /* Else device is assumed to be awake */
168 /* Device expects a multiple of 8 */
169 q->write_actual = (q->write & ~0x7);
170 iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
177 spin_unlock_irqrestore(&q->lock, flags);
181 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
183 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
185 return cpu_to_le32((u32)(dma_addr >> 8));
189 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
191 * If there are slots in the RX queue that need to be restocked,
192 * and we have free pre-allocated buffers, fill the ranks as much
193 * as we can, pulling from rx_free.
195 * This moves the 'write' index forward to catch up with 'processed', and
196 * also updates the memory address in the firmware to reference the new
199 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
201 struct iwl_trans_pcie *trans_pcie =
202 IWL_TRANS_GET_PCIE_TRANS(trans);
204 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
205 struct list_head *element;
206 struct iwl_rx_mem_buffer *rxb;
209 spin_lock_irqsave(&rxq->lock, flags);
210 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
211 /* The overwritten rxb must be a used one */
212 rxb = rxq->queue[rxq->write];
213 BUG_ON(rxb && rxb->page);
215 /* Get next free Rx buffer, remove from free list */
216 element = rxq->rx_free.next;
217 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
220 /* Point to Rx buffer via next RBD in circular buffer */
221 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
222 rxq->queue[rxq->write] = rxb;
223 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
226 spin_unlock_irqrestore(&rxq->lock, flags);
227 /* If the pre-allocated buffer pool is dropping low, schedule to
229 if (rxq->free_count <= RX_LOW_WATERMARK)
230 schedule_work(&trans_pcie->rx_replenish);
233 /* If we've added more space for the firmware to place data, tell it.
234 * Increment device's write pointer in multiples of 8. */
235 if (rxq->write_actual != (rxq->write & ~0x7)) {
236 spin_lock_irqsave(&rxq->lock, flags);
237 rxq->need_update = 1;
238 spin_unlock_irqrestore(&rxq->lock, flags);
239 iwl_rx_queue_update_write_ptr(trans, rxq);
244 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
246 * When moving to rx_free an SKB is allocated for the slot.
248 * Also restock the Rx queue via iwl_rx_queue_restock.
249 * This is called as a scheduled work item (except for during initialization)
251 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
253 struct iwl_trans_pcie *trans_pcie =
254 IWL_TRANS_GET_PCIE_TRANS(trans);
256 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
257 struct list_head *element;
258 struct iwl_rx_mem_buffer *rxb;
261 gfp_t gfp_mask = priority;
264 spin_lock_irqsave(&rxq->lock, flags);
265 if (list_empty(&rxq->rx_used)) {
266 spin_unlock_irqrestore(&rxq->lock, flags);
269 spin_unlock_irqrestore(&rxq->lock, flags);
271 if (rxq->free_count > RX_LOW_WATERMARK)
272 gfp_mask |= __GFP_NOWARN;
274 if (hw_params(trans).rx_page_order > 0)
275 gfp_mask |= __GFP_COMP;
277 /* Alloc a new receive buffer */
278 page = alloc_pages(gfp_mask,
279 hw_params(trans).rx_page_order);
282 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
284 hw_params(trans).rx_page_order);
286 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
288 IWL_CRIT(trans, "Failed to alloc_pages with %s."
289 "Only %u free buffers remaining.\n",
290 priority == GFP_ATOMIC ?
291 "GFP_ATOMIC" : "GFP_KERNEL",
293 /* We don't reschedule replenish work here -- we will
294 * call the restock method and if it still needs
295 * more buffers it will schedule replenish */
299 spin_lock_irqsave(&rxq->lock, flags);
301 if (list_empty(&rxq->rx_used)) {
302 spin_unlock_irqrestore(&rxq->lock, flags);
303 __free_pages(page, hw_params(trans).rx_page_order);
306 element = rxq->rx_used.next;
307 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
310 spin_unlock_irqrestore(&rxq->lock, flags);
314 /* Get physical address of the RB */
315 rxb->page_dma = dma_map_page(trans->dev, page, 0,
316 PAGE_SIZE << hw_params(trans).rx_page_order,
318 /* dma address must be no more than 36 bits */
319 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
320 /* and also 256 byte aligned! */
321 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
323 spin_lock_irqsave(&rxq->lock, flags);
325 list_add_tail(&rxb->list, &rxq->rx_free);
328 spin_unlock_irqrestore(&rxq->lock, flags);
332 void iwlagn_rx_replenish(struct iwl_trans *trans)
334 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
337 iwlagn_rx_allocate(trans, GFP_KERNEL);
339 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
340 iwlagn_rx_queue_restock(trans);
341 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
344 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
346 iwlagn_rx_allocate(trans, GFP_ATOMIC);
348 iwlagn_rx_queue_restock(trans);
351 void iwl_bg_rx_replenish(struct work_struct *data)
353 struct iwl_trans_pcie *trans_pcie =
354 container_of(data, struct iwl_trans_pcie, rx_replenish);
356 iwlagn_rx_replenish(trans_pcie->trans);
359 static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
360 struct iwl_rx_mem_buffer *rxb)
362 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
363 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
364 struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
365 struct iwl_device_cmd *cmd;
369 struct iwl_rx_cmd_buffer rxcb;
370 struct iwl_rx_packet *pkt;
372 int index, cmd_index;
377 dma_unmap_page(trans->dev, rxb->page_dma,
378 PAGE_SIZE << hw_params(trans).rx_page_order,
381 rxcb._page = rxb->page;
382 pkt = rxb_addr(&rxcb);
384 IWL_DEBUG_RX(trans, "%s, 0x%02x\n",
385 get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
388 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
389 len += sizeof(u32); /* account for status word */
390 trace_iwlwifi_dev_rx(trans->dev, pkt, len);
392 /* Reclaim a command buffer only if this packet is a response
393 * to a (driver-originated) command.
394 * If the packet (e.g. Rx frame) originated from uCode,
395 * there is no command buffer to reclaim.
396 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
397 * but apparently a few don't get set; catch them here. */
398 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
402 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
403 if (trans_pcie->no_reclaim_cmds[i] == pkt->hdr.cmd) {
410 sequence = le16_to_cpu(pkt->hdr.sequence);
411 index = SEQ_TO_INDEX(sequence);
412 cmd_index = get_cmd_index(&txq->q, index);
415 cmd = txq->cmd[cmd_index];
419 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
422 * XXX: After here, we should always check rxcb._page
423 * against NULL before touching it or its virtual
424 * memory (pkt). Because some rx_handler might have
425 * already taken or freed the pages.
429 /* Invoke any callbacks, transfer the buffer to caller,
430 * and fire off the (possibly) blocking
431 * iwl_trans_send_cmd()
432 * as we reclaim the driver command queue */
434 iwl_tx_cmd_complete(trans, &rxcb, err);
436 IWL_WARN(trans, "Claim null rxb?\n");
439 /* page was stolen from us */
440 if (rxcb._page == NULL)
443 /* Reuse the page if possible. For notification packets and
444 * SKBs that fail to Rx correctly, add them back into the
445 * rx_free list for reuse later. */
446 spin_lock_irqsave(&rxq->lock, flags);
447 if (rxb->page != NULL) {
449 dma_map_page(trans->dev, rxb->page, 0,
450 PAGE_SIZE << hw_params(trans).rx_page_order,
452 list_add_tail(&rxb->list, &rxq->rx_free);
455 list_add_tail(&rxb->list, &rxq->rx_used);
456 spin_unlock_irqrestore(&rxq->lock, flags);
460 * iwl_rx_handle - Main entry function for receiving responses from uCode
462 * Uses the priv->rx_handlers callback function array to invoke
463 * the appropriate handlers, including command responses,
464 * frame-received notifications, and other notifications.
466 static void iwl_rx_handle(struct iwl_trans *trans)
468 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
469 struct iwl_rx_queue *rxq = &trans_pcie->rxq;
475 /* uCode's read index (stored in shared DRAM) indicates the last Rx
476 * buffer that the driver may process (last buffer filled by ucode). */
477 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
480 /* Rx interrupt, but nothing sent from uCode */
482 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
484 /* calculate total frames need to be restock after handling RX */
485 total_empty = r - rxq->write_actual;
487 total_empty += RX_QUEUE_SIZE;
489 if (total_empty > (RX_QUEUE_SIZE / 2))
493 struct iwl_rx_mem_buffer *rxb;
496 rxq->queue[i] = NULL;
498 IWL_DEBUG_RX(trans, "rxbuf: r = %d, i = %d (%p)\n", rxb);
500 iwl_rx_handle_rxbuf(trans, rxb);
502 i = (i + 1) & RX_QUEUE_MASK;
503 /* If there are a lot of unused frames,
504 * restock the Rx queue so ucode wont assert. */
509 iwlagn_rx_replenish_now(trans);
515 /* Backtrack one entry */
518 iwlagn_rx_replenish_now(trans);
520 iwlagn_rx_queue_restock(trans);
523 static const char * const desc_lookup_text[] = {
532 "HW_ERROR_TUNE_LOCK",
533 "HW_ERROR_TEMPERATURE",
537 "NMI_INTERRUPT_HOST",
538 "NMI_INTERRUPT_ACTION_PT",
539 "NMI_INTERRUPT_UNKNOWN",
540 "UCODE_VERSION_MISMATCH",
542 "HW_ERROR_CAL_LOCK_FAIL",
543 "NMI_INTERRUPT_INST_ACTION_PT",
544 "NMI_INTERRUPT_DATA_ACTION_PT",
547 "NMI_INTERRUPT_BREAK_POINT",
554 static struct { char *name; u8 num; } advanced_lookup[] = {
555 { "NMI_INTERRUPT_WDG", 0x34 },
556 { "SYSASSERT", 0x35 },
557 { "UCODE_VERSION_MISMATCH", 0x37 },
558 { "BAD_COMMAND", 0x38 },
559 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
560 { "FATAL_ERROR", 0x3D },
561 { "NMI_TRM_HW_ERR", 0x46 },
562 { "NMI_INTERRUPT_TRM", 0x4C },
563 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
564 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
565 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
566 { "NMI_INTERRUPT_HOST", 0x66 },
567 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
568 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
569 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
570 { "ADVANCED_SYSASSERT", 0 },
573 static const char *desc_lookup(u32 num)
576 int max = ARRAY_SIZE(desc_lookup_text);
579 return desc_lookup_text[num];
581 max = ARRAY_SIZE(advanced_lookup) - 1;
582 for (i = 0; i < max; i++) {
583 if (advanced_lookup[i].num == num)
586 return advanced_lookup[i].name;
589 #define ERROR_START_OFFSET (1 * sizeof(u32))
590 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
592 static void iwl_dump_nic_error_log(struct iwl_trans *trans)
595 struct iwl_error_event_table table;
596 struct iwl_trans_pcie *trans_pcie =
597 IWL_TRANS_GET_PCIE_TRANS(trans);
599 base = trans->shrd->device_pointers.error_event_table;
600 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
602 base = trans->shrd->fw->init_errlog_ptr;
605 base = trans->shrd->fw->inst_errlog_ptr;
608 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
610 "Not valid error log pointer 0x%08X for %s uCode\n",
612 (trans->shrd->ucode_type == IWL_UCODE_INIT)
617 iwl_read_targ_mem_words(trans, base, &table, sizeof(table));
619 if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
620 IWL_ERR(trans, "Start IWL Error Log Dump:\n");
621 IWL_ERR(trans, "Status: 0x%08lX, count: %d\n",
622 trans->shrd->status, table.valid);
625 trans_pcie->isr_stats.err_code = table.error_id;
627 trace_iwlwifi_dev_ucode_error(trans->dev, table.error_id, table.tsf_low,
628 table.data1, table.data2, table.line,
629 table.blink1, table.blink2, table.ilink1,
630 table.ilink2, table.bcon_time, table.gp1,
631 table.gp2, table.gp3, table.ucode_ver,
632 table.hw_ver, table.brd_ver);
633 IWL_ERR(trans, "0x%08X | %-28s\n", table.error_id,
634 desc_lookup(table.error_id));
635 IWL_ERR(trans, "0x%08X | uPc\n", table.pc);
636 IWL_ERR(trans, "0x%08X | branchlink1\n", table.blink1);
637 IWL_ERR(trans, "0x%08X | branchlink2\n", table.blink2);
638 IWL_ERR(trans, "0x%08X | interruptlink1\n", table.ilink1);
639 IWL_ERR(trans, "0x%08X | interruptlink2\n", table.ilink2);
640 IWL_ERR(trans, "0x%08X | data1\n", table.data1);
641 IWL_ERR(trans, "0x%08X | data2\n", table.data2);
642 IWL_ERR(trans, "0x%08X | line\n", table.line);
643 IWL_ERR(trans, "0x%08X | beacon time\n", table.bcon_time);
644 IWL_ERR(trans, "0x%08X | tsf low\n", table.tsf_low);
645 IWL_ERR(trans, "0x%08X | tsf hi\n", table.tsf_hi);
646 IWL_ERR(trans, "0x%08X | time gp1\n", table.gp1);
647 IWL_ERR(trans, "0x%08X | time gp2\n", table.gp2);
648 IWL_ERR(trans, "0x%08X | time gp3\n", table.gp3);
649 IWL_ERR(trans, "0x%08X | uCode version\n", table.ucode_ver);
650 IWL_ERR(trans, "0x%08X | hw version\n", table.hw_ver);
651 IWL_ERR(trans, "0x%08X | board version\n", table.brd_ver);
652 IWL_ERR(trans, "0x%08X | hcmd\n", table.hcmd);
654 IWL_ERR(trans, "0x%08X | isr0\n", table.isr0);
655 IWL_ERR(trans, "0x%08X | isr1\n", table.isr1);
656 IWL_ERR(trans, "0x%08X | isr2\n", table.isr2);
657 IWL_ERR(trans, "0x%08X | isr3\n", table.isr3);
658 IWL_ERR(trans, "0x%08X | isr4\n", table.isr4);
659 IWL_ERR(trans, "0x%08X | isr_pref\n", table.isr_pref);
660 IWL_ERR(trans, "0x%08X | wait_event\n", table.wait_event);
661 IWL_ERR(trans, "0x%08X | l2p_control\n", table.l2p_control);
662 IWL_ERR(trans, "0x%08X | l2p_duration\n", table.l2p_duration);
663 IWL_ERR(trans, "0x%08X | l2p_mhvalid\n", table.l2p_mhvalid);
664 IWL_ERR(trans, "0x%08X | l2p_addr_match\n", table.l2p_addr_match);
665 IWL_ERR(trans, "0x%08X | lmpm_pmg_sel\n", table.lmpm_pmg_sel);
666 IWL_ERR(trans, "0x%08X | timestamp\n", table.u_timestamp);
667 IWL_ERR(trans, "0x%08X | flow_handler\n", table.flow_handler);
671 * iwl_irq_handle_error - called for HW or SW error interrupt from card
673 static void iwl_irq_handle_error(struct iwl_trans *trans)
675 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
676 if (cfg(trans)->internal_wimax_coex &&
677 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
678 APMS_CLK_VAL_MRB_FUNC_MODE) ||
679 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
680 APMG_PS_CTRL_VAL_RESET_REQ))) {
682 * Keep the restart process from trying to send host
683 * commands by clearing the ready bit.
685 clear_bit(STATUS_READY, &trans->shrd->status);
686 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
687 wake_up(&trans->wait_command_queue);
688 IWL_ERR(trans, "RF is used by WiMAX\n");
692 IWL_ERR(trans, "Loaded firmware version: %s\n",
693 trans->shrd->fw->fw_version);
695 iwl_dump_nic_error_log(trans);
697 iwl_dump_fh(trans, NULL, false);
698 iwl_dump_nic_event_log(trans, false, NULL, false);
700 iwl_op_mode_nic_error(trans->op_mode);
703 #define EVENT_START_OFFSET (4 * sizeof(u32))
706 * iwl_print_event_log - Dump error event log to syslog
709 static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
710 u32 num_events, u32 mode,
711 int pos, char **buf, size_t bufsz)
714 u32 base; /* SRAM byte address of event log header */
715 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
716 u32 ptr; /* SRAM byte address of log data */
717 u32 ev, time, data; /* event log data */
718 unsigned long reg_flags;
723 base = trans->shrd->device_pointers.log_event_table;
724 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
726 base = trans->shrd->fw->init_evtlog_ptr;
729 base = trans->shrd->fw->inst_evtlog_ptr;
733 event_size = 2 * sizeof(u32);
735 event_size = 3 * sizeof(u32);
737 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
739 /* Make sure device is powered up for SRAM reads */
740 spin_lock_irqsave(&trans->reg_lock, reg_flags);
741 if (unlikely(!iwl_grab_nic_access(trans)))
744 /* Set starting address; reads will auto-increment */
745 iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
747 /* "time" is actually "data" for mode 0 (no timestamp).
748 * place event id # at far right for easier visual parsing. */
749 for (i = 0; i < num_events; i++) {
750 ev = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
751 time = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
755 pos += scnprintf(*buf + pos, bufsz - pos,
756 "EVT_LOG:0x%08x:%04u\n",
759 trace_iwlwifi_dev_ucode_event(trans->dev, 0,
761 IWL_ERR(trans, "EVT_LOG:0x%08x:%04u\n",
765 data = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
767 pos += scnprintf(*buf + pos, bufsz - pos,
768 "EVT_LOGT:%010u:0x%08x:%04u\n",
771 IWL_ERR(trans, "EVT_LOGT:%010u:0x%08x:%04u\n",
773 trace_iwlwifi_dev_ucode_event(trans->dev, time,
779 /* Allow device to power down */
780 iwl_release_nic_access(trans);
782 spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
787 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
789 static int iwl_print_last_event_logs(struct iwl_trans *trans, u32 capacity,
790 u32 num_wraps, u32 next_entry,
792 int pos, char **buf, size_t bufsz)
795 * display the newest DEFAULT_LOG_ENTRIES entries
796 * i.e the entries just before the next ont that uCode would fill.
799 if (next_entry < size) {
800 pos = iwl_print_event_log(trans,
801 capacity - (size - next_entry),
802 size - next_entry, mode,
804 pos = iwl_print_event_log(trans, 0,
808 pos = iwl_print_event_log(trans, next_entry - size,
809 size, mode, pos, buf, bufsz);
811 if (next_entry < size) {
812 pos = iwl_print_event_log(trans, 0, next_entry,
813 mode, pos, buf, bufsz);
815 pos = iwl_print_event_log(trans, next_entry - size,
816 size, mode, pos, buf, bufsz);
822 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
824 int iwl_dump_nic_event_log(struct iwl_trans *trans, bool full_log,
825 char **buf, bool display)
827 u32 base; /* SRAM byte address of event log header */
828 u32 capacity; /* event log capacity in # entries */
829 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
830 u32 num_wraps; /* # times uCode wrapped to top of log */
831 u32 next_entry; /* index of next entry to be written by uCode */
832 u32 size; /* # entries that we'll print */
837 base = trans->shrd->device_pointers.log_event_table;
838 if (trans->shrd->ucode_type == IWL_UCODE_INIT) {
839 logsize = trans->shrd->fw->init_evtlog_size;
841 base = trans->shrd->fw->init_evtlog_ptr;
843 logsize = trans->shrd->fw->inst_evtlog_size;
845 base = trans->shrd->fw->inst_evtlog_ptr;
848 if (!iwlagn_hw_valid_rtc_data_addr(base)) {
850 "Invalid event log pointer 0x%08X for %s uCode\n",
852 (trans->shrd->ucode_type == IWL_UCODE_INIT)
857 /* event log header */
858 capacity = iwl_read_targ_mem(trans, base);
859 mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32)));
860 num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32)));
861 next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32)));
863 if (capacity > logsize) {
864 IWL_ERR(trans, "Log capacity %d is bogus, limit to %d "
865 "entries\n", capacity, logsize);
869 if (next_entry > logsize) {
870 IWL_ERR(trans, "Log write index %d is bogus, limit to %d\n",
871 next_entry, logsize);
872 next_entry = logsize;
875 size = num_wraps ? capacity : next_entry;
877 /* bail out if nothing in log */
879 IWL_ERR(trans, "Start IWL Event Log Dump: nothing in log\n");
883 #ifdef CONFIG_IWLWIFI_DEBUG
884 if (!(iwl_have_debug_level(IWL_DL_FW_ERRORS)) && !full_log)
885 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
886 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
888 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
889 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
891 IWL_ERR(trans, "Start IWL Event Log Dump: display last %u entries\n",
894 #ifdef CONFIG_IWLWIFI_DEBUG
897 bufsz = capacity * 48;
900 *buf = kmalloc(bufsz, GFP_KERNEL);
904 if (iwl_have_debug_level(IWL_DL_FW_ERRORS) || full_log) {
906 * if uCode has wrapped back to top of log,
907 * start at the oldest entry,
908 * i.e the next one that uCode would fill.
911 pos = iwl_print_event_log(trans, next_entry,
912 capacity - next_entry, mode,
914 /* (then/else) start at top of log */
915 pos = iwl_print_event_log(trans, 0,
916 next_entry, mode, pos, buf, bufsz);
918 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
919 next_entry, size, mode,
922 pos = iwl_print_last_event_logs(trans, capacity, num_wraps,
923 next_entry, size, mode,
929 /* tasklet for iwlagn interrupt */
930 void iwl_irq_tasklet(struct iwl_trans *trans)
936 #ifdef CONFIG_IWLWIFI_DEBUG
940 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
941 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
944 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
946 /* Ack/clear/reset pending uCode interrupts.
947 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
949 /* There is a hardware bug in the interrupt mask function that some
950 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
951 * they are disabled in the CSR_INT_MASK register. Furthermore the
952 * ICT interrupt handling mechanism has another bug that might cause
953 * these unmasked interrupts fail to be detected. We workaround the
954 * hardware bugs here by ACKing all the possible interrupts so that
955 * interrupt coalescing can still be achieved.
957 iwl_write32(trans, CSR_INT,
958 trans_pcie->inta | ~trans_pcie->inta_mask);
960 inta = trans_pcie->inta;
962 #ifdef CONFIG_IWLWIFI_DEBUG
963 if (iwl_have_debug_level(IWL_DL_ISR)) {
965 inta_mask = iwl_read32(trans, CSR_INT_MASK);
966 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n ",
971 /* saved interrupt in inta variable now we can reset trans_pcie->inta */
972 trans_pcie->inta = 0;
974 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
976 /* Now service all interrupt bits discovered above. */
977 if (inta & CSR_INT_BIT_HW_ERR) {
978 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
980 /* Tell the device to stop sending interrupts */
981 iwl_disable_interrupts(trans);
984 iwl_irq_handle_error(trans);
986 handled |= CSR_INT_BIT_HW_ERR;
991 #ifdef CONFIG_IWLWIFI_DEBUG
992 if (iwl_have_debug_level(IWL_DL_ISR)) {
993 /* NIC fires this, but we don't use it, redundant with WAKEUP */
994 if (inta & CSR_INT_BIT_SCD) {
995 IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
996 "the frame/frames.\n");
1000 /* Alive notification via Rx interrupt will do the real work */
1001 if (inta & CSR_INT_BIT_ALIVE) {
1002 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1007 /* Safely ignore these bits for debug checks below */
1008 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1010 /* HW RF KILL switch toggled */
1011 if (inta & CSR_INT_BIT_RF_KILL) {
1014 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
1015 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
1016 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1017 hw_rfkill ? "disable radio" : "enable radio");
1019 isr_stats->rfkill++;
1021 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
1023 handled |= CSR_INT_BIT_RF_KILL;
1026 /* Chip got too hot and stopped itself */
1027 if (inta & CSR_INT_BIT_CT_KILL) {
1028 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1029 isr_stats->ctkill++;
1030 handled |= CSR_INT_BIT_CT_KILL;
1033 /* Error detected by uCode */
1034 if (inta & CSR_INT_BIT_SW_ERR) {
1035 IWL_ERR(trans, "Microcode SW error detected. "
1036 " Restarting 0x%X.\n", inta);
1038 iwl_irq_handle_error(trans);
1039 handled |= CSR_INT_BIT_SW_ERR;
1042 /* uCode wakes up after power-down sleep */
1043 if (inta & CSR_INT_BIT_WAKEUP) {
1044 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1045 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
1046 for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++)
1047 iwl_txq_update_write_ptr(trans,
1048 &trans_pcie->txq[i]);
1050 isr_stats->wakeup++;
1052 handled |= CSR_INT_BIT_WAKEUP;
1055 /* All uCode command responses, including Tx command responses,
1056 * Rx "responses" (frame-received notification), and other
1057 * notifications from uCode come through here*/
1058 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1059 CSR_INT_BIT_RX_PERIODIC)) {
1060 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1061 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1062 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1063 iwl_write32(trans, CSR_FH_INT_STATUS,
1064 CSR_FH_INT_RX_MASK);
1066 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1067 handled |= CSR_INT_BIT_RX_PERIODIC;
1069 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1071 /* Sending RX interrupt require many steps to be done in the
1073 * 1- write interrupt to current index in ICT table.
1075 * 3- update RX shared data to indicate last write index.
1076 * 4- send interrupt.
1077 * This could lead to RX race, driver could receive RX interrupt
1078 * but the shared data changes does not reflect this;
1079 * periodic interrupt will detect any dangling Rx activity.
1082 /* Disable periodic interrupt; we use it as just a one-shot. */
1083 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1084 CSR_INT_PERIODIC_DIS);
1085 #ifdef CONFIG_IWLWIFI_IDI
1086 iwl_amfh_rx_handler();
1088 iwl_rx_handle(trans);
1091 * Enable periodic interrupt in 8 msec only if we received
1092 * real RX interrupt (instead of just periodic int), to catch
1093 * any dangling Rx interrupt. If it was just the periodic
1094 * interrupt, there was no dangling Rx activity, and no need
1095 * to extend the periodic interrupt; one-shot is enough.
1097 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1098 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1099 CSR_INT_PERIODIC_ENA);
1104 /* This "Tx" DMA channel is used only for loading uCode */
1105 if (inta & CSR_INT_BIT_FH_TX) {
1106 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1107 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1109 handled |= CSR_INT_BIT_FH_TX;
1110 /* Wake up uCode load routine, now that load is complete */
1111 trans_pcie->ucode_write_complete = true;
1112 wake_up(&trans_pcie->ucode_write_waitq);
1115 if (inta & ~handled) {
1116 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1117 isr_stats->unhandled++;
1120 if (inta & ~(trans_pcie->inta_mask)) {
1121 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1122 inta & ~trans_pcie->inta_mask);
1125 /* Re-enable all interrupts */
1126 /* only Re-enable if disabled by irq */
1127 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
1128 iwl_enable_interrupts(trans);
1129 /* Re-enable RF_KILL if it occurred */
1130 else if (handled & CSR_INT_BIT_RF_KILL)
1131 iwl_enable_rfkill_int(trans);
1134 /******************************************************************************
1138 ******************************************************************************/
1140 /* a device (PCI-E) page is 4096 bytes long */
1141 #define ICT_SHIFT 12
1142 #define ICT_SIZE (1 << ICT_SHIFT)
1143 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1145 /* Free dram table */
1146 void iwl_free_isr_ict(struct iwl_trans *trans)
1148 struct iwl_trans_pcie *trans_pcie =
1149 IWL_TRANS_GET_PCIE_TRANS(trans);
1151 if (trans_pcie->ict_tbl) {
1152 dma_free_coherent(trans->dev, ICT_SIZE,
1153 trans_pcie->ict_tbl,
1154 trans_pcie->ict_tbl_dma);
1155 trans_pcie->ict_tbl = NULL;
1156 trans_pcie->ict_tbl_dma = 0;
1162 * allocate dram shared table, it is an aligned memory
1163 * block of ICT_SIZE.
1164 * also reset all data related to ICT table interrupt.
1166 int iwl_alloc_isr_ict(struct iwl_trans *trans)
1168 struct iwl_trans_pcie *trans_pcie =
1169 IWL_TRANS_GET_PCIE_TRANS(trans);
1171 trans_pcie->ict_tbl =
1172 dma_alloc_coherent(trans->dev, ICT_SIZE,
1173 &trans_pcie->ict_tbl_dma,
1175 if (!trans_pcie->ict_tbl)
1178 /* just an API sanity check ... it is guaranteed to be aligned */
1179 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1180 iwl_free_isr_ict(trans);
1184 IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
1185 (unsigned long long)trans_pcie->ict_tbl_dma);
1187 IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
1189 /* reset table and index to all 0 */
1190 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1191 trans_pcie->ict_index = 0;
1193 /* add periodic RX interrupt */
1194 trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
1198 /* Device is going up inform it about using ICT interrupt table,
1199 * also we need to tell the driver to start using ICT interrupt.
1201 void iwl_reset_ict(struct iwl_trans *trans)
1204 unsigned long flags;
1205 struct iwl_trans_pcie *trans_pcie =
1206 IWL_TRANS_GET_PCIE_TRANS(trans);
1208 if (!trans_pcie->ict_tbl)
1211 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1212 iwl_disable_interrupts(trans);
1214 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1216 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1218 val |= CSR_DRAM_INT_TBL_ENABLE;
1219 val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1221 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1223 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1224 trans_pcie->use_ict = true;
1225 trans_pcie->ict_index = 0;
1226 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1227 iwl_enable_interrupts(trans);
1228 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1231 /* Device is going down disable ict interrupt usage */
1232 void iwl_disable_ict(struct iwl_trans *trans)
1234 struct iwl_trans_pcie *trans_pcie =
1235 IWL_TRANS_GET_PCIE_TRANS(trans);
1237 unsigned long flags;
1239 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1240 trans_pcie->use_ict = false;
1241 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1244 static irqreturn_t iwl_isr(int irq, void *data)
1246 struct iwl_trans *trans = data;
1247 struct iwl_trans_pcie *trans_pcie;
1248 u32 inta, inta_mask;
1249 unsigned long flags;
1250 #ifdef CONFIG_IWLWIFI_DEBUG
1256 trace_iwlwifi_dev_irq(trans->dev);
1258 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1260 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1262 /* Disable (but don't clear!) interrupts here to avoid
1263 * back-to-back ISRs and sporadic interrupts from our NIC.
1264 * If we have something to service, the tasklet will re-enable ints.
1265 * If we *don't* have something, we'll re-enable before leaving here. */
1266 inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */
1267 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1269 /* Discover which interrupts are active/pending */
1270 inta = iwl_read32(trans, CSR_INT);
1272 /* Ignore interrupt if there's nothing in NIC to service.
1273 * This may be due to IRQ shared with another device,
1274 * or due to sporadic interrupts thrown from our NIC. */
1276 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1280 if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1281 /* Hardware disappeared. It might have already raised
1283 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1287 #ifdef CONFIG_IWLWIFI_DEBUG
1288 if (iwl_have_debug_level(IWL_DL_ISR)) {
1289 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
1290 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
1291 "fh 0x%08x\n", inta, inta_mask, inta_fh);
1295 trans_pcie->inta |= inta;
1296 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1298 tasklet_schedule(&trans_pcie->irq_tasklet);
1299 else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1301 iwl_enable_interrupts(trans);
1304 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1308 /* re-enable interrupts here since we don't have anything to service. */
1309 /* only Re-enable if disabled by irq and no schedules tasklet. */
1310 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1312 iwl_enable_interrupts(trans);
1314 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1318 /* interrupt handler using ict table, with this interrupt driver will
1319 * stop using INTA register to get device's interrupt, reading this register
1320 * is expensive, device will write interrupts in ICT dram table, increment
1321 * index then will fire interrupt to driver, driver will OR all ICT table
1322 * entries from current index up to table entry with 0 value. the result is
1323 * the interrupt we need to service, driver will set the entries back to 0 and
1326 irqreturn_t iwl_isr_ict(int irq, void *data)
1328 struct iwl_trans *trans = data;
1329 struct iwl_trans_pcie *trans_pcie;
1330 u32 inta, inta_mask;
1333 unsigned long flags;
1338 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1340 /* dram interrupt table not set yet,
1341 * use legacy interrupt.
1343 if (!trans_pcie->use_ict)
1344 return iwl_isr(irq, data);
1346 trace_iwlwifi_dev_irq(trans->dev);
1348 spin_lock_irqsave(&trans_pcie->irq_lock, flags);
1350 /* Disable (but don't clear!) interrupts here to avoid
1351 * back-to-back ISRs and sporadic interrupts from our NIC.
1352 * If we have something to service, the tasklet will re-enable ints.
1353 * If we *don't* have something, we'll re-enable before leaving here.
1355 inta_mask = iwl_read32(trans, CSR_INT_MASK); /* just for debug */
1356 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1359 /* Ignore interrupt if there's nothing in NIC to service.
1360 * This may be due to IRQ shared with another device,
1361 * or due to sporadic interrupts thrown from our NIC. */
1362 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1363 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1365 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1370 * Collect all entries up to the first 0, starting from ict_index;
1371 * note we already read at ict_index.
1375 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1376 trans_pcie->ict_index, read);
1377 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1378 trans_pcie->ict_index =
1379 iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1381 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1382 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1386 /* We should not get this value, just ignore it. */
1387 if (val == 0xffffffff)
1391 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1392 * (bit 15 before shifting it to 31) to clear when using interrupt
1393 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1394 * so we use them to decide on the real state of the Rx bit.
1395 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1400 inta = (0xff & val) | ((0xff00 & val) << 16);
1401 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1402 inta, inta_mask, val);
1404 inta &= trans_pcie->inta_mask;
1405 trans_pcie->inta |= inta;
1407 /* iwl_irq_tasklet() will service interrupts and re-enable them */
1409 tasklet_schedule(&trans_pcie->irq_tasklet);
1410 else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1411 !trans_pcie->inta) {
1412 /* Allow interrupt if was disabled by this handler and
1413 * no tasklet was schedules, We should not enable interrupt,
1414 * tasklet will enable it.
1416 iwl_enable_interrupts(trans);
1419 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1423 /* re-enable interrupts here since we don't have anything to service.
1424 * only Re-enable if disabled by irq.
1426 if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1428 iwl_enable_interrupts(trans);
1430 spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);