drivers/net/wireless/iwlwifi/iwl-agn.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  31
  32 #include <linux/kernel.h>
  33 #include <linux/module.h>
  34 #include <linux/init.h>
  35 #include <linux/pci.h>
  36 #include <linux/pci-aspm.h>
  37 #include <linux/slab.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/delay.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/wireless.h>
  44 #include <linux/firmware.h>
  45 #include <linux/etherdevice.h>
  46 #include <linux/if_arp.h>
  47
  48 #include <net/mac80211.h>
  49
  50 #include <asm/div64.h>
  51
  52 #define DRV_NAME        "iwlagn"
  53
  54 #include "iwl-eeprom.h"
  55 #include "iwl-dev.h"
  56 #include "iwl-core.h"
  57 #include "iwl-io.h"
  58 #include "iwl-helpers.h"
  59 #include "iwl-sta.h"
  60 #include "iwl-agn-calib.h"
  61 #include "iwl-agn.h"
  62 #include "iwl-agn-led.h"
  63
  64
  65 /******************************************************************************
  66  *
  67  * module boiler plate
  68  *
  69  ******************************************************************************/
  70
  71 /*
  72  * module name, copyright, version, etc.
  73  */
  74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  75
  76 #ifdef CONFIG_IWLWIFI_DEBUG
  77 #define VD "d"
  78 #else
  79 #define VD
  80 #endif
  81
  82 #define DRV_VERSION     IWLWIFI_VERSION VD
  83
  84
  85 MODULE_DESCRIPTION(DRV_DESCRIPTION);
  86 MODULE_VERSION(DRV_VERSION);
  87 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  88 MODULE_LICENSE("GPL");
  89
  90 static int iwlagn_ant_coupling;
  91 static bool iwlagn_bt_ch_announce = 1;
  92
  93 void iwl_update_chain_flags(struct iwl_priv *priv)
  94 {
  95         struct iwl_rxon_context *ctx;
  96
  97         if (priv->cfg->ops->hcmd->set_rxon_chain) {
  98                 for_each_context(priv, ctx) {
  99                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 100                         if (ctx->active.rx_chain != ctx->staging.rx_chain)
 101                                 iwlcore_commit_rxon(priv, ctx);
 102                 }
 103         }
 104 }
 105
 106 static void iwl_clear_free_frames(struct iwl_priv *priv)
 107 {
 108         struct list_head *element;
 109
 110         IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
 111                        priv->frames_count);
 112
 113         while (!list_empty(&priv->free_frames)) {
 114                 element = priv->free_frames.next;
 115                 list_del(element);
 116                 kfree(list_entry(element, struct iwl_frame, list));
 117                 priv->frames_count--;
 118         }
 119
 120         if (priv->frames_count) {
 121                 IWL_WARN(priv, "%d frames still in use.  Did we lose one?\n",
 122                             priv->frames_count);
 123                 priv->frames_count = 0;
 124         }
 125 }
 126
 127 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
 128 {
 129         struct iwl_frame *frame;
 130         struct list_head *element;
 131         if (list_empty(&priv->free_frames)) {
 132                 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
 133                 if (!frame) {
 134                         IWL_ERR(priv, "Could not allocate frame!\n");
 135                         return NULL;
 136                 }
 137
 138                 priv->frames_count++;
 139                 return frame;
 140         }
 141
 142         element = priv->free_frames.next;
 143         list_del(element);
 144         return list_entry(element, struct iwl_frame, list);
 145 }
 146
 147 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
 148 {
 149         memset(frame, 0, sizeof(*frame));
 150         list_add(&frame->list, &priv->free_frames);
 151 }
 152
 153 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
 154                                  struct ieee80211_hdr *hdr,
 155                                  int left)
 156 {
 157         lockdep_assert_held(&priv->mutex);
 158
 159         if (!priv->beacon_skb)
 160                 return 0;
 161
 162         if (priv->beacon_skb->len > left)
 163                 return 0;
 164
 165         memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
 166
 167         return priv->beacon_skb->len;
 168 }
 169
 170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
 171 static void iwl_set_beacon_tim(struct iwl_priv *priv,
 172                                struct iwl_tx_beacon_cmd *tx_beacon_cmd,
 173                                u8 *beacon, u32 frame_size)
 174 {
 175         u16 tim_idx;
 176         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
 177
 178         /*
 179          * The index is relative to frame start but we start looking at the
 180          * variable-length part of the beacon.
 181          */
 182         tim_idx = mgmt->u.beacon.variable - beacon;
 183
 184         /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
 185         while ((tim_idx < (frame_size - 2)) &&
 186                         (beacon[tim_idx] != WLAN_EID_TIM))
 187                 tim_idx += beacon[tim_idx+1] + 2;
 188
 189         /* If TIM field was found, set variables */
 190         if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
 191                 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
 192                 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
 193         } else
 194                 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
 195 }
 196
 197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
 198                                        struct iwl_frame *frame)
 199 {
 200         struct iwl_tx_beacon_cmd *tx_beacon_cmd;
 201         u32 frame_size;
 202         u32 rate_flags;
 203         u32 rate;
 204         /*
 205          * We have to set up the TX command, the TX Beacon command, and the
 206          * beacon contents.
 207          */
 208
 209         lockdep_assert_held(&priv->mutex);
 210
 211         if (!priv->beacon_ctx) {
 212                 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
 213                 return 0;
 214         }
 215
 216         /* Initialize memory */
 217         tx_beacon_cmd = &frame->u.beacon;
 218         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
 219
 220         /* Set up TX beacon contents */
 221         frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
 222                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
 223         if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
 224                 return 0;
 225         if (!frame_size)
 226                 return 0;
 227
 228         /* Set up TX command fields */
 229         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
 230         tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
 231         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
 232         tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
 233                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
 234
 235         /* Set up TX beacon command fields */
 236         iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
 237                            frame_size);
 238
 239         /* Set up packet rate and flags */
 240         rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
 241         priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
 242                                               priv->hw_params.valid_tx_ant);
 243         rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
 244         if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
 245                 rate_flags |= RATE_MCS_CCK_MSK;
 246         tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
 247                         rate_flags);
 248
 249         return sizeof(*tx_beacon_cmd) + frame_size;
 250 }
 251
 252 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
 253 {
 254         struct iwl_frame *frame;
 255         unsigned int frame_size;
 256         int rc;
 257
 258         frame = iwl_get_free_frame(priv);
 259         if (!frame) {
 260                 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
 261                           "command.\n");
 262                 return -ENOMEM;
 263         }
 264
 265         frame_size = iwl_hw_get_beacon_cmd(priv, frame);
 266         if (!frame_size) {
 267                 IWL_ERR(priv, "Error configuring the beacon command\n");
 268                 iwl_free_frame(priv, frame);
 269                 return -EINVAL;
 270         }
 271
 272         rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
 273                               &frame->u.cmd[0]);
 274
 275         iwl_free_frame(priv, frame);
 276
 277         return rc;
 278 }
 279
 280 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
 281 {
 282         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 283
 284         dma_addr_t addr = get_unaligned_le32(&tb->lo);
 285         if (sizeof(dma_addr_t) > sizeof(u32))
 286                 addr |=
 287                 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
 288
 289         return addr;
 290 }
 291
 292 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
 293 {
 294         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 295
 296         return le16_to_cpu(tb->hi_n_len) >> 4;
 297 }
 298
 299 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
 300                                   dma_addr_t addr, u16 len)
 301 {
 302         struct iwl_tfd_tb *tb = &tfd->tbs[idx];
 303         u16 hi_n_len = len << 4;
 304
 305         put_unaligned_le32(addr, &tb->lo);
 306         if (sizeof(dma_addr_t) > sizeof(u32))
 307                 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
 308
 309         tb->hi_n_len = cpu_to_le16(hi_n_len);
 310
 311         tfd->num_tbs = idx + 1;
 312 }
 313
 314 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
 315 {
 316         return tfd->num_tbs & 0x1f;
 317 }
 318
 319 /**
 320  * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
 321  * @priv - driver private data
 322  * @txq - tx queue
 323  *
 324  * Does NOT advance any TFD circular buffer read/write indexes
 325  * Does NOT free the TFD itself (which is within circular buffer)
 326  */
 327 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 328 {
 329         struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
 330         struct iwl_tfd *tfd;
 331         struct pci_dev *dev = priv->pci_dev;
 332         int index = txq->q.read_ptr;
 333         int i;
 334         int num_tbs;
 335
 336         tfd = &tfd_tmp[index];
 337
 338         /* Sanity check on number of chunks */
 339         num_tbs = iwl_tfd_get_num_tbs(tfd);
 340
 341         if (num_tbs >= IWL_NUM_OF_TBS) {
 342                 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
 343                 /* @todo issue fatal error, it is quite serious situation */
 344                 return;
 345         }
 346
 347         /* Unmap tx_cmd */
 348         if (num_tbs)
 349                 pci_unmap_single(dev,
 350                                 dma_unmap_addr(&txq->meta[index], mapping),
 351                                 dma_unmap_len(&txq->meta[index], len),
 352                                 PCI_DMA_BIDIRECTIONAL);
 353
 354         /* Unmap chunks, if any. */
 355         for (i = 1; i < num_tbs; i++)
 356                 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
 357                                 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
 358
 359         /* free SKB */
 360         if (txq->txb) {
 361                 struct sk_buff *skb;
 362
 363                 skb = txq->txb[txq->q.read_ptr].skb;
 364
 365                 /* can be called from irqs-disabled context */
 366                 if (skb) {
 367                         dev_kfree_skb_any(skb);
 368                         txq->txb[txq->q.read_ptr].skb = NULL;
 369                 }
 370         }
 371 }
 372
 373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 374                                  struct iwl_tx_queue *txq,
 375                                  dma_addr_t addr, u16 len,
 376                                  u8 reset, u8 pad)
 377 {
 378         struct iwl_queue *q;
 379         struct iwl_tfd *tfd, *tfd_tmp;
 380         u32 num_tbs;
 381
 382         q = &txq->q;
 383         tfd_tmp = (struct iwl_tfd *)txq->tfds;
 384         tfd = &tfd_tmp[q->write_ptr];
 385
 386         if (reset)
 387                 memset(tfd, 0, sizeof(*tfd));
 388
 389         num_tbs = iwl_tfd_get_num_tbs(tfd);
 390
 391         /* Each TFD can point to a maximum 20 Tx buffers */
 392         if (num_tbs >= IWL_NUM_OF_TBS) {
 393                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 394                           IWL_NUM_OF_TBS);
 395                 return -EINVAL;
 396         }
 397
 398         BUG_ON(addr & ~DMA_BIT_MASK(36));
 399         if (unlikely(addr & ~IWL_TX_DMA_MASK))
 400                 IWL_ERR(priv, "Unaligned address = %llx\n",
 401                           (unsigned long long)addr);
 402
 403         iwl_tfd_set_tb(tfd, num_tbs, addr, len);
 404
 405         return 0;
 406 }
 407
 408 /*
 409  * Tell nic where to find circular buffer of Tx Frame Descriptors for
 410  * given Tx queue, and enable the DMA channel used for that queue.
 411  *
 412  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
 413  * channels supported in hardware.
 414  */
 415 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
 416                          struct iwl_tx_queue *txq)
 417 {
 418         int txq_id = txq->q.id;
 419
 420         /* Circular buffer (TFD queue in DRAM) physical base address */
 421         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
 422                              txq->q.dma_addr >> 8);
 423
 424         return 0;
 425 }
 426
 427 /******************************************************************************
 428  *
 429  * Generic RX handler implementations
 430  *
 431  ******************************************************************************/
 432 static void iwl_rx_reply_alive(struct iwl_priv *priv,
 433                                 struct iwl_rx_mem_buffer *rxb)
 434 {
 435         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 436         struct iwl_alive_resp *palive;
 437         struct delayed_work *pwork;
 438
 439         palive = &pkt->u.alive_frame;
 440
 441         IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
 442                        "0x%01X 0x%01X\n",
 443                        palive->is_valid, palive->ver_type,
 444                        palive->ver_subtype);
 445
 446         if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
 447                 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
 448                 memcpy(&priv->card_alive_init,
 449                        &pkt->u.alive_frame,
 450                        sizeof(struct iwl_init_alive_resp));
 451                 pwork = &priv->init_alive_start;
 452         } else {
 453                 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
 454                 memcpy(&priv->card_alive, &pkt->u.alive_frame,
 455                        sizeof(struct iwl_alive_resp));
 456                 pwork = &priv->alive_start;
 457         }
 458
 459         /* We delay the ALIVE response by 5ms to
 460          * give the HW RF Kill time to activate... */
 461         if (palive->is_valid == UCODE_VALID_OK)
 462                 queue_delayed_work(priv->workqueue, pwork,
 463                                    msecs_to_jiffies(5));
 464         else {
 465                 IWL_WARN(priv, "%s uCode did not respond OK.\n",
 466                         (palive->ver_subtype == INITIALIZE_SUBTYPE) ?
 467                         "init" : "runtime");
 468                 /*
 469                  * If fail to load init uCode,
 470                  * let's try to load the init uCode again.
 471                  * We should not get into this situation, but if it
 472                  * does happen, we should not move on and loading "runtime"
 473                  * without proper calibrate the device.
 474                  */
 475                 if (palive->ver_subtype == INITIALIZE_SUBTYPE)
 476                         priv->ucode_type = UCODE_NONE;
 477                 queue_work(priv->workqueue, &priv->restart);
 478         }
 479 }
 480
 481 static void iwl_bg_beacon_update(struct work_struct *work)
 482 {
 483         struct iwl_priv *priv =
 484                 container_of(work, struct iwl_priv, beacon_update);
 485         struct sk_buff *beacon;
 486
 487         mutex_lock(&priv->mutex);
 488         if (!priv->beacon_ctx) {
 489                 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
 490                 goto out;
 491         }
 492
 493         if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
 494                 /*
 495                  * The ucode will send beacon notifications even in
 496                  * IBSS mode, but we don't want to process them. But
 497                  * we need to defer the type check to here due to
 498                  * requiring locking around the beacon_ctx access.
 499                  */
 500                 goto out;
 501         }
 502
 503         /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
 504         beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
 505         if (!beacon) {
 506                 IWL_ERR(priv, "update beacon failed -- keeping old\n");
 507                 goto out;
 508         }
 509
 510         /* new beacon skb is allocated every time; dispose previous.*/
 511         dev_kfree_skb(priv->beacon_skb);
 512
 513         priv->beacon_skb = beacon;
 514
 515         iwlagn_send_beacon_cmd(priv);
 516  out:
 517         mutex_unlock(&priv->mutex);
 518 }
 519
 520 static void iwl_bg_bt_runtime_config(struct work_struct *work)
 521 {
 522         struct iwl_priv *priv =
 523                 container_of(work, struct iwl_priv, bt_runtime_config);
 524
 525         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 526                 return;
 527
 528         /* dont send host command if rf-kill is on */
 529         if (!iwl_is_ready_rf(priv))
 530                 return;
 531         priv->cfg->ops->hcmd->send_bt_config(priv);
 532 }
 533
 534 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
 535 {
 536         struct iwl_priv *priv =
 537                 container_of(work, struct iwl_priv, bt_full_concurrency);
 538         struct iwl_rxon_context *ctx;
 539
 540         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 541                 return;
 542
 543         /* dont send host command if rf-kill is on */
 544         if (!iwl_is_ready_rf(priv))
 545                 return;
 546
 547         IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
 548                        priv->bt_full_concurrent ?
 549                        "full concurrency" : "3-wire");
 550
 551         /*
 552          * LQ & RXON updated cmds must be sent before BT Config cmd
 553          * to avoid 3-wire collisions
 554          */
 555         mutex_lock(&priv->mutex);
 556         for_each_context(priv, ctx) {
 557                 if (priv->cfg->ops->hcmd->set_rxon_chain)
 558                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
 559                 iwlcore_commit_rxon(priv, ctx);
 560         }
 561         mutex_unlock(&priv->mutex);
 562
 563         priv->cfg->ops->hcmd->send_bt_config(priv);
 564 }
 565
 566 /**
 567  * iwl_bg_statistics_periodic - Timer callback to queue statistics
 568  *
 569  * This callback is provided in order to send a statistics request.
 570  *
 571  * This timer function is continually reset to execute within
 572  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 573  * was received.  We need to ensure we receive the statistics in order
 574  * to update the temperature used for calibrating the TXPOWER.
 575  */
 576 static void iwl_bg_statistics_periodic(unsigned long data)
 577 {
 578         struct iwl_priv *priv = (struct iwl_priv *)data;
 579
 580         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 581                 return;
 582
 583         /* dont send host command if rf-kill is on */
 584         if (!iwl_is_ready_rf(priv))
 585                 return;
 586
 587         iwl_send_statistics_request(priv, CMD_ASYNC, false);
 588 }
 589
 590
 591 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
 592                                         u32 start_idx, u32 num_events,
 593                                         u32 mode)
 594 {
 595         u32 i;
 596         u32 ptr;        /* SRAM byte address of log data */
 597         u32 ev, time, data; /* event log data */
 598         unsigned long reg_flags;
 599
 600         if (mode == 0)
 601                 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
 602         else
 603                 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
 604
 605         /* Make sure device is powered up for SRAM reads */
 606         spin_lock_irqsave(&priv->reg_lock, reg_flags);
 607         if (iwl_grab_nic_access(priv)) {
 608                 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 609                 return;
 610         }
 611
 612         /* Set starting address; reads will auto-increment */
 613         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
 614         rmb();
 615
 616         /*
 617          * "time" is actually "data" for mode 0 (no timestamp).
 618          * place event id # at far right for easier visual parsing.
 619          */
 620         for (i = 0; i < num_events; i++) {
 621                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 622                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 623                 if (mode == 0) {
 624                         trace_iwlwifi_dev_ucode_cont_event(priv,
 625                                                         0, time, ev);
 626                 } else {
 627                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 628                         trace_iwlwifi_dev_ucode_cont_event(priv,
 629                                                 time, data, ev);
 630                 }
 631         }
 632         /* Allow device to power down */
 633         iwl_release_nic_access(priv);
 634         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
 635 }
 636
 637 static void iwl_continuous_event_trace(struct iwl_priv *priv)
 638 {
 639         u32 capacity;   /* event log capacity in # entries */
 640         u32 base;       /* SRAM byte address of event log header */
 641         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
 642         u32 num_wraps;  /* # times uCode wrapped to top of log */
 643         u32 next_entry; /* index of next entry to be written by uCode */
 644
 645         if (priv->ucode_type == UCODE_INIT)
 646                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
 647         else
 648                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 649         if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
 650                 capacity = iwl_read_targ_mem(priv, base);
 651                 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
 652                 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
 653                 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
 654         } else
 655                 return;
 656
 657         if (num_wraps == priv->event_log.num_wraps) {
 658                 iwl_print_cont_event_trace(priv,
 659                                        base, priv->event_log.next_entry,
 660                                        next_entry - priv->event_log.next_entry,
 661                                        mode);
 662                 priv->event_log.non_wraps_count++;
 663         } else {
 664                 if ((num_wraps - priv->event_log.num_wraps) > 1)
 665                         priv->event_log.wraps_more_count++;
 666                 else
 667                         priv->event_log.wraps_once_count++;
 668                 trace_iwlwifi_dev_ucode_wrap_event(priv,
 669                                 num_wraps - priv->event_log.num_wraps,
 670                                 next_entry, priv->event_log.next_entry);
 671                 if (next_entry < priv->event_log.next_entry) {
 672                         iwl_print_cont_event_trace(priv, base,
 673                                priv->event_log.next_entry,
 674                                capacity - priv->event_log.next_entry,
 675                                mode);
 676
 677                         iwl_print_cont_event_trace(priv, base, 0,
 678                                 next_entry, mode);
 679                 } else {
 680                         iwl_print_cont_event_trace(priv, base,
 681                                next_entry, capacity - next_entry,
 682                                mode);
 683
 684                         iwl_print_cont_event_trace(priv, base, 0,
 685                                 next_entry, mode);
 686                 }
 687         }
 688         priv->event_log.num_wraps = num_wraps;
 689         priv->event_log.next_entry = next_entry;
 690 }
 691
 692 /**
 693  * iwl_bg_ucode_trace - Timer callback to log ucode event
 694  *
 695  * The timer is continually set to execute every
 696  * UCODE_TRACE_PERIOD milliseconds after the last timer expired
 697  * this function is to perform continuous uCode event logging operation
 698  * if enabled
 699  */
 700 static void iwl_bg_ucode_trace(unsigned long data)
 701 {
 702         struct iwl_priv *priv = (struct iwl_priv *)data;
 703
 704         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 705                 return;
 706
 707         if (priv->event_log.ucode_trace) {
 708                 iwl_continuous_event_trace(priv);
 709                 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
 710                 mod_timer(&priv->ucode_trace,
 711                          jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
 712         }
 713 }
 714
 715 static void iwlagn_rx_beacon_notif(struct iwl_priv *priv,
 716                                    struct iwl_rx_mem_buffer *rxb)
 717 {
 718         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 719         struct iwlagn_beacon_notif *beacon = (void *)pkt->u.raw;
 720 #ifdef CONFIG_IWLWIFI_DEBUG
 721         u16 status = le16_to_cpu(beacon->beacon_notify_hdr.status.status);
 722         u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
 723
 724         IWL_DEBUG_RX(priv, "beacon status %#x, retries:%d ibssmgr:%d "
 725                 "tsf:0x%.8x%.8x rate:%d\n",
 726                 status & TX_STATUS_MSK,
 727                 beacon->beacon_notify_hdr.failure_frame,
 728                 le32_to_cpu(beacon->ibss_mgr_status),
 729                 le32_to_cpu(beacon->high_tsf),
 730                 le32_to_cpu(beacon->low_tsf), rate);
 731 #endif
 732
 733         priv->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status);
 734
 735         if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
 736                 queue_work(priv->workqueue, &priv->beacon_update);
 737 }
 738
 739 /* Handle notification from uCode that card's power state is changing
 740  * due to software, hardware, or critical temperature RFKILL */
 741 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
 742                                     struct iwl_rx_mem_buffer *rxb)
 743 {
 744         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 745         u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
 746         unsigned long status = priv->status;
 747
 748         IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s CT:%s\n",
 749                           (flags & HW_CARD_DISABLED) ? "Kill" : "On",
 750                           (flags & SW_CARD_DISABLED) ? "Kill" : "On",
 751                           (flags & CT_CARD_DISABLED) ?
 752                           "Reached" : "Not reached");
 753
 754         if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
 755                      CT_CARD_DISABLED)) {
 756
 757                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
 758                             CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 759
 760                 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 761                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 762
 763                 if (!(flags & RXON_CARD_DISABLED)) {
 764                         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
 765                                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 766                         iwl_write_direct32(priv, HBUS_TARG_MBX_C,
 767                                         HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
 768                 }
 769                 if (flags & CT_CARD_DISABLED)
 770                         iwl_tt_enter_ct_kill(priv);
 771         }
 772         if (!(flags & CT_CARD_DISABLED))
 773                 iwl_tt_exit_ct_kill(priv);
 774
 775         if (flags & HW_CARD_DISABLED)
 776                 set_bit(STATUS_RF_KILL_HW, &priv->status);
 777         else
 778                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
 779
 780
 781         if (!(flags & RXON_CARD_DISABLED))
 782                 iwl_scan_cancel(priv);
 783
 784         if ((test_bit(STATUS_RF_KILL_HW, &status) !=
 785              test_bit(STATUS_RF_KILL_HW, &priv->status)))
 786                 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
 787                         test_bit(STATUS_RF_KILL_HW, &priv->status));
 788         else
 789                 wake_up_interruptible(&priv->wait_command_queue);
 790 }
 791
 792 static void iwl_bg_tx_flush(struct work_struct *work)
 793 {
 794         struct iwl_priv *priv =
 795                 container_of(work, struct iwl_priv, tx_flush);
 796
 797         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 798                 return;
 799
 800         /* do nothing if rf-kill is on */
 801         if (!iwl_is_ready_rf(priv))
 802                 return;
 803
 804         if (priv->cfg->ops->lib->txfifo_flush) {
 805                 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
 806                 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
 807         }
 808 }
 809
 810 /**
 811  * iwl_setup_rx_handlers - Initialize Rx handler callbacks
 812  *
 813  * Setup the RX handlers for each of the reply types sent from the uCode
 814  * to the host.
 815  *
 816  * This function chains into the hardware specific files for them to setup
 817  * any hardware specific handlers as well.
 818  */
 819 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
 820 {
 821         priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
 822         priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
 823         priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
 824         priv->rx_handlers[SPECTRUM_MEASURE_NOTIFICATION] =
 825                         iwl_rx_spectrum_measure_notif;
 826         priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
 827         priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
 828             iwl_rx_pm_debug_statistics_notif;
 829         priv->rx_handlers[BEACON_NOTIFICATION] = iwlagn_rx_beacon_notif;
 830
 831         /*
 832          * The same handler is used for both the REPLY to a discrete
 833          * statistics request from the host as well as for the periodic
 834          * statistics notifications (after received beacons) from the uCode.
 835          */
 836         priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
 837         priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
 838
 839         iwl_setup_rx_scan_handlers(priv);
 840
 841         /* status change handler */
 842         priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
 843
 844         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
 845             iwl_rx_missed_beacon_notif;
 846         /* Rx handlers */
 847         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwlagn_rx_reply_rx_phy;
 848         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwlagn_rx_reply_rx;
 849         /* block ack */
 850         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwlagn_rx_reply_compressed_ba;
 851         /* Set up hardware specific Rx handlers */
 852         priv->cfg->ops->lib->rx_handler_setup(priv);
 853 }
 854
 855 /**
 856  * iwl_rx_handle - Main entry function for receiving responses from uCode
 857  *
 858  * Uses the priv->rx_handlers callback function array to invoke
 859  * the appropriate handlers, including command responses,
 860  * frame-received notifications, and other notifications.
 861  */
 862 static void iwl_rx_handle(struct iwl_priv *priv)
 863 {
 864         struct iwl_rx_mem_buffer *rxb;
 865         struct iwl_rx_packet *pkt;
 866         struct iwl_rx_queue *rxq = &priv->rxq;
 867         u32 r, i;
 868         int reclaim;
 869         unsigned long flags;
 870         u8 fill_rx = 0;
 871         u32 count = 8;
 872         int total_empty;
 873
 874         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 875          * buffer that the driver may process (last buffer filled by ucode). */
 876         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 877         i = rxq->read;
 878
 879         /* Rx interrupt, but nothing sent from uCode */
 880         if (i == r)
 881                 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
 882
 883         /* calculate total frames need to be restock after handling RX */
 884         total_empty = r - rxq->write_actual;
 885         if (total_empty < 0)
 886                 total_empty += RX_QUEUE_SIZE;
 887
 888         if (total_empty > (RX_QUEUE_SIZE / 2))
 889                 fill_rx = 1;
 890
 891         while (i != r) {
 892                 int len;
 893
 894                 rxb = rxq->queue[i];
 895
 896                 /* If an RXB doesn't have a Rx queue slot associated with it,
 897                  * then a bug has been introduced in the queue refilling
 898                  * routines -- catch it here */
 899                 BUG_ON(rxb == NULL);
 900
 901                 rxq->queue[i] = NULL;
 902
 903                 pci_unmap_page(priv->pci_dev, rxb->page_dma,
 904                                PAGE_SIZE << priv->hw_params.rx_page_order,
 905                                PCI_DMA_FROMDEVICE);
 906                 pkt = rxb_addr(rxb);
 907
 908                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 909                 len += sizeof(u32); /* account for status word */
 910                 trace_iwlwifi_dev_rx(priv, pkt, len);
 911
 912                 /* Reclaim a command buffer only if this packet is a response
 913                  *   to a (driver-originated) command.
 914                  * If the packet (e.g. Rx frame) originated from uCode,
 915                  *   there is no command buffer to reclaim.
 916                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 917                  *   but apparently a few don't get set; catch them here. */
 918                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
 919                         (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
 920                         (pkt->hdr.cmd != REPLY_RX) &&
 921                         (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
 922                         (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
 923                         (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
 924                         (pkt->hdr.cmd != REPLY_TX);
 925
 926                 /*
 927                  * Do the notification wait before RX handlers so
 928                  * even if the RX handler consumes the RXB we have
 929                  * access to it in the notification wait entry.
 930                  */
 931                 if (!list_empty(&priv->_agn.notif_waits)) {
 932                         struct iwl_notification_wait *w;
 933
 934                         spin_lock(&priv->_agn.notif_wait_lock);
 935                         list_for_each_entry(w, &priv->_agn.notif_waits, list) {
 936                                 if (w->cmd == pkt->hdr.cmd) {
 937                                         w->triggered = true;
 938                                         if (w->fn)
 939                                                 w->fn(priv, pkt);
 940                                 }
 941                         }
 942                         spin_unlock(&priv->_agn.notif_wait_lock);
 943
 944                         wake_up_all(&priv->_agn.notif_waitq);
 945                 }
 946
 947                 /* Based on type of command response or notification,
 948                  *   handle those that need handling via function in
 949                  *   rx_handlers table.  See iwl_setup_rx_handlers() */
 950                 if (priv->rx_handlers[pkt->hdr.cmd]) {
 951                         IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
 952                                 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
 953                         priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
 954                         priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
 955                 } else {
 956                         /* No handling needed */
 957                         IWL_DEBUG_RX(priv,
 958                                 "r %d i %d No handler needed for %s, 0x%02x\n",
 959                                 r, i, get_cmd_string(pkt->hdr.cmd),
 960                                 pkt->hdr.cmd);
 961                 }
 962
 963                 /*
 964                  * XXX: After here, we should always check rxb->page
 965                  * against NULL before touching it or its virtual
 966                  * memory (pkt). Because some rx_handler might have
 967                  * already taken or freed the pages.
 968                  */
 969
 970                 if (reclaim) {
 971                         /* Invoke any callbacks, transfer the buffer to caller,
 972                          * and fire off the (possibly) blocking iwl_send_cmd()
 973                          * as we reclaim the driver command queue */
 974                         if (rxb->page)
 975                                 iwl_tx_cmd_complete(priv, rxb);
 976                         else
 977                                 IWL_WARN(priv, "Claim null rxb?\n");
 978                 }
 979
 980                 /* Reuse the page if possible. For notification packets and
 981                  * SKBs that fail to Rx correctly, add them back into the
 982                  * rx_free list for reuse later. */
 983                 spin_lock_irqsave(&rxq->lock, flags);
 984                 if (rxb->page != NULL) {
 985                         rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
 986                                 0, PAGE_SIZE << priv->hw_params.rx_page_order,
 987                                 PCI_DMA_FROMDEVICE);
 988                         list_add_tail(&rxb->list, &rxq->rx_free);
 989                         rxq->free_count++;
 990                 } else
 991                         list_add_tail(&rxb->list, &rxq->rx_used);
 992
 993                 spin_unlock_irqrestore(&rxq->lock, flags);
 994
 995                 i = (i + 1) & RX_QUEUE_MASK;
 996                 /* If there are a lot of unused frames,
 997                  * restock the Rx queue so ucode wont assert. */
 998                 if (fill_rx) {
 999                         count++;
1000                         if (count >= 8) {
1001                                 rxq->read = i;
1002                                 iwlagn_rx_replenish_now(priv);
1003                                 count = 0;
1004                         }
1005                 }
1006         }
1007
1008         /* Backtrack one entry */
1009         rxq->read = i;
1010         if (fill_rx)
1011                 iwlagn_rx_replenish_now(priv);
1012         else
1013                 iwlagn_rx_queue_restock(priv);
1014 }
1015
1016 /* call this function to flush any scheduled tasklet */
1017 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
1018 {
1019         /* wait to make sure we flush pending tasklet*/
1020         synchronize_irq(priv->pci_dev->irq);
1021         tasklet_kill(&priv->irq_tasklet);
1022 }
1023
1024 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
1025 {
1026         u32 inta, handled = 0;
1027         u32 inta_fh;
1028         unsigned long flags;
1029         u32 i;
1030 #ifdef CONFIG_IWLWIFI_DEBUG
1031         u32 inta_mask;
1032 #endif
1033
1034         spin_lock_irqsave(&priv->lock, flags);
1035
1036         /* Ack/clear/reset pending uCode interrupts.
1037          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1038          *  and will clear only when CSR_FH_INT_STATUS gets cleared. */
1039         inta = iwl_read32(priv, CSR_INT);
1040         iwl_write32(priv, CSR_INT, inta);
1041
1042         /* Ack/clear/reset pending flow-handler (DMA) interrupts.
1043          * Any new interrupts that happen after this, either while we're
1044          * in this tasklet, or later, will show up in next ISR/tasklet. */
1045         inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1046         iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
1047
1048 #ifdef CONFIG_IWLWIFI_DEBUG
1049         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1050                 /* just for debug */
1051                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1052                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
1053                               inta, inta_mask, inta_fh);
1054         }
1055 #endif
1056
1057         spin_unlock_irqrestore(&priv->lock, flags);
1058
1059         /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
1060          * atomic, make sure that inta covers all the interrupts that
1061          * we've discovered, even if FH interrupt came in just after
1062          * reading CSR_INT. */
1063         if (inta_fh & CSR49_FH_INT_RX_MASK)
1064                 inta |= CSR_INT_BIT_FH_RX;
1065         if (inta_fh & CSR49_FH_INT_TX_MASK)
1066                 inta |= CSR_INT_BIT_FH_TX;
1067
1068         /* Now service all interrupt bits discovered above. */
1069         if (inta & CSR_INT_BIT_HW_ERR) {
1070                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1071
1072                 /* Tell the device to stop sending interrupts */
1073                 iwl_disable_interrupts(priv);
1074
1075                 priv->isr_stats.hw++;
1076                 iwl_irq_handle_error(priv);
1077
1078                 handled |= CSR_INT_BIT_HW_ERR;
1079
1080                 return;
1081         }
1082
1083 #ifdef CONFIG_IWLWIFI_DEBUG
1084         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1085                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1086                 if (inta & CSR_INT_BIT_SCD) {
1087                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1088                                       "the frame/frames.\n");
1089                         priv->isr_stats.sch++;
1090                 }
1091
1092                 /* Alive notification via Rx interrupt will do the real work */
1093                 if (inta & CSR_INT_BIT_ALIVE) {
1094                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1095                         priv->isr_stats.alive++;
1096                 }
1097         }
1098 #endif
1099         /* Safely ignore these bits for debug checks below */
1100         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1101
1102         /* HW RF KILL switch toggled */
1103         if (inta & CSR_INT_BIT_RF_KILL) {
1104                 int hw_rf_kill = 0;
1105                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1106                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1107                         hw_rf_kill = 1;
1108
1109                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1110                                 hw_rf_kill ? "disable radio" : "enable radio");
1111
1112                 priv->isr_stats.rfkill++;
1113
1114                 /* driver only loads ucode once setting the interface up.
1115                  * the driver allows loading the ucode even if the radio
1116                  * is killed. Hence update the killswitch state here. The
1117                  * rfkill handler will care about restarting if needed.
1118                  */
1119                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1120                         if (hw_rf_kill)
1121                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1122                         else
1123                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1124                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1125                 }
1126
1127                 handled |= CSR_INT_BIT_RF_KILL;
1128         }
1129
1130         /* Chip got too hot and stopped itself */
1131         if (inta & CSR_INT_BIT_CT_KILL) {
1132                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1133                 priv->isr_stats.ctkill++;
1134                 handled |= CSR_INT_BIT_CT_KILL;
1135         }
1136
1137         /* Error detected by uCode */
1138         if (inta & CSR_INT_BIT_SW_ERR) {
1139                 IWL_ERR(priv, "Microcode SW error detected. "
1140                         " Restarting 0x%X.\n", inta);
1141                 priv->isr_stats.sw++;
1142                 iwl_irq_handle_error(priv);
1143                 handled |= CSR_INT_BIT_SW_ERR;
1144         }
1145
1146         /*
1147          * uCode wakes up after power-down sleep.
1148          * Tell device about any new tx or host commands enqueued,
1149          * and about any Rx buffers made available while asleep.
1150          */
1151         if (inta & CSR_INT_BIT_WAKEUP) {
1152                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1153                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1154                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1155                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1156                 priv->isr_stats.wakeup++;
1157                 handled |= CSR_INT_BIT_WAKEUP;
1158         }
1159
1160         /* All uCode command responses, including Tx command responses,
1161          * Rx "responses" (frame-received notification), and other
1162          * notifications from uCode come through here*/
1163         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1164                 iwl_rx_handle(priv);
1165                 priv->isr_stats.rx++;
1166                 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1167         }
1168
1169         /* This "Tx" DMA channel is used only for loading uCode */
1170         if (inta & CSR_INT_BIT_FH_TX) {
1171                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1172                 priv->isr_stats.tx++;
1173                 handled |= CSR_INT_BIT_FH_TX;
1174                 /* Wake up uCode load routine, now that load is complete */
1175                 priv->ucode_write_complete = 1;
1176                 wake_up_interruptible(&priv->wait_command_queue);
1177         }
1178
1179         if (inta & ~handled) {
1180                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1181                 priv->isr_stats.unhandled++;
1182         }
1183
1184         if (inta & ~(priv->inta_mask)) {
1185                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1186                          inta & ~priv->inta_mask);
1187                 IWL_WARN(priv, "   with FH_INT = 0x%08x\n", inta_fh);
1188         }
1189
1190         /* Re-enable all interrupts */
1191         /* only Re-enable if disabled by irq */
1192         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1193                 iwl_enable_interrupts(priv);
1194         /* Re-enable RF_KILL if it occurred */
1195         else if (handled & CSR_INT_BIT_RF_KILL)
1196                 iwl_enable_rfkill_int(priv);
1197
1198 #ifdef CONFIG_IWLWIFI_DEBUG
1199         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1200                 inta = iwl_read32(priv, CSR_INT);
1201                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1202                 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1203                 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1204                         "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1205         }
1206 #endif
1207 }
1208
1209 /* tasklet for iwlagn interrupt */
1210 static void iwl_irq_tasklet(struct iwl_priv *priv)
1211 {
1212         u32 inta = 0;
1213         u32 handled = 0;
1214         unsigned long flags;
1215         u32 i;
1216 #ifdef CONFIG_IWLWIFI_DEBUG
1217         u32 inta_mask;
1218 #endif
1219
1220         spin_lock_irqsave(&priv->lock, flags);
1221
1222         /* Ack/clear/reset pending uCode interrupts.
1223          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1224          */
1225         /* There is a hardware bug in the interrupt mask function that some
1226          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1227          * they are disabled in the CSR_INT_MASK register. Furthermore the
1228          * ICT interrupt handling mechanism has another bug that might cause
1229          * these unmasked interrupts fail to be detected. We workaround the
1230          * hardware bugs here by ACKing all the possible interrupts so that
1231          * interrupt coalescing can still be achieved.
1232          */
1233         iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
1234
1235         inta = priv->_agn.inta;
1236
1237 #ifdef CONFIG_IWLWIFI_DEBUG
1238         if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1239                 /* just for debug */
1240                 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1241                 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1242                                 inta, inta_mask);
1243         }
1244 #endif
1245
1246         spin_unlock_irqrestore(&priv->lock, flags);
1247
1248         /* saved interrupt in inta variable now we can reset priv->_agn.inta */
1249         priv->_agn.inta = 0;
1250
1251         /* Now service all interrupt bits discovered above. */
1252         if (inta & CSR_INT_BIT_HW_ERR) {
1253                 IWL_ERR(priv, "Hardware error detected.  Restarting.\n");
1254
1255                 /* Tell the device to stop sending interrupts */
1256                 iwl_disable_interrupts(priv);
1257
1258                 priv->isr_stats.hw++;
1259                 iwl_irq_handle_error(priv);
1260
1261                 handled |= CSR_INT_BIT_HW_ERR;
1262
1263                 return;
1264         }
1265
1266 #ifdef CONFIG_IWLWIFI_DEBUG
1267         if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1268                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1269                 if (inta & CSR_INT_BIT_SCD) {
1270                         IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1271                                       "the frame/frames.\n");
1272                         priv->isr_stats.sch++;
1273                 }
1274
1275                 /* Alive notification via Rx interrupt will do the real work */
1276                 if (inta & CSR_INT_BIT_ALIVE) {
1277                         IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1278                         priv->isr_stats.alive++;
1279                 }
1280         }
1281 #endif
1282         /* Safely ignore these bits for debug checks below */
1283         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1284
1285         /* HW RF KILL switch toggled */
1286         if (inta & CSR_INT_BIT_RF_KILL) {
1287                 int hw_rf_kill = 0;
1288                 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1289                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1290                         hw_rf_kill = 1;
1291
1292                 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1293                                 hw_rf_kill ? "disable radio" : "enable radio");
1294
1295                 priv->isr_stats.rfkill++;
1296
1297                 /* driver only loads ucode once setting the interface up.
1298                  * the driver allows loading the ucode even if the radio
1299                  * is killed. Hence update the killswitch state here. The
1300                  * rfkill handler will care about restarting if needed.
1301                  */
1302                 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1303                         if (hw_rf_kill)
1304                                 set_bit(STATUS_RF_KILL_HW, &priv->status);
1305                         else
1306                                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1307                         wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1308                 }
1309
1310                 handled |= CSR_INT_BIT_RF_KILL;
1311         }
1312
1313         /* Chip got too hot and stopped itself */
1314         if (inta & CSR_INT_BIT_CT_KILL) {
1315                 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1316                 priv->isr_stats.ctkill++;
1317                 handled |= CSR_INT_BIT_CT_KILL;
1318         }
1319
1320         /* Error detected by uCode */
1321         if (inta & CSR_INT_BIT_SW_ERR) {
1322                 IWL_ERR(priv, "Microcode SW error detected. "
1323                         " Restarting 0x%X.\n", inta);
1324                 priv->isr_stats.sw++;
1325                 iwl_irq_handle_error(priv);
1326                 handled |= CSR_INT_BIT_SW_ERR;
1327         }
1328
1329         /* uCode wakes up after power-down sleep */
1330         if (inta & CSR_INT_BIT_WAKEUP) {
1331                 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1332                 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1333                 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1334                         iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1335
1336                 priv->isr_stats.wakeup++;
1337
1338                 handled |= CSR_INT_BIT_WAKEUP;
1339         }
1340
1341         /* All uCode command responses, including Tx command responses,
1342          * Rx "responses" (frame-received notification), and other
1343          * notifications from uCode come through here*/
1344         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1345                         CSR_INT_BIT_RX_PERIODIC)) {
1346                 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1347                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1348                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1349                         iwl_write32(priv, CSR_FH_INT_STATUS,
1350                                         CSR49_FH_INT_RX_MASK);
1351                 }
1352                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1353                         handled |= CSR_INT_BIT_RX_PERIODIC;
1354                         iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1355                 }
1356                 /* Sending RX interrupt require many steps to be done in the
1357                  * the device:
1358                  * 1- write interrupt to current index in ICT table.
1359                  * 2- dma RX frame.
1360                  * 3- update RX shared data to indicate last write index.
1361                  * 4- send interrupt.
1362                  * This could lead to RX race, driver could receive RX interrupt
1363                  * but the shared data changes does not reflect this;
1364                  * periodic interrupt will detect any dangling Rx activity.
1365                  */
1366
1367                 /* Disable periodic interrupt; we use it as just a one-shot. */
1368                 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1369                             CSR_INT_PERIODIC_DIS);
1370                 iwl_rx_handle(priv);
1371
1372                 /*
1373                  * Enable periodic interrupt in 8 msec only if we received
1374                  * real RX interrupt (instead of just periodic int), to catch
1375                  * any dangling Rx interrupt.  If it was just the periodic
1376                  * interrupt, there was no dangling Rx activity, and no need
1377                  * to extend the periodic interrupt; one-shot is enough.
1378                  */
1379                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1380                         iwl_write8(priv, CSR_INT_PERIODIC_REG,
1381                                     CSR_INT_PERIODIC_ENA);
1382
1383                 priv->isr_stats.rx++;
1384         }
1385
1386         /* This "Tx" DMA channel is used only for loading uCode */
1387         if (inta & CSR_INT_BIT_FH_TX) {
1388                 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1389                 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1390                 priv->isr_stats.tx++;
1391                 handled |= CSR_INT_BIT_FH_TX;
1392                 /* Wake up uCode load routine, now that load is complete */
1393                 priv->ucode_write_complete = 1;
1394                 wake_up_interruptible(&priv->wait_command_queue);
1395         }
1396
1397         if (inta & ~handled) {
1398                 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1399                 priv->isr_stats.unhandled++;
1400         }
1401
1402         if (inta & ~(priv->inta_mask)) {
1403                 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1404                          inta & ~priv->inta_mask);
1405         }
1406
1407         /* Re-enable all interrupts */
1408         /* only Re-enable if disabled by irq */
1409         if (test_bit(STATUS_INT_ENABLED, &priv->status))
1410                 iwl_enable_interrupts(priv);
1411         /* Re-enable RF_KILL if it occurred */
1412         else if (handled & CSR_INT_BIT_RF_KILL)
1413                 iwl_enable_rfkill_int(priv);
1414 }
1415
1416 /*****************************************************************************
1417  *
1418  * sysfs attributes
1419  *
1420  *****************************************************************************/
1421
1422 #ifdef CONFIG_IWLWIFI_DEBUG
1423
1424 /*
1425  * The following adds a new attribute to the sysfs representation
1426  * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1427  * used for controlling the debug level.
1428  *
1429  * See the level definitions in iwl for details.
1430  *
1431  * The debug_level being managed using sysfs below is a per device debug
1432  * level that is used instead of the global debug level if it (the per
1433  * device debug level) is set.
1434  */
1435 static ssize_t show_debug_level(struct device *d,
1436                                 struct device_attribute *attr, char *buf)
1437 {
1438         struct iwl_priv *priv = dev_get_drvdata(d);
1439         return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1440 }
1441 static ssize_t store_debug_level(struct device *d,
1442                                 struct device_attribute *attr,
1443                                  const char *buf, size_t count)
1444 {
1445         struct iwl_priv *priv = dev_get_drvdata(d);
1446         unsigned long val;
1447         int ret;
1448
1449         ret = strict_strtoul(buf, 0, &val);
1450         if (ret)
1451                 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1452         else {
1453                 priv->debug_level = val;
1454                 if (iwl_alloc_traffic_mem(priv))
1455                         IWL_ERR(priv,
1456                                 "Not enough memory to generate traffic log\n");
1457         }
1458         return strnlen(buf, count);
1459 }
1460
1461 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1462                         show_debug_level, store_debug_level);
1463
1464
1465 #endif /* CONFIG_IWLWIFI_DEBUG */
1466
1467
1468 static ssize_t show_temperature(struct device *d,
1469                                 struct device_attribute *attr, char *buf)
1470 {
1471         struct iwl_priv *priv = dev_get_drvdata(d);
1472
1473         if (!iwl_is_alive(priv))
1474                 return -EAGAIN;
1475
1476         return sprintf(buf, "%d\n", priv->temperature);
1477 }
1478
1479 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1480
1481 static ssize_t show_tx_power(struct device *d,
1482                              struct device_attribute *attr, char *buf)
1483 {
1484         struct iwl_priv *priv = dev_get_drvdata(d);
1485
1486         if (!iwl_is_ready_rf(priv))
1487                 return sprintf(buf, "off\n");
1488         else
1489                 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1490 }
1491
1492 static ssize_t store_tx_power(struct device *d,
1493                               struct device_attribute *attr,
1494                               const char *buf, size_t count)
1495 {
1496         struct iwl_priv *priv = dev_get_drvdata(d);
1497         unsigned long val;
1498         int ret;
1499
1500         ret = strict_strtoul(buf, 10, &val);
1501         if (ret)
1502                 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1503         else {
1504                 ret = iwl_set_tx_power(priv, val, false);
1505                 if (ret)
1506                         IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1507                                 ret);
1508                 else
1509                         ret = count;
1510         }
1511         return ret;
1512 }
1513
1514 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1515
1516 static struct attribute *iwl_sysfs_entries[] = {
1517         &dev_attr_temperature.attr,
1518         &dev_attr_tx_power.attr,
1519 #ifdef CONFIG_IWLWIFI_DEBUG
1520         &dev_attr_debug_level.attr,
1521 #endif
1522         NULL
1523 };
1524
1525 static struct attribute_group iwl_attribute_group = {
1526         .name = NULL,           /* put in device directory */
1527         .attrs = iwl_sysfs_entries,
1528 };
1529
1530 /******************************************************************************
1531  *
1532  * uCode download functions
1533  *
1534  ******************************************************************************/
1535
1536 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1537 {
1538         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1539         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1540         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1541         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1542         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1543         iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1544 }
1545
1546 static void iwl_nic_start(struct iwl_priv *priv)
1547 {
1548         /* Remove all resets to allow NIC to operate */
1549         iwl_write32(priv, CSR_RESET, 0);
1550 }
1551
1552 struct iwlagn_ucode_capabilities {
1553         u32 max_probe_length;
1554         u32 standard_phy_calibration_size;
1555         bool pan;
1556 };
1557
1558 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1559 static int iwl_mac_setup_register(struct iwl_priv *priv,
1560                                   struct iwlagn_ucode_capabilities *capa);
1561
1562 #define UCODE_EXPERIMENTAL_INDEX        100
1563 #define UCODE_EXPERIMENTAL_TAG          "exp"
1564
1565 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1566 {
1567         const char *name_pre = priv->cfg->fw_name_pre;
1568         char tag[8];
1569
1570         if (first) {
1571 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1572                 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1573                 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1574         } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1575 #endif
1576                 priv->fw_index = priv->cfg->ucode_api_max;
1577                 sprintf(tag, "%d", priv->fw_index);
1578         } else {
1579                 priv->fw_index--;
1580                 sprintf(tag, "%d", priv->fw_index);
1581         }
1582
1583         if (priv->fw_index < priv->cfg->ucode_api_min) {
1584                 IWL_ERR(priv, "no suitable firmware found!\n");
1585                 return -ENOENT;
1586         }
1587
1588         sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1589
1590         IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1591                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1592                                 ? "EXPERIMENTAL " : "",
1593                        priv->firmware_name);
1594
1595         return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1596                                        &priv->pci_dev->dev, GFP_KERNEL, priv,
1597                                        iwl_ucode_callback);
1598 }
1599
1600 struct iwlagn_firmware_pieces {
1601         const void *inst, *data, *init, *init_data, *boot;
1602         size_t inst_size, data_size, init_size, init_data_size, boot_size;
1603
1604         u32 build;
1605
1606         u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1607         u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1608 };
1609
1610 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1611                                        const struct firmware *ucode_raw,
1612                                        struct iwlagn_firmware_pieces *pieces)
1613 {
1614         struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1615         u32 api_ver, hdr_size;
1616         const u8 *src;
1617
1618         priv->ucode_ver = le32_to_cpu(ucode->ver);
1619         api_ver = IWL_UCODE_API(priv->ucode_ver);
1620
1621         switch (api_ver) {
1622         default:
1623                 /*
1624                  * 4965 doesn't revision the firmware file format
1625                  * along with the API version, it always uses v1
1626                  * file format.
1627                  */
1628                 if ((priv->hw_rev & CSR_HW_REV_TYPE_MSK) !=
1629                                 CSR_HW_REV_TYPE_4965) {
1630                         hdr_size = 28;
1631                         if (ucode_raw->size < hdr_size) {
1632                                 IWL_ERR(priv, "File size too small!\n");
1633                                 return -EINVAL;
1634                         }
1635                         pieces->build = le32_to_cpu(ucode->u.v2.build);
1636                         pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1637                         pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1638                         pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1639                         pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1640                         pieces->boot_size = le32_to_cpu(ucode->u.v2.boot_size);
1641                         src = ucode->u.v2.data;
1642                         break;
1643                 }
1644                 /* fall through for 4965 */
1645         case 0:
1646         case 1:
1647         case 2:
1648                 hdr_size = 24;
1649                 if (ucode_raw->size < hdr_size) {
1650                         IWL_ERR(priv, "File size too small!\n");
1651                         return -EINVAL;
1652                 }
1653                 pieces->build = 0;
1654                 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1655                 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1656                 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1657                 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1658                 pieces->boot_size = le32_to_cpu(ucode->u.v1.boot_size);
1659                 src = ucode->u.v1.data;
1660                 break;
1661         }
1662
1663         /* Verify size of file vs. image size info in file's header */
1664         if (ucode_raw->size != hdr_size + pieces->inst_size +
1665                                 pieces->data_size + pieces->init_size +
1666                                 pieces->init_data_size + pieces->boot_size) {
1667
1668                 IWL_ERR(priv,
1669                         "uCode file size %d does not match expected size\n",
1670                         (int)ucode_raw->size);
1671                 return -EINVAL;
1672         }
1673
1674         pieces->inst = src;
1675         src += pieces->inst_size;
1676         pieces->data = src;
1677         src += pieces->data_size;
1678         pieces->init = src;
1679         src += pieces->init_size;
1680         pieces->init_data = src;
1681         src += pieces->init_data_size;
1682         pieces->boot = src;
1683         src += pieces->boot_size;
1684
1685         return 0;
1686 }
1687
1688 static int iwlagn_wanted_ucode_alternative = 1;
1689
1690 static int iwlagn_load_firmware(struct iwl_priv *priv,
1691                                 const struct firmware *ucode_raw,
1692                                 struct iwlagn_firmware_pieces *pieces,
1693                                 struct iwlagn_ucode_capabilities *capa)
1694 {
1695         struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1696         struct iwl_ucode_tlv *tlv;
1697         size_t len = ucode_raw->size;
1698         const u8 *data;
1699         int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1700         u64 alternatives;
1701         u32 tlv_len;
1702         enum iwl_ucode_tlv_type tlv_type;
1703         const u8 *tlv_data;
1704
1705         if (len < sizeof(*ucode)) {
1706                 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1707                 return -EINVAL;
1708         }
1709
1710         if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1711                 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1712                         le32_to_cpu(ucode->magic));
1713                 return -EINVAL;
1714         }
1715
1716         /*
1717          * Check which alternatives are present, and "downgrade"
1718          * when the chosen alternative is not present, warning
1719          * the user when that happens. Some files may not have
1720          * any alternatives, so don't warn in that case.
1721          */
1722         alternatives = le64_to_cpu(ucode->alternatives);
1723         tmp = wanted_alternative;
1724         if (wanted_alternative > 63)
1725                 wanted_alternative = 63;
1726         while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1727                 wanted_alternative--;
1728         if (wanted_alternative && wanted_alternative != tmp)
1729                 IWL_WARN(priv,
1730                          "uCode alternative %d not available, choosing %d\n",
1731                          tmp, wanted_alternative);
1732
1733         priv->ucode_ver = le32_to_cpu(ucode->ver);
1734         pieces->build = le32_to_cpu(ucode->build);
1735         data = ucode->data;
1736
1737         len -= sizeof(*ucode);
1738
1739         while (len >= sizeof(*tlv)) {
1740                 u16 tlv_alt;
1741
1742                 len -= sizeof(*tlv);
1743                 tlv = (void *)data;
1744
1745                 tlv_len = le32_to_cpu(tlv->length);
1746                 tlv_type = le16_to_cpu(tlv->type);
1747                 tlv_alt = le16_to_cpu(tlv->alternative);
1748                 tlv_data = tlv->data;
1749
1750                 if (len < tlv_len) {
1751                         IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1752                                 len, tlv_len);
1753                         return -EINVAL;
1754                 }
1755                 len -= ALIGN(tlv_len, 4);
1756                 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1757
1758                 /*
1759                  * Alternative 0 is always valid.
1760                  *
1761                  * Skip alternative TLVs that are not selected.
1762                  */
1763                 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1764                         continue;
1765
1766                 switch (tlv_type) {
1767                 case IWL_UCODE_TLV_INST:
1768                         pieces->inst = tlv_data;
1769                         pieces->inst_size = tlv_len;
1770                         break;
1771                 case IWL_UCODE_TLV_DATA:
1772                         pieces->data = tlv_data;
1773                         pieces->data_size = tlv_len;
1774                         break;
1775                 case IWL_UCODE_TLV_INIT:
1776                         pieces->init = tlv_data;
1777                         pieces->init_size = tlv_len;
1778                         break;
1779                 case IWL_UCODE_TLV_INIT_DATA:
1780                         pieces->init_data = tlv_data;
1781                         pieces->init_data_size = tlv_len;
1782                         break;
1783                 case IWL_UCODE_TLV_BOOT:
1784                         pieces->boot = tlv_data;
1785                         pieces->boot_size = tlv_len;
1786                         break;
1787                 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1788                         if (tlv_len != sizeof(u32))
1789                                 goto invalid_tlv_len;
1790                         capa->max_probe_length =
1791                                         le32_to_cpup((__le32 *)tlv_data);
1792                         break;
1793                 case IWL_UCODE_TLV_PAN:
1794                         if (tlv_len)
1795                                 goto invalid_tlv_len;
1796                         capa->pan = true;
1797                         break;
1798                 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1799                         if (tlv_len != sizeof(u32))
1800                                 goto invalid_tlv_len;
1801                         pieces->init_evtlog_ptr =
1802                                         le32_to_cpup((__le32 *)tlv_data);
1803                         break;
1804                 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1805                         if (tlv_len != sizeof(u32))
1806                                 goto invalid_tlv_len;
1807                         pieces->init_evtlog_size =
1808                                         le32_to_cpup((__le32 *)tlv_data);
1809                         break;
1810                 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1811                         if (tlv_len != sizeof(u32))
1812                                 goto invalid_tlv_len;
1813                         pieces->init_errlog_ptr =
1814                                         le32_to_cpup((__le32 *)tlv_data);
1815                         break;
1816                 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1817                         if (tlv_len != sizeof(u32))
1818                                 goto invalid_tlv_len;
1819                         pieces->inst_evtlog_ptr =
1820                                         le32_to_cpup((__le32 *)tlv_data);
1821                         break;
1822                 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1823                         if (tlv_len != sizeof(u32))
1824                                 goto invalid_tlv_len;
1825                         pieces->inst_evtlog_size =
1826                                         le32_to_cpup((__le32 *)tlv_data);
1827                         break;
1828                 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1829                         if (tlv_len != sizeof(u32))
1830                                 goto invalid_tlv_len;
1831                         pieces->inst_errlog_ptr =
1832                                         le32_to_cpup((__le32 *)tlv_data);
1833                         break;
1834                 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1835                         if (tlv_len)
1836                                 goto invalid_tlv_len;
1837                         priv->enhance_sensitivity_table = true;
1838                         break;
1839                 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1840                         if (tlv_len != sizeof(u32))
1841                                 goto invalid_tlv_len;
1842                         capa->standard_phy_calibration_size =
1843                                         le32_to_cpup((__le32 *)tlv_data);
1844                         break;
1845                 default:
1846                         IWL_WARN(priv, "unknown TLV: %d\n", tlv_type);
1847                         break;
1848                 }
1849         }
1850
1851         if (len) {
1852                 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1853                 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1854                 return -EINVAL;
1855         }
1856
1857         return 0;
1858
1859  invalid_tlv_len:
1860         IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1861         iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1862
1863         return -EINVAL;
1864 }
1865
1866 /**
1867  * iwl_ucode_callback - callback when firmware was loaded
1868  *
1869  * If loaded successfully, copies the firmware into buffers
1870  * for the card to fetch (via DMA).
1871  */
1872 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1873 {
1874         struct iwl_priv *priv = context;
1875         struct iwl_ucode_header *ucode;
1876         int err;
1877         struct iwlagn_firmware_pieces pieces;
1878         const unsigned int api_max = priv->cfg->ucode_api_max;
1879         const unsigned int api_min = priv->cfg->ucode_api_min;
1880         u32 api_ver;
1881         char buildstr[25];
1882         u32 build;
1883         struct iwlagn_ucode_capabilities ucode_capa = {
1884                 .max_probe_length = 200,
1885                 .standard_phy_calibration_size =
1886                         IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1887         };
1888
1889         memset(&pieces, 0, sizeof(pieces));
1890
1891         if (!ucode_raw) {
1892                 if (priv->fw_index <= priv->cfg->ucode_api_max)
1893                         IWL_ERR(priv,
1894                                 "request for firmware file '%s' failed.\n",
1895                                 priv->firmware_name);
1896                 goto try_again;
1897         }
1898
1899         IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1900                        priv->firmware_name, ucode_raw->size);
1901
1902         /* Make sure that we got at least the API version number */
1903         if (ucode_raw->size < 4) {
1904                 IWL_ERR(priv, "File size way too small!\n");
1905                 goto try_again;
1906         }
1907
1908         /* Data from ucode file:  header followed by uCode images */
1909         ucode = (struct iwl_ucode_header *)ucode_raw->data;
1910
1911         if (ucode->ver)
1912                 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1913         else
1914                 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1915                                            &ucode_capa);
1916
1917         if (err)
1918                 goto try_again;
1919
1920         api_ver = IWL_UCODE_API(priv->ucode_ver);
1921         build = pieces.build;
1922
1923         /*
1924          * api_ver should match the api version forming part of the
1925          * firmware filename ... but we don't check for that and only rely
1926          * on the API version read from firmware header from here on forward
1927          */
1928         /* no api version check required for experimental uCode */
1929         if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1930                 if (api_ver < api_min || api_ver > api_max) {
1931                         IWL_ERR(priv,
1932                                 "Driver unable to support your firmware API. "
1933                                 "Driver supports v%u, firmware is v%u.\n",
1934                                 api_max, api_ver);
1935                         goto try_again;
1936                 }
1937
1938                 if (api_ver != api_max)
1939                         IWL_ERR(priv,
1940                                 "Firmware has old API version. Expected v%u, "
1941                                 "got v%u. New firmware can be obtained "
1942                                 "from http://www.intellinuxwireless.org.\n",
1943                                 api_max, api_ver);
1944         }
1945
1946         if (build)
1947                 sprintf(buildstr, " build %u%s", build,
1948                        (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1949                                 ? " (EXP)" : "");
1950         else
1951                 buildstr[0] = '\0';
1952
1953         IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1954                  IWL_UCODE_MAJOR(priv->ucode_ver),
1955                  IWL_UCODE_MINOR(priv->ucode_ver),
1956                  IWL_UCODE_API(priv->ucode_ver),
1957                  IWL_UCODE_SERIAL(priv->ucode_ver),
1958                  buildstr);
1959
1960         snprintf(priv->hw->wiphy->fw_version,
1961                  sizeof(priv->hw->wiphy->fw_version),
1962                  "%u.%u.%u.%u%s",
1963                  IWL_UCODE_MAJOR(priv->ucode_ver),
1964                  IWL_UCODE_MINOR(priv->ucode_ver),
1965                  IWL_UCODE_API(priv->ucode_ver),
1966                  IWL_UCODE_SERIAL(priv->ucode_ver),
1967                  buildstr);
1968
1969         /*
1970          * For any of the failures below (before allocating pci memory)
1971          * we will try to load a version with a smaller API -- maybe the
1972          * user just got a corrupted version of the latest API.
1973          */
1974
1975         IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1976                        priv->ucode_ver);
1977         IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1978                        pieces.inst_size);
1979         IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1980                        pieces.data_size);
1981         IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1982                        pieces.init_size);
1983         IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1984                        pieces.init_data_size);
1985         IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %Zd\n",
1986                        pieces.boot_size);
1987
1988         /* Verify that uCode images will fit in card's SRAM */
1989         if (pieces.inst_size > priv->hw_params.max_inst_size) {
1990                 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1991                         pieces.inst_size);
1992                 goto try_again;
1993         }
1994
1995         if (pieces.data_size > priv->hw_params.max_data_size) {
1996                 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1997                         pieces.data_size);
1998                 goto try_again;
1999         }
2000
2001         if (pieces.init_size > priv->hw_params.max_inst_size) {
2002                 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
2003                         pieces.init_size);
2004                 goto try_again;
2005         }
2006
2007         if (pieces.init_data_size > priv->hw_params.max_data_size) {
2008                 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
2009                         pieces.init_data_size);
2010                 goto try_again;
2011         }
2012
2013         if (pieces.boot_size > priv->hw_params.max_bsm_size) {
2014                 IWL_ERR(priv, "uCode boot instr len %Zd too large to fit in\n",
2015                         pieces.boot_size);
2016                 goto try_again;
2017         }
2018
2019         /* Allocate ucode buffers for card's bus-master loading ... */
2020
2021         /* Runtime instructions and 2 copies of data:
2022          * 1) unmodified from disk
2023          * 2) backup cache for save/restore during power-downs */
2024         priv->ucode_code.len = pieces.inst_size;
2025         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
2026
2027         priv->ucode_data.len = pieces.data_size;
2028         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
2029
2030         priv->ucode_data_backup.len = pieces.data_size;
2031         iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
2032
2033         if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
2034             !priv->ucode_data_backup.v_addr)
2035                 goto err_pci_alloc;
2036
2037         /* Initialization instructions and data */
2038         if (pieces.init_size && pieces.init_data_size) {
2039                 priv->ucode_init.len = pieces.init_size;
2040                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
2041
2042                 priv->ucode_init_data.len = pieces.init_data_size;
2043                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
2044
2045                 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
2046                         goto err_pci_alloc;
2047         }
2048
2049         /* Bootstrap (instructions only, no data) */
2050         if (pieces.boot_size) {
2051                 priv->ucode_boot.len = pieces.boot_size;
2052                 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
2053
2054                 if (!priv->ucode_boot.v_addr)
2055                         goto err_pci_alloc;
2056         }
2057
2058         /* Now that we can no longer fail, copy information */
2059
2060         /*
2061          * The (size - 16) / 12 formula is based on the information recorded
2062          * for each event, which is of mode 1 (including timestamp) for all
2063          * new microcodes that include this information.
2064          */
2065         priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
2066         if (pieces.init_evtlog_size)
2067                 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
2068         else
2069                 priv->_agn.init_evtlog_size =
2070                         priv->cfg->base_params->max_event_log_size;
2071         priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
2072         priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
2073         if (pieces.inst_evtlog_size)
2074                 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
2075         else
2076                 priv->_agn.inst_evtlog_size =
2077                         priv->cfg->base_params->max_event_log_size;
2078         priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
2079
2080         if (ucode_capa.pan) {
2081                 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
2082                 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
2083         } else
2084                 priv->sta_key_max_num = STA_KEY_MAX_NUM;
2085
2086         /* Copy images into buffers for card's bus-master reads ... */
2087
2088         /* Runtime instructions (first block of data in file) */
2089         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n",
2090                         pieces.inst_size);
2091         memcpy(priv->ucode_code.v_addr, pieces.inst, pieces.inst_size);
2092
2093         IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
2094                 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
2095
2096         /*
2097          * Runtime data
2098          * NOTE:  Copy into backup buffer will be done in iwl_up()
2099          */
2100         IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n",
2101                         pieces.data_size);
2102         memcpy(priv->ucode_data.v_addr, pieces.data, pieces.data_size);
2103         memcpy(priv->ucode_data_backup.v_addr, pieces.data, pieces.data_size);
2104
2105         /* Initialization instructions */
2106         if (pieces.init_size) {
2107                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
2108                                 pieces.init_size);
2109                 memcpy(priv->ucode_init.v_addr, pieces.init, pieces.init_size);
2110         }
2111
2112         /* Initialization data */
2113         if (pieces.init_data_size) {
2114                 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
2115                                pieces.init_data_size);
2116                 memcpy(priv->ucode_init_data.v_addr, pieces.init_data,
2117                        pieces.init_data_size);
2118         }
2119
2120         /* Bootstrap instructions */
2121         IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n",
2122                         pieces.boot_size);
2123         memcpy(priv->ucode_boot.v_addr, pieces.boot, pieces.boot_size);
2124
2125         /*
2126          * figure out the offset of chain noise reset and gain commands
2127          * base on the size of standard phy calibration commands table size
2128          */
2129         if (ucode_capa.standard_phy_calibration_size >
2130             IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
2131                 ucode_capa.standard_phy_calibration_size =
2132                         IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
2133
2134         priv->_agn.phy_calib_chain_noise_reset_cmd =
2135                 ucode_capa.standard_phy_calibration_size;
2136         priv->_agn.phy_calib_chain_noise_gain_cmd =
2137                 ucode_capa.standard_phy_calibration_size + 1;
2138
2139         /**************************************************
2140          * This is still part of probe() in a sense...
2141          *
2142          * 9. Setup and register with mac80211 and debugfs
2143          **************************************************/
2144         err = iwl_mac_setup_register(priv, &ucode_capa);
2145         if (err)
2146                 goto out_unbind;
2147
2148         err = iwl_dbgfs_register(priv, DRV_NAME);
2149         if (err)
2150                 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
2151
2152         err = sysfs_create_group(&priv->pci_dev->dev.kobj,
2153                                         &iwl_attribute_group);
2154         if (err) {
2155                 IWL_ERR(priv, "failed to create sysfs device attributes\n");
2156                 goto out_unbind;
2157         }
2158
2159         /* We have our copies now, allow OS release its copies */
2160         release_firmware(ucode_raw);
2161         complete(&priv->_agn.firmware_loading_complete);
2162         return;
2163
2164  try_again:
2165         /* try next, if any */
2166         if (iwl_request_firmware(priv, false))
2167                 goto out_unbind;
2168         release_firmware(ucode_raw);
2169         return;
2170
2171  err_pci_alloc:
2172         IWL_ERR(priv, "failed to allocate pci memory\n");
2173         iwl_dealloc_ucode_pci(priv);
2174  out_unbind:
2175         complete(&priv->_agn.firmware_loading_complete);
2176         device_release_driver(&priv->pci_dev->dev);
2177         release_firmware(ucode_raw);
2178 }
2179
2180 static const char *desc_lookup_text[] = {
2181         "OK",
2182         "FAIL",
2183         "BAD_PARAM",
2184         "BAD_CHECKSUM",
2185         "NMI_INTERRUPT_WDG",
2186         "SYSASSERT",
2187         "FATAL_ERROR",
2188         "BAD_COMMAND",
2189         "HW_ERROR_TUNE_LOCK",
2190         "HW_ERROR_TEMPERATURE",
2191         "ILLEGAL_CHAN_FREQ",
2192         "VCC_NOT_STABLE",
2193         "FH_ERROR",
2194         "NMI_INTERRUPT_HOST",
2195         "NMI_INTERRUPT_ACTION_PT",
2196         "NMI_INTERRUPT_UNKNOWN",
2197         "UCODE_VERSION_MISMATCH",
2198         "HW_ERROR_ABS_LOCK",
2199         "HW_ERROR_CAL_LOCK_FAIL",
2200         "NMI_INTERRUPT_INST_ACTION_PT",
2201         "NMI_INTERRUPT_DATA_ACTION_PT",
2202         "NMI_TRM_HW_ER",
2203         "NMI_INTERRUPT_TRM",
2204         "NMI_INTERRUPT_BREAK_POINT"
2205         "DEBUG_0",
2206         "DEBUG_1",
2207         "DEBUG_2",
2208         "DEBUG_3",
2209 };
2210
2211 static struct { char *name; u8 num; } advanced_lookup[] = {
2212         { "NMI_INTERRUPT_WDG", 0x34 },
2213         { "SYSASSERT", 0x35 },
2214         { "UCODE_VERSION_MISMATCH", 0x37 },
2215         { "BAD_COMMAND", 0x38 },
2216         { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
2217         { "FATAL_ERROR", 0x3D },
2218         { "NMI_TRM_HW_ERR", 0x46 },
2219         { "NMI_INTERRUPT_TRM", 0x4C },
2220         { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
2221         { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
2222         { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
2223         { "NMI_INTERRUPT_HOST", 0x66 },
2224         { "NMI_INTERRUPT_ACTION_PT", 0x7C },
2225         { "NMI_INTERRUPT_UNKNOWN", 0x84 },
2226         { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
2227         { "ADVANCED_SYSASSERT", 0 },
2228 };
2229
2230 static const char *desc_lookup(u32 num)
2231 {
2232         int i;
2233         int max = ARRAY_SIZE(desc_lookup_text);
2234
2235         if (num < max)
2236                 return desc_lookup_text[num];
2237
2238         max = ARRAY_SIZE(advanced_lookup) - 1;
2239         for (i = 0; i < max; i++) {
2240                 if (advanced_lookup[i].num == num)
2241                         break;;
2242         }
2243         return advanced_lookup[i].name;
2244 }
2245
2246 #define ERROR_START_OFFSET  (1 * sizeof(u32))
2247 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
2248
2249 void iwl_dump_nic_error_log(struct iwl_priv *priv)
2250 {
2251         u32 data2, line;
2252         u32 desc, time, count, base, data1;
2253         u32 blink1, blink2, ilink1, ilink2;
2254         u32 pc, hcmd;
2255
2256         if (priv->ucode_type == UCODE_INIT) {
2257                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
2258                 if (!base)
2259                         base = priv->_agn.init_errlog_ptr;
2260         } else {
2261                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
2262                 if (!base)
2263                         base = priv->_agn.inst_errlog_ptr;
2264         }
2265
2266         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2267                 IWL_ERR(priv,
2268                         "Not valid error log pointer 0x%08X for %s uCode\n",
2269                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2270                 return;
2271         }
2272
2273         count = iwl_read_targ_mem(priv, base);
2274
2275         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
2276                 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
2277                 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
2278                         priv->status, count);
2279         }
2280
2281         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
2282         priv->isr_stats.err_code = desc;
2283         pc = iwl_read_targ_mem(priv, base + 2 * sizeof(u32));
2284         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
2285         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
2286         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
2287         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
2288         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
2289         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
2290         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
2291         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
2292         hcmd = iwl_read_targ_mem(priv, base + 22 * sizeof(u32));
2293
2294         trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
2295                                       blink1, blink2, ilink1, ilink2);
2296
2297         IWL_ERR(priv, "Desc                                  Time       "
2298                 "data1      data2      line\n");
2299         IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
2300                 desc_lookup(desc), desc, time, data1, data2, line);
2301         IWL_ERR(priv, "pc      blink1  blink2  ilink1  ilink2  hcmd\n");
2302         IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
2303                 pc, blink1, blink2, ilink1, ilink2, hcmd);
2304 }
2305
2306 #define EVENT_START_OFFSET  (4 * sizeof(u32))
2307
2308 /**
2309  * iwl_print_event_log - Dump error event log to syslog
2310  *
2311  */
2312 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
2313                                u32 num_events, u32 mode,
2314                                int pos, char **buf, size_t bufsz)
2315 {
2316         u32 i;
2317         u32 base;       /* SRAM byte address of event log header */
2318         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
2319         u32 ptr;        /* SRAM byte address of log data */
2320         u32 ev, time, data; /* event log data */
2321         unsigned long reg_flags;
2322
2323         if (num_events == 0)
2324                 return pos;
2325
2326         if (priv->ucode_type == UCODE_INIT) {
2327                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2328                 if (!base)
2329                         base = priv->_agn.init_evtlog_ptr;
2330         } else {
2331                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2332                 if (!base)
2333                         base = priv->_agn.inst_evtlog_ptr;
2334         }
2335
2336         if (mode == 0)
2337                 event_size = 2 * sizeof(u32);
2338         else
2339                 event_size = 3 * sizeof(u32);
2340
2341         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
2342
2343         /* Make sure device is powered up for SRAM reads */
2344         spin_lock_irqsave(&priv->reg_lock, reg_flags);
2345         iwl_grab_nic_access(priv);
2346
2347         /* Set starting address; reads will auto-increment */
2348         _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
2349         rmb();
2350
2351         /* "time" is actually "data" for mode 0 (no timestamp).
2352         * place event id # at far right for easier visual parsing. */
2353         for (i = 0; i < num_events; i++) {
2354                 ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2355                 time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2356                 if (mode == 0) {
2357                         /* data, ev */
2358                         if (bufsz) {
2359                                 pos += scnprintf(*buf + pos, bufsz - pos,
2360                                                 "EVT_LOG:0x%08x:%04u\n",
2361                                                 time, ev);
2362                         } else {
2363                                 trace_iwlwifi_dev_ucode_event(priv, 0,
2364                                         time, ev);
2365                                 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
2366                                         time, ev);
2367                         }
2368                 } else {
2369                         data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
2370                         if (bufsz) {
2371                                 pos += scnprintf(*buf + pos, bufsz - pos,
2372                                                 "EVT_LOGT:%010u:0x%08x:%04u\n",
2373                                                  time, data, ev);
2374                         } else {
2375                                 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
2376                                         time, data, ev);
2377                                 trace_iwlwifi_dev_ucode_event(priv, time,
2378                                         data, ev);
2379                         }
2380                 }
2381         }
2382
2383         /* Allow device to power down */
2384         iwl_release_nic_access(priv);
2385         spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
2386         return pos;
2387 }
2388
2389 /**
2390  * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2391  */
2392 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2393                                     u32 num_wraps, u32 next_entry,
2394                                     u32 size, u32 mode,
2395                                     int pos, char **buf, size_t bufsz)
2396 {
2397         /*
2398          * display the newest DEFAULT_LOG_ENTRIES entries
2399          * i.e the entries just before the next ont that uCode would fill.
2400          */
2401         if (num_wraps) {
2402                 if (next_entry < size) {
2403                         pos = iwl_print_event_log(priv,
2404                                                 capacity - (size - next_entry),
2405                                                 size - next_entry, mode,
2406                                                 pos, buf, bufsz);
2407                         pos = iwl_print_event_log(priv, 0,
2408                                                   next_entry, mode,
2409                                                   pos, buf, bufsz);
2410                 } else
2411                         pos = iwl_print_event_log(priv, next_entry - size,
2412                                                   size, mode, pos, buf, bufsz);
2413         } else {
2414                 if (next_entry < size) {
2415                         pos = iwl_print_event_log(priv, 0, next_entry,
2416                                                   mode, pos, buf, bufsz);
2417                 } else {
2418                         pos = iwl_print_event_log(priv, next_entry - size,
2419                                                   size, mode, pos, buf, bufsz);
2420                 }
2421         }
2422         return pos;
2423 }
2424
2425 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2426
2427 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2428                             char **buf, bool display)
2429 {
2430         u32 base;       /* SRAM byte address of event log header */
2431         u32 capacity;   /* event log capacity in # entries */
2432         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
2433         u32 num_wraps;  /* # times uCode wrapped to top of log */
2434         u32 next_entry; /* index of next entry to be written by uCode */
2435         u32 size;       /* # entries that we'll print */
2436         u32 logsize;
2437         int pos = 0;
2438         size_t bufsz = 0;
2439
2440         if (priv->ucode_type == UCODE_INIT) {
2441                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
2442                 logsize = priv->_agn.init_evtlog_size;
2443                 if (!base)
2444                         base = priv->_agn.init_evtlog_ptr;
2445         } else {
2446                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
2447                 logsize = priv->_agn.inst_evtlog_size;
2448                 if (!base)
2449                         base = priv->_agn.inst_evtlog_ptr;
2450         }
2451
2452         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2453                 IWL_ERR(priv,
2454                         "Invalid event log pointer 0x%08X for %s uCode\n",
2455                         base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
2456                 return -EINVAL;
2457         }
2458
2459         /* event log header */
2460         capacity = iwl_read_targ_mem(priv, base);
2461         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2462         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2463         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2464
2465         if (capacity > logsize) {
2466                 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2467                         capacity, logsize);
2468                 capacity = logsize;
2469         }
2470
2471         if (next_entry > logsize) {
2472                 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2473                         next_entry, logsize);
2474                 next_entry = logsize;
2475         }
2476
2477         size = num_wraps ? capacity : next_entry;
2478
2479         /* bail out if nothing in log */
2480         if (size == 0) {
2481                 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2482                 return pos;
2483         }
2484
2485         /* enable/disable bt channel inhibition */
2486         priv->bt_ch_announce = iwlagn_bt_ch_announce;
2487
2488 #ifdef CONFIG_IWLWIFI_DEBUG
2489         if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2490                 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2491                         ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2492 #else
2493         size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2494                 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2495 #endif
2496         IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2497                 size);
2498
2499 #ifdef CONFIG_IWLWIFI_DEBUG
2500         if (display) {
2501                 if (full_log)
2502                         bufsz = capacity * 48;
2503                 else
2504                         bufsz = size * 48;
2505                 *buf = kmalloc(bufsz, GFP_KERNEL);
2506                 if (!*buf)
2507                         return -ENOMEM;
2508         }
2509         if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2510                 /*
2511                  * if uCode has wrapped back to top of log,
2512                  * start at the oldest entry,
2513                  * i.e the next one that uCode would fill.
2514                  */
2515                 if (num_wraps)
2516                         pos = iwl_print_event_log(priv, next_entry,
2517                                                 capacity - next_entry, mode,
2518                                                 pos, buf, bufsz);
2519                 /* (then/else) start at top of log */
2520                 pos = iwl_print_event_log(priv, 0,
2521                                           next_entry, mode, pos, buf, bufsz);
2522         } else
2523                 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2524                                                 next_entry, size, mode,
2525                                                 pos, buf, bufsz);
2526 #else
2527         pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2528                                         next_entry, size, mode,
2529                                         pos, buf, bufsz);
2530 #endif
2531         return pos;
2532 }
2533
2534 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2535 {
2536         struct iwl_ct_kill_config cmd;
2537         struct iwl_ct_kill_throttling_config adv_cmd;
2538         unsigned long flags;
2539         int ret = 0;
2540
2541         spin_lock_irqsave(&priv->lock, flags);
2542         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2543                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2544         spin_unlock_irqrestore(&priv->lock, flags);
2545         priv->thermal_throttle.ct_kill_toggle = false;
2546
2547         if (priv->cfg->base_params->support_ct_kill_exit) {
2548                 adv_cmd.critical_temperature_enter =
2549                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2550                 adv_cmd.critical_temperature_exit =
2551                         cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2552
2553                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2554                                        sizeof(adv_cmd), &adv_cmd);
2555                 if (ret)
2556                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2557                 else
2558                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2559                                         "succeeded, "
2560                                         "critical temperature enter is %d,"
2561                                         "exit is %d\n",
2562                                        priv->hw_params.ct_kill_threshold,
2563                                        priv->hw_params.ct_kill_exit_threshold);
2564         } else {
2565                 cmd.critical_temperature_R =
2566                         cpu_to_le32(priv->hw_params.ct_kill_threshold);
2567
2568                 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2569                                        sizeof(cmd), &cmd);
2570                 if (ret)
2571                         IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2572                 else
2573                         IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2574                                         "succeeded, "
2575                                         "critical temperature is %d\n",
2576                                         priv->hw_params.ct_kill_threshold);
2577         }
2578 }
2579
2580 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2581 {
2582         struct iwl_calib_cfg_cmd calib_cfg_cmd;
2583         struct iwl_host_cmd cmd = {
2584                 .id = CALIBRATION_CFG_CMD,
2585                 .len = sizeof(struct iwl_calib_cfg_cmd),
2586                 .data = &calib_cfg_cmd,
2587         };
2588
2589         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2590         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2591         calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2592
2593         return iwl_send_cmd(priv, &cmd);
2594 }
2595
2596
2597 /**
2598  * iwl_alive_start - called after REPLY_ALIVE notification received
2599  *                   from protocol/runtime uCode (initialization uCode's
2600  *                   Alive gets handled by iwl_init_alive_start()).
2601  */
2602 static void iwl_alive_start(struct iwl_priv *priv)
2603 {
2604         int ret = 0;
2605         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2606
2607         IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2608
2609         /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2610          * This is a paranoid check, because we would not have gotten the
2611          * "runtime" alive if code weren't properly loaded.  */
2612         if (iwl_verify_ucode(priv)) {
2613                 /* Runtime instruction load was bad;
2614                  * take it all the way back down so we can try again */
2615                 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
2616                 goto restart;
2617         }
2618
2619         ret = priv->cfg->ops->lib->alive_notify(priv);
2620         if (ret) {
2621                 IWL_WARN(priv,
2622                         "Could not complete ALIVE transition [ntf]: %d\n", ret);
2623                 goto restart;
2624         }
2625
2626
2627         /* After the ALIVE response, we can send host commands to the uCode */
2628         set_bit(STATUS_ALIVE, &priv->status);
2629
2630         /* Enable watchdog to monitor the driver tx queues */
2631         iwl_setup_watchdog(priv);
2632
2633         if (iwl_is_rfkill(priv))
2634                 return;
2635
2636         /* download priority table before any calibration request */
2637         if (priv->cfg->bt_params &&
2638             priv->cfg->bt_params->advanced_bt_coexist) {
2639                 /* Configure Bluetooth device coexistence support */
2640                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2641                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2642                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2643                 priv->cfg->ops->hcmd->send_bt_config(priv);
2644                 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2645                 iwlagn_send_prio_tbl(priv);
2646
2647                 /* FIXME: w/a to force change uCode BT state machine */
2648                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2649                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2650                 iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2651                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2652         }
2653         if (priv->hw_params.calib_rt_cfg)
2654                 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2655
2656         ieee80211_wake_queues(priv->hw);
2657
2658         priv->active_rate = IWL_RATES_MASK;
2659
2660         /* Configure Tx antenna selection based on H/W config */
2661         if (priv->cfg->ops->hcmd->set_tx_ant)
2662                 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2663
2664         if (iwl_is_associated_ctx(ctx)) {
2665                 struct iwl_rxon_cmd *active_rxon =
2666                                 (struct iwl_rxon_cmd *)&ctx->active;
2667                 /* apply any changes in staging */
2668                 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2669                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2670         } else {
2671                 struct iwl_rxon_context *tmp;
2672                 /* Initialize our rx_config data */
2673                 for_each_context(priv, tmp)
2674                         iwl_connection_init_rx_config(priv, tmp);
2675
2676                 if (priv->cfg->ops->hcmd->set_rxon_chain)
2677                         priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2678         }
2679
2680         if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2681             !priv->cfg->bt_params->advanced_bt_coexist)) {
2682                 /*
2683                  * default is 2-wire BT coexexistence support
2684                  */
2685                 priv->cfg->ops->hcmd->send_bt_config(priv);
2686         }
2687
2688         iwl_reset_run_time_calib(priv);
2689
2690         set_bit(STATUS_READY, &priv->status);
2691
2692         /* Configure the adapter for unassociated operation */
2693         iwlcore_commit_rxon(priv, ctx);
2694
2695         /* At this point, the NIC is initialized and operational */
2696         iwl_rf_kill_ct_config(priv);
2697
2698         IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2699         wake_up_interruptible(&priv->wait_command_queue);
2700
2701         iwl_power_update_mode(priv, true);
2702         IWL_DEBUG_INFO(priv, "Updated power mode\n");
2703
2704
2705         return;
2706
2707  restart:
2708         queue_work(priv->workqueue, &priv->restart);
2709 }
2710
2711 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2712
2713 static void __iwl_down(struct iwl_priv *priv)
2714 {
2715         unsigned long flags;
2716         int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
2717
2718         IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2719
2720         iwl_scan_cancel_timeout(priv, 200);
2721
2722         exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2723
2724         /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2725          * to prevent rearm timer */
2726         del_timer_sync(&priv->watchdog);
2727
2728         iwl_clear_ucode_stations(priv, NULL);
2729         iwl_dealloc_bcast_stations(priv);
2730         iwl_clear_driver_stations(priv);
2731
2732         /* reset BT coex data */
2733         priv->bt_status = 0;
2734         if (priv->cfg->bt_params)
2735                 priv->bt_traffic_load =
2736                          priv->cfg->bt_params->bt_init_traffic_load;
2737         else
2738                 priv->bt_traffic_load = 0;
2739         priv->bt_full_concurrent = false;
2740         priv->bt_ci_compliance = 0;
2741
2742         /* Unblock any waiting calls */
2743         wake_up_interruptible_all(&priv->wait_command_queue);
2744
2745         /* Wipe out the EXIT_PENDING status bit if we are not actually
2746          * exiting the module */
2747         if (!exit_pending)
2748                 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2749
2750         /* stop and reset the on-board processor */
2751         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
2752
2753         /* tell the device to stop sending interrupts */
2754         spin_lock_irqsave(&priv->lock, flags);
2755         iwl_disable_interrupts(priv);
2756         spin_unlock_irqrestore(&priv->lock, flags);
2757         iwl_synchronize_irq(priv);
2758
2759         if (priv->mac80211_registered)
2760                 ieee80211_stop_queues(priv->hw);
2761
2762         /* If we have not previously called iwl_init() then
2763          * clear all bits but the RF Kill bit and return */
2764         if (!iwl_is_init(priv)) {
2765                 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2766                                         STATUS_RF_KILL_HW |
2767                                test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2768                                         STATUS_GEO_CONFIGURED |
2769                                test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2770                                         STATUS_EXIT_PENDING;
2771                 goto exit;
2772         }
2773
2774         /* ...otherwise clear out all the status bits but the RF Kill
2775          * bit and continue taking the NIC down. */
2776         priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2777                                 STATUS_RF_KILL_HW |
2778                         test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2779                                 STATUS_GEO_CONFIGURED |
2780                         test_bit(STATUS_FW_ERROR, &priv->status) <<
2781                                 STATUS_FW_ERROR |
2782                        test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2783                                 STATUS_EXIT_PENDING;
2784
2785         /* device going down, Stop using ICT table */
2786         if (priv->cfg->ops->lib->isr_ops.disable)
2787                 priv->cfg->ops->lib->isr_ops.disable(priv);
2788
2789         iwlagn_txq_ctx_stop(priv);
2790         iwlagn_rxq_stop(priv);
2791
2792         /* Power-down device's busmaster DMA clocks */
2793         iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
2794         udelay(5);
2795
2796         /* Make sure (redundant) we've released our request to stay awake */
2797         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2798
2799         /* Stop the device, and put it in low power state */
2800         iwl_apm_stop(priv);
2801
2802  exit:
2803         memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
2804
2805         dev_kfree_skb(priv->beacon_skb);
2806         priv->beacon_skb = NULL;
2807
2808         /* clear out any free frames */
2809         iwl_clear_free_frames(priv);
2810 }
2811
2812 static void iwl_down(struct iwl_priv *priv)
2813 {
2814         mutex_lock(&priv->mutex);
2815         __iwl_down(priv);
2816         mutex_unlock(&priv->mutex);
2817
2818         iwl_cancel_deferred_work(priv);
2819 }
2820
2821 #define HW_READY_TIMEOUT (50)
2822
2823 static int iwl_set_hw_ready(struct iwl_priv *priv)
2824 {
2825         int ret = 0;
2826
2827         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2828                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2829
2830         /* See if we got it */
2831         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2832                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2833                                 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2834                                 HW_READY_TIMEOUT);
2835         if (ret != -ETIMEDOUT)
2836                 priv->hw_ready = true;
2837         else
2838                 priv->hw_ready = false;
2839
2840         IWL_DEBUG_INFO(priv, "hardware %s\n",
2841                       (priv->hw_ready == 1) ? "ready" : "not ready");
2842         return ret;
2843 }
2844
2845 static int iwl_prepare_card_hw(struct iwl_priv *priv)
2846 {
2847         int ret = 0;
2848
2849         IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2850
2851         ret = iwl_set_hw_ready(priv);
2852         if (priv->hw_ready)
2853                 return ret;
2854
2855         /* If HW is not ready, prepare the conditions to check again */
2856         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2857                         CSR_HW_IF_CONFIG_REG_PREPARE);
2858
2859         ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2860                         ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2861                         CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2862
2863         /* HW should be ready by now, check again. */
2864         if (ret != -ETIMEDOUT)
2865                 iwl_set_hw_ready(priv);
2866
2867         return ret;
2868 }
2869
2870 #define MAX_HW_RESTARTS 5
2871
2872 static int __iwl_up(struct iwl_priv *priv)
2873 {
2874         struct iwl_rxon_context *ctx;
2875         int i;
2876         int ret;
2877
2878         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2879                 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2880                 return -EIO;
2881         }
2882
2883         if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2884                 IWL_ERR(priv, "ucode not available for device bringup\n");
2885                 return -EIO;
2886         }
2887
2888         for_each_context(priv, ctx) {
2889                 ret = iwlagn_alloc_bcast_station(priv, ctx);
2890                 if (ret) {
2891                         iwl_dealloc_bcast_stations(priv);
2892                         return ret;
2893                 }
2894         }
2895
2896         iwl_prepare_card_hw(priv);
2897
2898         if (!priv->hw_ready) {
2899                 IWL_WARN(priv, "Exit HW not ready\n");
2900                 return -EIO;
2901         }
2902
2903         /* If platform's RF_KILL switch is NOT set to KILL */
2904         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2905                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2906         else
2907                 set_bit(STATUS_RF_KILL_HW, &priv->status);
2908
2909         if (iwl_is_rfkill(priv)) {
2910                 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2911
2912                 iwl_enable_interrupts(priv);
2913                 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2914                 return 0;
2915         }
2916
2917         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2918
2919         /* must be initialised before iwl_hw_nic_init */
2920         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
2921                 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
2922         else
2923                 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
2924
2925         ret = iwlagn_hw_nic_init(priv);
2926         if (ret) {
2927                 IWL_ERR(priv, "Unable to init nic\n");
2928                 return ret;
2929         }
2930
2931         /* make sure rfkill handshake bits are cleared */
2932         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2933         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2934                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2935
2936         /* clear (again), then enable host interrupts */
2937         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2938         iwl_enable_interrupts(priv);
2939
2940         /* really make sure rfkill handshake bits are cleared */
2941         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2942         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2943
2944         /* Copy original ucode data image from disk into backup cache.
2945          * This will be used to initialize the on-board processor's
2946          * data SRAM for a clean start when the runtime program first loads. */
2947         memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2948                priv->ucode_data.len);
2949
2950         for (i = 0; i < MAX_HW_RESTARTS; i++) {
2951
2952                 /* load bootstrap state machine,
2953                  * load bootstrap program into processor's memory,
2954                  * prepare to load the "initialize" uCode */
2955                 ret = priv->cfg->ops->lib->load_ucode(priv);
2956
2957                 if (ret) {
2958                         IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2959                                 ret);
2960                         continue;
2961                 }
2962
2963                 /* start card; "initialize" will load runtime ucode */
2964                 iwl_nic_start(priv);
2965
2966                 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2967
2968                 return 0;
2969         }
2970
2971         set_bit(STATUS_EXIT_PENDING, &priv->status);
2972         __iwl_down(priv);
2973         clear_bit(STATUS_EXIT_PENDING, &priv->status);
2974
2975         /* tried to restart and config the device for as long as our
2976          * patience could withstand */
2977         IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2978         return -EIO;
2979 }
2980
2981
2982 /*****************************************************************************
2983  *
2984  * Workqueue callbacks
2985  *
2986  *****************************************************************************/
2987
2988 static void iwl_bg_init_alive_start(struct work_struct *data)
2989 {
2990         struct iwl_priv *priv =
2991             container_of(data, struct iwl_priv, init_alive_start.work);
2992
2993         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2994                 return;
2995
2996         mutex_lock(&priv->mutex);
2997         priv->cfg->ops->lib->init_alive_start(priv);
2998         mutex_unlock(&priv->mutex);
2999 }
3000
3001 static void iwl_bg_alive_start(struct work_struct *data)
3002 {
3003         struct iwl_priv *priv =
3004             container_of(data, struct iwl_priv, alive_start.work);
3005
3006         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3007                 return;
3008
3009         /* enable dram interrupt */
3010         if (priv->cfg->ops->lib->isr_ops.reset)
3011                 priv->cfg->ops->lib->isr_ops.reset(priv);
3012
3013         mutex_lock(&priv->mutex);
3014         iwl_alive_start(priv);
3015         mutex_unlock(&priv->mutex);
3016 }
3017
3018 static void iwl_bg_run_time_calib_work(struct work_struct *work)
3019 {
3020         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3021                         run_time_calib_work);
3022
3023         mutex_lock(&priv->mutex);
3024
3025         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3026             test_bit(STATUS_SCANNING, &priv->status)) {
3027                 mutex_unlock(&priv->mutex);
3028                 return;
3029         }
3030
3031         if (priv->start_calib) {
3032                 if (iwl_bt_statistics(priv)) {
3033                         iwl_chain_noise_calibration(priv,
3034                                         (void *)&priv->_agn.statistics_bt);
3035                         iwl_sensitivity_calibration(priv,
3036                                         (void *)&priv->_agn.statistics_bt);
3037                 } else {
3038                         iwl_chain_noise_calibration(priv,
3039                                         (void *)&priv->_agn.statistics);
3040                         iwl_sensitivity_calibration(priv,
3041                                         (void *)&priv->_agn.statistics);
3042                 }
3043         }
3044
3045         mutex_unlock(&priv->mutex);
3046 }
3047
3048 static void iwl_bg_restart(struct work_struct *data)
3049 {
3050         struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
3051
3052         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3053                 return;
3054
3055         if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
3056                 struct iwl_rxon_context *ctx;
3057                 bool bt_full_concurrent;
3058                 u8 bt_ci_compliance;
3059                 u8 bt_load;
3060                 u8 bt_status;
3061
3062                 mutex_lock(&priv->mutex);
3063                 for_each_context(priv, ctx)
3064                         ctx->vif = NULL;
3065                 priv->is_open = 0;
3066
3067                 /*
3068                  * __iwl_down() will clear the BT status variables,
3069                  * which is correct, but when we restart we really
3070                  * want to keep them so restore them afterwards.
3071                  *
3072                  * The restart process will later pick them up and
3073                  * re-configure the hw when we reconfigure the BT
3074                  * command.
3075                  */
3076                 bt_full_concurrent = priv->bt_full_concurrent;
3077                 bt_ci_compliance = priv->bt_ci_compliance;
3078                 bt_load = priv->bt_traffic_load;
3079                 bt_status = priv->bt_status;
3080
3081                 __iwl_down(priv);
3082
3083                 priv->bt_full_concurrent = bt_full_concurrent;
3084                 priv->bt_ci_compliance = bt_ci_compliance;
3085                 priv->bt_traffic_load = bt_load;
3086                 priv->bt_status = bt_status;
3087
3088                 mutex_unlock(&priv->mutex);
3089                 iwl_cancel_deferred_work(priv);
3090                 ieee80211_restart_hw(priv->hw);
3091         } else {
3092                 iwl_down(priv);
3093
3094                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3095                         return;
3096
3097                 mutex_lock(&priv->mutex);
3098                 __iwl_up(priv);
3099                 mutex_unlock(&priv->mutex);
3100         }
3101 }
3102
3103 static void iwl_bg_rx_replenish(struct work_struct *data)
3104 {
3105         struct iwl_priv *priv =
3106             container_of(data, struct iwl_priv, rx_replenish);
3107
3108         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3109                 return;
3110
3111         mutex_lock(&priv->mutex);
3112         iwlagn_rx_replenish(priv);
3113         mutex_unlock(&priv->mutex);
3114 }
3115
3116 /*****************************************************************************
3117  *
3118  * mac80211 entry point functions
3119  *
3120  *****************************************************************************/
3121
3122 #define UCODE_READY_TIMEOUT     (4 * HZ)
3123
3124 /*
3125  * Not a mac80211 entry point function, but it fits in with all the
3126  * other mac80211 functions grouped here.
3127  */
3128 static int iwl_mac_setup_register(struct iwl_priv *priv,
3129                                   struct iwlagn_ucode_capabilities *capa)
3130 {
3131         int ret;
3132         struct ieee80211_hw *hw = priv->hw;
3133         struct iwl_rxon_context *ctx;
3134
3135         hw->rate_control_algorithm = "iwl-agn-rs";
3136
3137         /* Tell mac80211 our characteristics */
3138         hw->flags = IEEE80211_HW_SIGNAL_DBM |
3139                     IEEE80211_HW_AMPDU_AGGREGATION |
3140                     IEEE80211_HW_NEED_DTIM_PERIOD |
3141                     IEEE80211_HW_SPECTRUM_MGMT |
3142                     IEEE80211_HW_REPORTS_TX_ACK_STATUS;
3143
3144         hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3145
3146         if (!priv->cfg->base_params->broken_powersave)
3147                 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
3148                              IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
3149
3150         if (priv->cfg->sku & IWL_SKU_N)
3151                 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
3152                              IEEE80211_HW_SUPPORTS_STATIC_SMPS;
3153
3154         hw->sta_data_size = sizeof(struct iwl_station_priv);
3155         hw->vif_data_size = sizeof(struct iwl_vif_priv);
3156
3157         for_each_context(priv, ctx) {
3158                 hw->wiphy->interface_modes |= ctx->interface_modes;
3159                 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
3160         }
3161
3162         hw->wiphy->max_remain_on_channel_duration = 1000;
3163
3164         hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
3165                             WIPHY_FLAG_DISABLE_BEACON_HINTS |
3166                             WIPHY_FLAG_IBSS_RSN;
3167
3168         /*
3169          * For now, disable PS by default because it affects
3170          * RX performance significantly.
3171          */
3172         hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
3173
3174         hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
3175         /* we create the 802.11 header and a zero-length SSID element */
3176         hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
3177
3178         /* Default value; 4 EDCA QOS priorities */
3179         hw->queues = 4;
3180
3181         hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
3182
3183         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
3184                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3185                         &priv->bands[IEEE80211_BAND_2GHZ];
3186         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
3187                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
3188                         &priv->bands[IEEE80211_BAND_5GHZ];
3189
3190         iwl_leds_init(priv);
3191
3192         ret = ieee80211_register_hw(priv->hw);
3193         if (ret) {
3194                 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
3195                 return ret;
3196         }
3197         priv->mac80211_registered = 1;
3198
3199         return 0;
3200 }
3201
3202
3203 int iwlagn_mac_start(struct ieee80211_hw *hw)
3204 {
3205         struct iwl_priv *priv = hw->priv;
3206         int ret;
3207
3208         IWL_DEBUG_MAC80211(priv, "enter\n");
3209
3210         /* we should be verifying the device is ready to be opened */
3211         mutex_lock(&priv->mutex);
3212         ret = __iwl_up(priv);
3213         mutex_unlock(&priv->mutex);
3214
3215         if (ret)
3216                 return ret;
3217
3218         if (iwl_is_rfkill(priv))
3219                 goto out;
3220
3221         IWL_DEBUG_INFO(priv, "Start UP work done.\n");
3222
3223         /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
3224          * mac80211 will not be run successfully. */
3225         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
3226                         test_bit(STATUS_READY, &priv->status),
3227                         UCODE_READY_TIMEOUT);
3228         if (!ret) {
3229                 if (!test_bit(STATUS_READY, &priv->status)) {
3230                         IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
3231                                 jiffies_to_msecs(UCODE_READY_TIMEOUT));
3232                         return -ETIMEDOUT;
3233                 }
3234         }
3235
3236         iwlagn_led_enable(priv);
3237
3238 out:
3239         priv->is_open = 1;
3240         IWL_DEBUG_MAC80211(priv, "leave\n");
3241         return 0;
3242 }
3243
3244 void iwlagn_mac_stop(struct ieee80211_hw *hw)
3245 {
3246         struct iwl_priv *priv = hw->priv;
3247
3248         IWL_DEBUG_MAC80211(priv, "enter\n");
3249
3250         if (!priv->is_open)
3251                 return;
3252
3253         priv->is_open = 0;
3254
3255         iwl_down(priv);
3256
3257         flush_workqueue(priv->workqueue);
3258
3259         /* User space software may expect getting rfkill changes
3260          * even if interface is down */
3261         iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
3262         iwl_enable_rfkill_int(priv);
3263
3264         IWL_DEBUG_MAC80211(priv, "leave\n");
3265 }
3266
3267 void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
3268 {
3269         struct iwl_priv *priv = hw->priv;
3270
3271         IWL_DEBUG_MACDUMP(priv, "enter\n");
3272
3273         IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
3274                      ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
3275
3276         if (iwlagn_tx_skb(priv, skb))
3277                 dev_kfree_skb_any(skb);
3278
3279         IWL_DEBUG_MACDUMP(priv, "leave\n");
3280 }
3281
3282 void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
3283                                 struct ieee80211_vif *vif,
3284                                 struct ieee80211_key_conf *keyconf,
3285                                 struct ieee80211_sta *sta,
3286                                 u32 iv32, u16 *phase1key)
3287 {
3288         struct iwl_priv *priv = hw->priv;
3289         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3290
3291         IWL_DEBUG_MAC80211(priv, "enter\n");
3292
3293         iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
3294                             iv32, phase1key);
3295
3296         IWL_DEBUG_MAC80211(priv, "leave\n");
3297 }
3298
3299 int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3300                        struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3301                        struct ieee80211_key_conf *key)
3302 {
3303         struct iwl_priv *priv = hw->priv;
3304         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3305         struct iwl_rxon_context *ctx = vif_priv->ctx;
3306         int ret;
3307         u8 sta_id;
3308         bool is_default_wep_key = false;
3309
3310         IWL_DEBUG_MAC80211(priv, "enter\n");
3311
3312         if (priv->cfg->mod_params->sw_crypto) {
3313                 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
3314                 return -EOPNOTSUPP;
3315         }
3316
3317         /*
3318          * To support IBSS RSN, don't program group keys in IBSS, the
3319          * hardware will then not attempt to decrypt the frames.
3320          */
3321         if (vif->type == NL80211_IFTYPE_ADHOC &&
3322             !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
3323                 return -EOPNOTSUPP;
3324
3325         sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
3326         if (sta_id == IWL_INVALID_STATION)
3327                 return -EINVAL;
3328
3329         mutex_lock(&priv->mutex);
3330         iwl_scan_cancel_timeout(priv, 100);
3331
3332         /*
3333          * If we are getting WEP group key and we didn't receive any key mapping
3334          * so far, we are in legacy wep mode (group key only), otherwise we are
3335          * in 1X mode.
3336          * In legacy wep mode, we use another host command to the uCode.
3337          */
3338         if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
3339              key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
3340             !sta) {
3341                 if (cmd == SET_KEY)
3342                         is_default_wep_key = !ctx->key_mapping_keys;
3343                 else
3344                         is_default_wep_key =
3345                                         (key->hw_key_idx == HW_KEY_DEFAULT);
3346         }
3347
3348         switch (cmd) {
3349         case SET_KEY:
3350                 if (is_default_wep_key)
3351                         ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
3352                 else
3353                         ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
3354                                                   key, sta_id);
3355
3356                 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
3357                 break;
3358         case DISABLE_KEY:
3359                 if (is_default_wep_key)
3360                         ret = iwl_remove_default_wep_key(priv, ctx, key);
3361                 else
3362                         ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
3363
3364                 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
3365                 break;
3366         default:
3367                 ret = -EINVAL;
3368         }
3369
3370         mutex_unlock(&priv->mutex);
3371         IWL_DEBUG_MAC80211(priv, "leave\n");
3372
3373         return ret;
3374 }
3375
3376 int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
3377                             struct ieee80211_vif *vif,
3378                             enum ieee80211_ampdu_mlme_action action,
3379                             struct ieee80211_sta *sta, u16 tid, u16 *ssn,
3380                             u8 buf_size)
3381 {
3382         struct iwl_priv *priv = hw->priv;
3383         int ret = -EINVAL;
3384         struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
3385
3386         IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
3387                      sta->addr, tid);
3388
3389         if (!(priv->cfg->sku & IWL_SKU_N))
3390                 return -EACCES;
3391
3392         mutex_lock(&priv->mutex);
3393
3394         switch (action) {
3395         case IEEE80211_AMPDU_RX_START:
3396                 IWL_DEBUG_HT(priv, "start Rx\n");
3397                 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
3398                 break;
3399         case IEEE80211_AMPDU_RX_STOP:
3400                 IWL_DEBUG_HT(priv, "stop Rx\n");
3401                 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
3402                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3403                         ret = 0;
3404                 break;
3405         case IEEE80211_AMPDU_TX_START:
3406                 IWL_DEBUG_HT(priv, "start Tx\n");
3407                 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
3408                 if (ret == 0) {
3409                         priv->_agn.agg_tids_count++;
3410                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3411                                      priv->_agn.agg_tids_count);
3412                 }
3413                 break;
3414         case IEEE80211_AMPDU_TX_STOP:
3415                 IWL_DEBUG_HT(priv, "stop Tx\n");
3416                 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
3417                 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
3418                         priv->_agn.agg_tids_count--;
3419                         IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
3420                                      priv->_agn.agg_tids_count);
3421                 }
3422                 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
3423                         ret = 0;
3424                 if (priv->cfg->ht_params &&
3425                     priv->cfg->ht_params->use_rts_for_aggregation) {
3426                         struct iwl_station_priv *sta_priv =
3427                                 (void *) sta->drv_priv;
3428                         /*
3429                          * switch off RTS/CTS if it was previously enabled
3430                          */
3431
3432                         sta_priv->lq_sta.lq.general_params.flags &=
3433                                 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3434                         iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3435                                         &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3436                 }
3437                 break;
3438         case IEEE80211_AMPDU_TX_OPERATIONAL:
3439                 /*
3440                  * If the limit is 0, then it wasn't initialised yet,
3441                  * use the default. We can do that since we take the
3442                  * minimum below, and we don't want to go above our
3443                  * default due to hardware restrictions.
3444                  */
3445                 if (sta_priv->max_agg_bufsize == 0)
3446                         sta_priv->max_agg_bufsize =
3447                                 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
3448
3449                 /*
3450                  * Even though in theory the peer could have different
3451                  * aggregation reorder buffer sizes for different sessions,
3452                  * our ucode doesn't allow for that and has a global limit
3453                  * for each station. Therefore, use the minimum of all the
3454                  * aggregation sessions and our default value.
3455                  */
3456                 sta_priv->max_agg_bufsize =
3457                         min(sta_priv->max_agg_bufsize, buf_size);
3458
3459                 if (priv->cfg->ht_params &&
3460                     priv->cfg->ht_params->use_rts_for_aggregation) {
3461                         /*
3462                          * switch to RTS/CTS if it is the prefer protection
3463                          * method for HT traffic
3464                          */
3465
3466                         sta_priv->lq_sta.lq.general_params.flags |=
3467                                 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
3468                 }
3469
3470                 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
3471                         sta_priv->max_agg_bufsize;
3472
3473                 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
3474                                 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
3475                 ret = 0;
3476                 break;
3477         }
3478         mutex_unlock(&priv->mutex);
3479
3480         return ret;
3481 }
3482
3483 int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3484                        struct ieee80211_vif *vif,
3485                        struct ieee80211_sta *sta)
3486 {
3487         struct iwl_priv *priv = hw->priv;
3488         struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3489         struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3490         bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3491         int ret;
3492         u8 sta_id;
3493
3494         IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3495                         sta->addr);
3496         mutex_lock(&priv->mutex);
3497         IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3498                         sta->addr);
3499         sta_priv->common.sta_id = IWL_INVALID_STATION;
3500
3501         atomic_set(&sta_priv->pending_frames, 0);
3502         if (vif->type == NL80211_IFTYPE_AP)
3503                 sta_priv->client = true;
3504
3505         ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3506                                      is_ap, sta, &sta_id);
3507         if (ret) {
3508                 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3509                         sta->addr, ret);
3510                 /* Should we return success if return code is EEXIST ? */
3511                 mutex_unlock(&priv->mutex);
3512                 return ret;
3513         }
3514
3515         sta_priv->common.sta_id = sta_id;
3516
3517         /* Initialize rate scaling */
3518         IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3519                        sta->addr);
3520         iwl_rs_rate_init(priv, sta, sta_id);
3521         mutex_unlock(&priv->mutex);
3522
3523         return 0;
3524 }
3525
3526 void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3527                                struct ieee80211_channel_switch *ch_switch)
3528 {
3529         struct iwl_priv *priv = hw->priv;
3530         const struct iwl_channel_info *ch_info;
3531         struct ieee80211_conf *conf = &hw->conf;
3532         struct ieee80211_channel *channel = ch_switch->channel;
3533         struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3534         /*
3535          * MULTI-FIXME
3536          * When we add support for multiple interfaces, we need to
3537          * revisit this. The channel switch command in the device
3538          * only affects the BSS context, but what does that really
3539          * mean? And what if we get a CSA on the second interface?
3540          * This needs a lot of work.
3541          */
3542         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3543         u16 ch;
3544         unsigned long flags = 0;
3545
3546         IWL_DEBUG_MAC80211(priv, "enter\n");
3547
3548         if (iwl_is_rfkill(priv))
3549                 goto out_exit;
3550
3551         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3552             test_bit(STATUS_SCANNING, &priv->status))
3553                 goto out_exit;
3554
3555         if (!iwl_is_associated_ctx(ctx))
3556                 goto out_exit;
3557
3558         /* channel switch in progress */
3559         if (priv->switch_rxon.switch_in_progress == true)
3560                 goto out_exit;
3561
3562         mutex_lock(&priv->mutex);
3563         if (priv->cfg->ops->lib->set_channel_switch) {
3564
3565                 ch = channel->hw_value;
3566                 if (le16_to_cpu(ctx->active.channel) != ch) {
3567                         ch_info = iwl_get_channel_info(priv,
3568                                                        channel->band,
3569                                                        ch);
3570                         if (!is_channel_valid(ch_info)) {
3571                                 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3572                                 goto out;
3573                         }
3574                         spin_lock_irqsave(&priv->lock, flags);
3575
3576                         priv->current_ht_config.smps = conf->smps_mode;
3577
3578                         /* Configure HT40 channels */
3579                         ctx->ht.enabled = conf_is_ht(conf);
3580                         if (ctx->ht.enabled) {
3581                                 if (conf_is_ht40_minus(conf)) {
3582                                         ctx->ht.extension_chan_offset =
3583                                                 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3584                                         ctx->ht.is_40mhz = true;
3585                                 } else if (conf_is_ht40_plus(conf)) {
3586                                         ctx->ht.extension_chan_offset =
3587                                                 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3588                                         ctx->ht.is_40mhz = true;
3589                                 } else {
3590                                         ctx->ht.extension_chan_offset =
3591                                                 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3592                                         ctx->ht.is_40mhz = false;
3593                                 }
3594                         } else
3595                                 ctx->ht.is_40mhz = false;
3596
3597                         if ((le16_to_cpu(ctx->staging.channel) != ch))
3598                                 ctx->staging.flags = 0;
3599
3600                         iwl_set_rxon_channel(priv, channel, ctx);
3601                         iwl_set_rxon_ht(priv, ht_conf);
3602                         iwl_set_flags_for_band(priv, ctx, channel->band,
3603                                                ctx->vif);
3604                         spin_unlock_irqrestore(&priv->lock, flags);
3605
3606                         iwl_set_rate(priv);
3607                         /*
3608                          * at this point, staging_rxon has the
3609                          * configuration for channel switch
3610                          */
3611                         if (priv->cfg->ops->lib->set_channel_switch(priv,
3612                                                                     ch_switch))
3613                                 priv->switch_rxon.switch_in_progress = false;
3614                 }
3615         }
3616 out:
3617         mutex_unlock(&priv->mutex);
3618 out_exit:
3619         if (!priv->switch_rxon.switch_in_progress)
3620                 ieee80211_chswitch_done(ctx->vif, false);
3621         IWL_DEBUG_MAC80211(priv, "leave\n");
3622 }
3623
3624 void iwlagn_configure_filter(struct ieee80211_hw *hw,
3625                              unsigned int changed_flags,
3626                              unsigned int *total_flags,
3627                              u64 multicast)
3628 {
3629         struct iwl_priv *priv = hw->priv;
3630         __le32 filter_or = 0, filter_nand = 0;
3631         struct iwl_rxon_context *ctx;
3632
3633 #define CHK(test, flag) do { \
3634         if (*total_flags & (test))              \
3635                 filter_or |= (flag);            \
3636         else                                    \
3637                 filter_nand |= (flag);          \
3638         } while (0)
3639
3640         IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3641                         changed_flags, *total_flags);
3642
3643         CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3644         /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3645         CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3646         CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3647
3648 #undef CHK
3649
3650         mutex_lock(&priv->mutex);
3651
3652         for_each_context(priv, ctx) {
3653                 ctx->staging.filter_flags &= ~filter_nand;
3654                 ctx->staging.filter_flags |= filter_or;
3655
3656                 /*
3657                  * Not committing directly because hardware can perform a scan,
3658                  * but we'll eventually commit the filter flags change anyway.
3659                  */
3660         }
3661
3662         mutex_unlock(&priv->mutex);
3663
3664         /*
3665          * Receiving all multicast frames is always enabled by the
3666          * default flags setup in iwl_connection_init_rx_config()
3667          * since we currently do not support programming multicast
3668          * filters into the device.
3669          */
3670         *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3671                         FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3672 }
3673
3674 void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3675 {
3676         struct iwl_priv *priv = hw->priv;
3677
3678         mutex_lock(&priv->mutex);
3679         IWL_DEBUG_MAC80211(priv, "enter\n");
3680
3681         /* do not support "flush" */
3682         if (!priv->cfg->ops->lib->txfifo_flush)
3683                 goto done;
3684
3685         if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3686                 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3687                 goto done;
3688         }
3689         if (iwl_is_rfkill(priv)) {
3690                 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3691                 goto done;
3692         }
3693
3694         /*
3695          * mac80211 will not push any more frames for transmit
3696          * until the flush is completed
3697          */
3698         if (drop) {
3699                 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3700                 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3701                         IWL_ERR(priv, "flush request fail\n");
3702                         goto done;
3703                 }
3704         }
3705         IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3706         iwlagn_wait_tx_queue_empty(priv);
3707 done:
3708         mutex_unlock(&priv->mutex);
3709         IWL_DEBUG_MAC80211(priv, "leave\n");
3710 }
3711
3712 static void iwlagn_disable_roc(struct iwl_priv *priv)
3713 {
3714         struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3715         struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3716
3717         lockdep_assert_held(&priv->mutex);
3718
3719         if (!ctx->is_active)
3720                 return;
3721
3722         ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3723         ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3724         iwl_set_rxon_channel(priv, chan, ctx);
3725         iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3726
3727         priv->_agn.hw_roc_channel = NULL;
3728
3729         iwlcore_commit_rxon(priv, ctx);
3730
3731         ctx->is_active = false;
3732 }
3733
3734 static void iwlagn_bg_roc_done(struct work_struct *work)
3735 {
3736         struct iwl_priv *priv = container_of(work, struct iwl_priv,
3737                                              _agn.hw_roc_work.work);
3738
3739         mutex_lock(&priv->mutex);
3740         ieee80211_remain_on_channel_expired(priv->hw);
3741         iwlagn_disable_roc(priv);
3742         mutex_unlock(&priv->mutex);
3743 }
3744
3745 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3746                                      struct ieee80211_channel *channel,
3747                                      enum nl80211_channel_type channel_type,
3748                                      int duration)
3749 {
3750         struct iwl_priv *priv = hw->priv;
3751         int err = 0;
3752
3753         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3754                 return -EOPNOTSUPP;
3755
3756         if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3757                                         BIT(NL80211_IFTYPE_P2P_CLIENT)))
3758                 return -EOPNOTSUPP;
3759
3760         mutex_lock(&priv->mutex);
3761
3762         if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3763             test_bit(STATUS_SCAN_HW, &priv->status)) {
3764                 err = -EBUSY;
3765                 goto out;
3766         }
3767
3768         priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3769         priv->_agn.hw_roc_channel = channel;
3770         priv->_agn.hw_roc_chantype = channel_type;
3771         priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3772         iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3773         queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3774                            msecs_to_jiffies(duration + 20));
3775
3776         msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3777         ieee80211_ready_on_channel(priv->hw);
3778
3779  out:
3780         mutex_unlock(&priv->mutex);
3781
3782         return err;
3783 }
3784
3785 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3786 {
3787         struct iwl_priv *priv = hw->priv;
3788
3789         if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3790                 return -EOPNOTSUPP;
3791
3792         cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3793
3794         mutex_lock(&priv->mutex);
3795         iwlagn_disable_roc(priv);
3796         mutex_unlock(&priv->mutex);
3797
3798         return 0;
3799 }
3800
3801 /*****************************************************************************
3802  *
3803  * driver setup and teardown
3804  *
3805  *****************************************************************************/
3806
3807 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3808 {
3809         priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3810
3811         init_waitqueue_head(&priv->wait_command_queue);
3812
3813         INIT_WORK(&priv->restart, iwl_bg_restart);
3814         INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3815         INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3816         INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3817         INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3818         INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3819         INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3820         INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
3821         INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
3822         INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3823
3824         iwl_setup_scan_deferred_work(priv);
3825
3826         if (priv->cfg->ops->lib->setup_deferred_work)
3827                 priv->cfg->ops->lib->setup_deferred_work(priv);
3828
3829         init_timer(&priv->statistics_periodic);
3830         priv->statistics_periodic.data = (unsigned long)priv;
3831         priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3832
3833         init_timer(&priv->ucode_trace);
3834         priv->ucode_trace.data = (unsigned long)priv;
3835         priv->ucode_trace.function = iwl_bg_ucode_trace;
3836
3837         init_timer(&priv->watchdog);
3838         priv->watchdog.data = (unsigned long)priv;
3839         priv->watchdog.function = iwl_bg_watchdog;
3840
3841         if (!priv->cfg->base_params->use_isr_legacy)
3842                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3843                         iwl_irq_tasklet, (unsigned long)priv);
3844         else
3845                 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3846                         iwl_irq_tasklet_legacy, (unsigned long)priv);
3847 }
3848
3849 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3850 {
3851         if (priv->cfg->ops->lib->cancel_deferred_work)
3852                 priv->cfg->ops->lib->cancel_deferred_work(priv);
3853
3854         cancel_delayed_work_sync(&priv->init_alive_start);
3855         cancel_delayed_work(&priv->alive_start);
3856         cancel_work_sync(&priv->run_time_calib_work);
3857         cancel_work_sync(&priv->beacon_update);
3858
3859         iwl_cancel_scan_deferred_work(priv);
3860
3861         cancel_work_sync(&priv->bt_full_concurrency);
3862         cancel_work_sync(&priv->bt_runtime_config);
3863
3864         del_timer_sync(&priv->statistics_periodic);
3865         del_timer_sync(&priv->ucode_trace);
3866 }
3867
3868 static void iwl_init_hw_rates(struct iwl_priv *priv,
3869                               struct ieee80211_rate *rates)
3870 {
3871         int i;
3872
3873         for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3874                 rates[i].bitrate = iwl_rates[i].ieee * 5;
3875                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3876                 rates[i].hw_value_short = i;
3877                 rates[i].flags = 0;
3878                 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3879                         /*
3880                          * If CCK != 1M then set short preamble rate flag.
3881                          */
3882                         rates[i].flags |=
3883                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3884                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
3885                 }
3886         }
3887 }
3888
3889 static int iwl_init_drv(struct iwl_priv *priv)
3890 {
3891         int ret;
3892
3893         spin_lock_init(&priv->sta_lock);
3894         spin_lock_init(&priv->hcmd_lock);
3895
3896         INIT_LIST_HEAD(&priv->free_frames);
3897
3898         mutex_init(&priv->mutex);
3899         mutex_init(&priv->sync_cmd_mutex);
3900
3901         priv->ieee_channels = NULL;
3902         priv->ieee_rates = NULL;
3903         priv->band = IEEE80211_BAND_2GHZ;
3904
3905         priv->iw_mode = NL80211_IFTYPE_STATION;
3906         priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3907         priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3908         priv->_agn.agg_tids_count = 0;
3909
3910         /* initialize force reset */
3911         priv->force_reset[IWL_RF_RESET].reset_duration =
3912                 IWL_DELAY_NEXT_FORCE_RF_RESET;
3913         priv->force_reset[IWL_FW_RESET].reset_duration =
3914                 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3915
3916         /* Choose which receivers/antennas to use */
3917         if (priv->cfg->ops->hcmd->set_rxon_chain)
3918                 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3919                                         &priv->contexts[IWL_RXON_CTX_BSS]);
3920
3921         iwl_init_scan_params(priv);
3922
3923         /* init bt coex */
3924         if (priv->cfg->bt_params &&
3925             priv->cfg->bt_params->advanced_bt_coexist) {
3926                 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3927                 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3928                 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3929                 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3930                 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3931                 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3932         }
3933
3934         /* Set the tx_power_user_lmt to the lowest power level
3935          * this value will get overwritten by channel max power avg
3936          * from eeprom */
3937         priv->tx_power_user_lmt = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3938         priv->tx_power_next = IWLAGN_TX_POWER_TARGET_POWER_MIN;
3939
3940         ret = iwl_init_channel_map(priv);
3941         if (ret) {
3942                 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3943                 goto err;
3944         }
3945
3946         ret = iwlcore_init_geos(priv);
3947         if (ret) {
3948                 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3949                 goto err_free_channel_map;
3950         }
3951         iwl_init_hw_rates(priv, priv->ieee_rates);
3952
3953         return 0;
3954
3955 err_free_channel_map:
3956         iwl_free_channel_map(priv);
3957 err:
3958         return ret;
3959 }
3960
3961 static void iwl_uninit_drv(struct iwl_priv *priv)
3962 {
3963         iwl_calib_free_results(priv);
3964         iwlcore_free_geos(priv);
3965         iwl_free_channel_map(priv);
3966         kfree(priv->scan_cmd);
3967 }
3968
3969 struct ieee80211_ops iwlagn_hw_ops = {
3970         .tx = iwlagn_mac_tx,
3971         .start = iwlagn_mac_start,
3972         .stop = iwlagn_mac_stop,
3973         .add_interface = iwl_mac_add_interface,
3974         .remove_interface = iwl_mac_remove_interface,
3975         .change_interface = iwl_mac_change_interface,
3976         .config = iwlagn_mac_config,
3977         .configure_filter = iwlagn_configure_filter,
3978         .set_key = iwlagn_mac_set_key,
3979         .update_tkip_key = iwlagn_mac_update_tkip_key,
3980         .conf_tx = iwl_mac_conf_tx,
3981         .bss_info_changed = iwlagn_bss_info_changed,
3982         .ampdu_action = iwlagn_mac_ampdu_action,
3983         .hw_scan = iwl_mac_hw_scan,
3984         .sta_notify = iwlagn_mac_sta_notify,
3985         .sta_add = iwlagn_mac_sta_add,
3986         .sta_remove = iwl_mac_sta_remove,
3987         .channel_switch = iwlagn_mac_channel_switch,
3988         .flush = iwlagn_mac_flush,
3989         .tx_last_beacon = iwl_mac_tx_last_beacon,
3990         .remain_on_channel = iwl_mac_remain_on_channel,
3991         .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3992 };
3993
3994 static void iwl_hw_detect(struct iwl_priv *priv)
3995 {
3996         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
3997         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
3998         priv->rev_id = priv->pci_dev->revision;
3999         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", priv->rev_id);
4000 }
4001
4002 static int iwl_set_hw_params(struct iwl_priv *priv)
4003 {
4004         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
4005         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
4006         if (priv->cfg->mod_params->amsdu_size_8K)
4007                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
4008         else
4009                 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
4010
4011         priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
4012
4013         if (priv->cfg->mod_params->disable_11n)
4014                 priv->cfg->sku &= ~IWL_SKU_N;
4015
4016         /* Device-specific setup */
4017         return priv->cfg->ops->lib->set_hw_params(priv);
4018 }
4019
4020 static const u8 iwlagn_bss_ac_to_fifo[] = {
4021         IWL_TX_FIFO_VO,
4022         IWL_TX_FIFO_VI,
4023         IWL_TX_FIFO_BE,
4024         IWL_TX_FIFO_BK,
4025 };
4026
4027 static const u8 iwlagn_bss_ac_to_queue[] = {
4028         0, 1, 2, 3,
4029 };
4030
4031 static const u8 iwlagn_pan_ac_to_fifo[] = {
4032         IWL_TX_FIFO_VO_IPAN,
4033         IWL_TX_FIFO_VI_IPAN,
4034         IWL_TX_FIFO_BE_IPAN,
4035         IWL_TX_FIFO_BK_IPAN,
4036 };
4037
4038 static const u8 iwlagn_pan_ac_to_queue[] = {
4039         7, 6, 5, 4,
4040 };
4041
4042 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
4043 {
4044         int err = 0, i;
4045         struct iwl_priv *priv;
4046         struct ieee80211_hw *hw;
4047         struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
4048         unsigned long flags;
4049         u16 pci_cmd, num_mac;
4050
4051         /************************
4052          * 1. Allocating HW data
4053          ************************/
4054
4055         /* Disabling hardware scan means that mac80211 will perform scans
4056          * "the hard way", rather than using device's scan. */
4057         if (cfg->mod_params->disable_hw_scan) {
4058                 dev_printk(KERN_DEBUG, &(pdev->dev),
4059                         "sw scan support is deprecated\n");
4060                 iwlagn_hw_ops.hw_scan = NULL;
4061         }
4062
4063         hw = iwl_alloc_all(cfg);
4064         if (!hw) {
4065                 err = -ENOMEM;
4066                 goto out;
4067         }
4068         priv = hw->priv;
4069         /* At this point both hw and priv are allocated. */
4070
4071         /*
4072          * The default context is always valid,
4073          * more may be discovered when firmware
4074          * is loaded.
4075          */
4076         priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
4077
4078         for (i = 0; i < NUM_IWL_RXON_CTX; i++)
4079                 priv->contexts[i].ctxid = i;
4080
4081         priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
4082         priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
4083         priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
4084         priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
4085         priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
4086         priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
4087         priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
4088         priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
4089         priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
4090         priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
4091         priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
4092                 BIT(NL80211_IFTYPE_ADHOC);
4093         priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
4094                 BIT(NL80211_IFTYPE_STATION);
4095         priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
4096         priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
4097         priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
4098         priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
4099
4100         priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
4101         priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
4102         priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
4103         priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
4104         priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
4105         priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
4106         priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
4107         priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
4108         priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
4109         priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
4110         priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
4111         priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
4112                 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
4113 #ifdef CONFIG_IWL_P2P
4114         priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
4115                 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
4116 #endif
4117         priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
4118         priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
4119         priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
4120
4121         BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
4122
4123         SET_IEEE80211_DEV(hw, &pdev->dev);
4124
4125         IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
4126         priv->cfg = cfg;
4127         priv->pci_dev = pdev;
4128         priv->inta_mask = CSR_INI_SET_MASK;
4129
4130         /* is antenna coupling more than 35dB ? */
4131         priv->bt_ant_couple_ok =
4132                 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
4133                 true : false;
4134
4135         /* enable/disable bt channel inhibition */
4136         priv->bt_ch_announce = iwlagn_bt_ch_announce;
4137         IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
4138                        (priv->bt_ch_announce) ? "On" : "Off");
4139
4140         if (iwl_alloc_traffic_mem(priv))
4141                 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
4142
4143         /**************************
4144          * 2. Initializing PCI bus
4145          **************************/
4146         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
4147                                 PCIE_LINK_STATE_CLKPM);
4148
4149         if (pci_enable_device(pdev)) {
4150                 err = -ENODEV;
4151                 goto out_ieee80211_free_hw;
4152         }
4153
4154         pci_set_master(pdev);
4155
4156         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
4157         if (!err)
4158                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
4159         if (err) {
4160                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4161                 if (!err)
4162                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4163                 /* both attempts failed: */
4164                 if (err) {
4165                         IWL_WARN(priv, "No suitable DMA available.\n");
4166                         goto out_pci_disable_device;
4167                 }
4168         }
4169
4170         err = pci_request_regions(pdev, DRV_NAME);
4171         if (err)
4172                 goto out_pci_disable_device;
4173
4174         pci_set_drvdata(pdev, priv);
4175
4176
4177         /***********************
4178          * 3. Read REV register
4179          ***********************/
4180         priv->hw_base = pci_iomap(pdev, 0, 0);
4181         if (!priv->hw_base) {
4182                 err = -ENODEV;
4183                 goto out_pci_release_regions;
4184         }
4185
4186         IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
4187                 (unsigned long long) pci_resource_len(pdev, 0));
4188         IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
4189
4190         /* these spin locks will be used in apm_ops.init and EEPROM access
4191          * we should init now
4192          */
4193         spin_lock_init(&priv->reg_lock);
4194         spin_lock_init(&priv->lock);
4195
4196         /*
4197          * stop and reset the on-board processor just in case it is in a
4198          * strange state ... like being left stranded by a primary kernel
4199          * and this is now the kdump kernel trying to start up
4200          */
4201         iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
4202
4203         iwl_hw_detect(priv);
4204         IWL_INFO(priv, "Detected %s, REV=0x%X\n",
4205                 priv->cfg->name, priv->hw_rev);
4206
4207         /* We disable the RETRY_TIMEOUT register (0x41) to keep
4208          * PCI Tx retries from interfering with C3 CPU state */
4209         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
4210
4211         iwl_prepare_card_hw(priv);
4212         if (!priv->hw_ready) {
4213                 IWL_WARN(priv, "Failed, HW not ready\n");
4214                 goto out_iounmap;
4215         }
4216
4217         /*****************
4218          * 4. Read EEPROM
4219          *****************/
4220         /* Read the EEPROM */
4221         err = iwl_eeprom_init(priv);
4222         if (err) {
4223                 IWL_ERR(priv, "Unable to init EEPROM\n");
4224                 goto out_iounmap;
4225         }
4226         err = iwl_eeprom_check_version(priv);
4227         if (err)
4228                 goto out_free_eeprom;
4229
4230         err = iwl_eeprom_check_sku(priv);
4231         if (err)
4232                 goto out_free_eeprom;
4233
4234         /* extract MAC Address */
4235         iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
4236         IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
4237         priv->hw->wiphy->addresses = priv->addresses;
4238         priv->hw->wiphy->n_addresses = 1;
4239         num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
4240         if (num_mac > 1) {
4241                 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
4242                        ETH_ALEN);
4243                 priv->addresses[1].addr[5]++;
4244                 priv->hw->wiphy->n_addresses++;
4245         }
4246
4247         /************************
4248          * 5. Setup HW constants
4249          ************************/
4250         if (iwl_set_hw_params(priv)) {
4251                 IWL_ERR(priv, "failed to set hw parameters\n");
4252                 goto out_free_eeprom;
4253         }
4254
4255         /*******************
4256          * 6. Setup priv
4257          *******************/
4258
4259         err = iwl_init_drv(priv);
4260         if (err)
4261                 goto out_free_eeprom;
4262         /* At this point both hw and priv are initialized. */
4263
4264         /********************
4265          * 7. Setup services
4266          ********************/
4267         spin_lock_irqsave(&priv->lock, flags);
4268         iwl_disable_interrupts(priv);
4269         spin_unlock_irqrestore(&priv->lock, flags);
4270
4271         pci_enable_msi(priv->pci_dev);
4272
4273         if (priv->cfg->ops->lib->isr_ops.alloc)
4274                 priv->cfg->ops->lib->isr_ops.alloc(priv);
4275
4276         err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr_ops.isr,
4277                           IRQF_SHARED, DRV_NAME, priv);
4278         if (err) {
4279                 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
4280                 goto out_disable_msi;
4281         }
4282
4283         iwl_setup_deferred_work(priv);
4284         iwl_setup_rx_handlers(priv);
4285
4286         /*********************************************
4287          * 8. Enable interrupts and read RFKILL state
4288          *********************************************/
4289
4290         /* enable rfkill interrupt: hw bug w/a */
4291         pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
4292         if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
4293                 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
4294                 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
4295         }
4296
4297         iwl_enable_rfkill_int(priv);
4298
4299         /* If platform's RF_KILL switch is NOT set to KILL */
4300         if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
4301                 clear_bit(STATUS_RF_KILL_HW, &priv->status);
4302         else
4303                 set_bit(STATUS_RF_KILL_HW, &priv->status);
4304
4305         wiphy_rfkill_set_hw_state(priv->hw->wiphy,
4306                 test_bit(STATUS_RF_KILL_HW, &priv->status));
4307
4308         iwl_power_initialize(priv);
4309         iwl_tt_initialize(priv);
4310
4311         init_completion(&priv->_agn.firmware_loading_complete);
4312
4313         err = iwl_request_firmware(priv, true);
4314         if (err)
4315                 goto out_destroy_workqueue;
4316
4317         return 0;
4318
4319  out_destroy_workqueue:
4320         destroy_workqueue(priv->workqueue);
4321         priv->workqueue = NULL;
4322         free_irq(priv->pci_dev->irq, priv);
4323         if (priv->cfg->ops->lib->isr_ops.free)
4324                 priv->cfg->ops->lib->isr_ops.free(priv);
4325  out_disable_msi:
4326         pci_disable_msi(priv->pci_dev);
4327         iwl_uninit_drv(priv);
4328  out_free_eeprom:
4329         iwl_eeprom_free(priv);
4330  out_iounmap:
4331         pci_iounmap(pdev, priv->hw_base);
4332  out_pci_release_regions:
4333         pci_set_drvdata(pdev, NULL);
4334         pci_release_regions(pdev);
4335  out_pci_disable_device:
4336         pci_disable_device(pdev);
4337  out_ieee80211_free_hw:
4338         iwl_free_traffic_mem(priv);
4339         ieee80211_free_hw(priv->hw);
4340  out:
4341         return err;
4342 }
4343
4344 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
4345 {
4346         struct iwl_priv *priv = pci_get_drvdata(pdev);
4347         unsigned long flags;
4348
4349         if (!priv)
4350                 return;
4351
4352         wait_for_completion(&priv->_agn.firmware_loading_complete);
4353
4354         IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
4355
4356         iwl_dbgfs_unregister(priv);
4357         sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
4358
4359         /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4360          * to be called and iwl_down since we are removing the device
4361          * we need to set STATUS_EXIT_PENDING bit.
4362          */
4363         set_bit(STATUS_EXIT_PENDING, &priv->status);
4364
4365         iwl_leds_exit(priv);
4366
4367         if (priv->mac80211_registered) {
4368                 ieee80211_unregister_hw(priv->hw);
4369                 priv->mac80211_registered = 0;
4370         } else {
4371                 iwl_down(priv);
4372         }
4373
4374         /*
4375          * Make sure device is reset to low power before unloading driver.
4376          * This may be redundant with iwl_down(), but there are paths to
4377          * run iwl_down() without calling apm_ops.stop(), and there are
4378          * paths to avoid running iwl_down() at all before leaving driver.
4379          * This (inexpensive) call *makes sure* device is reset.
4380          */
4381         iwl_apm_stop(priv);
4382
4383         iwl_tt_exit(priv);
4384
4385         /* make sure we flush any pending irq or
4386          * tasklet for the driver
4387          */
4388         spin_lock_irqsave(&priv->lock, flags);
4389         iwl_disable_interrupts(priv);
4390         spin_unlock_irqrestore(&priv->lock, flags);
4391
4392         iwl_synchronize_irq(priv);
4393
4394         iwl_dealloc_ucode_pci(priv);
4395
4396         if (priv->rxq.bd)
4397                 iwlagn_rx_queue_free(priv, &priv->rxq);
4398         iwlagn_hw_txq_ctx_free(priv);
4399
4400         iwl_eeprom_free(priv);
4401
4402
4403         /*netif_stop_queue(dev); */
4404         flush_workqueue(priv->workqueue);
4405
4406         /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4407          * priv->workqueue... so we can't take down the workqueue
4408          * until now... */
4409         destroy_workqueue(priv->workqueue);
4410         priv->workqueue = NULL;
4411         iwl_free_traffic_mem(priv);
4412
4413         free_irq(priv->pci_dev->irq, priv);
4414         pci_disable_msi(priv->pci_dev);
4415         pci_iounmap(pdev, priv->hw_base);
4416         pci_release_regions(pdev);
4417         pci_disable_device(pdev);
4418         pci_set_drvdata(pdev, NULL);
4419
4420         iwl_uninit_drv(priv);
4421
4422         if (priv->cfg->ops->lib->isr_ops.free)
4423                 priv->cfg->ops->lib->isr_ops.free(priv);
4424
4425         dev_kfree_skb(priv->beacon_skb);
4426
4427         ieee80211_free_hw(priv->hw);
4428 }
4429
4430
4431 /*****************************************************************************
4432  *
4433  * driver and module entry point
4434  *
4435  *****************************************************************************/
4436
4437 /* Hardware specific file defines the PCI IDs table for that hardware module */
4438 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
4439         {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
4440         {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
4441         {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
4442         {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
4443         {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
4444         {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
4445         {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
4446         {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
4447         {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
4448         {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
4449         {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
4450         {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
4451         {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
4452         {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
4453         {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
4454         {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
4455         {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
4456         {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
4457         {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
4458         {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
4459         {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
4460         {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
4461         {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
4462         {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
4463
4464 /* 5300 Series WiFi */
4465         {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
4466         {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
4467         {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
4468         {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
4469         {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
4470         {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
4471         {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
4472         {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
4473         {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
4474         {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
4475         {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
4476         {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
4477
4478 /* 5350 Series WiFi/WiMax */
4479         {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
4480         {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
4481         {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
4482
4483 /* 5150 Series Wifi/WiMax */
4484         {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4485         {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4486         {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4487         {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4488         {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4489         {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4490
4491         {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4492         {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4493         {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4494         {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4495
4496 /* 6x00 Series */
4497         {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4498         {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4499         {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4500         {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4501         {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4502         {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4503         {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4504         {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4505         {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4506         {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4507
4508 /* 6x05 Series */
4509         {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4510         {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4511         {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4512         {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4513         {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4514         {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4515         {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4516
4517 /* 6x30 Series */
4518         {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4519         {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4520         {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4521         {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4522         {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4523         {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4524         {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4525         {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4526         {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4527         {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4528         {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4529         {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4530         {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4531         {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4532         {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4533         {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4534
4535 /* 6x50 WiFi/WiMax Series */
4536         {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4537         {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4538         {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4539         {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4540         {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4541         {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4542
4543 /* 6150 WiFi/WiMax Series */
4544         {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4545         {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4546         {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4547         {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4548         {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4549         {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4550
4551 /* 1000 Series WiFi */
4552         {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4553         {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4554         {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4555         {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4556         {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4557         {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4558         {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4559         {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4560         {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4561         {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4562         {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4563         {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4564
4565 /* 100 Series WiFi */
4566         {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4567         {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4568         {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4569         {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4570         {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4571         {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4572
4573 /* 130 Series WiFi */
4574         {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4575         {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4576         {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4577         {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4578         {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4579         {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4580
4581 /* 2x00 Series */
4582         {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4583         {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4584         {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4585         {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4586         {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4587         {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4588
4589 /* 2x30 Series */
4590         {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4591         {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4592         {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4593         {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4594         {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4595         {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4596
4597 /* 6x35 Series */
4598         {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4599         {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4600         {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4601         {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4602         {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4603         {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4604         {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4605         {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4606         {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4607
4608 /* 200 Series */
4609         {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4610         {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4611         {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4612         {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4613         {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4614         {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4615
4616 /* 230 Series */
4617         {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4618         {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4619         {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4620         {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4621         {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4622         {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4623
4624         {0}
4625 };
4626 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4627
4628 static struct pci_driver iwl_driver = {
4629         .name = DRV_NAME,
4630         .id_table = iwl_hw_card_ids,
4631         .probe = iwl_pci_probe,
4632         .remove = __devexit_p(iwl_pci_remove),
4633         .driver.pm = IWL_PM_OPS,
4634 };
4635
4636 static int __init iwl_init(void)
4637 {
4638
4639         int ret;
4640         pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4641         pr_info(DRV_COPYRIGHT "\n");
4642
4643         ret = iwlagn_rate_control_register();
4644         if (ret) {
4645                 pr_err("Unable to register rate control algorithm: %d\n", ret);
4646                 return ret;
4647         }
4648
4649         ret = pci_register_driver(&iwl_driver);
4650         if (ret) {
4651                 pr_err("Unable to initialize PCI module\n");
4652                 goto error_register;
4653         }
4654
4655         return ret;
4656
4657 error_register:
4658         iwlagn_rate_control_unregister();
4659         return ret;
4660 }
4661
4662 static void __exit iwl_exit(void)
4663 {
4664         pci_unregister_driver(&iwl_driver);
4665         iwlagn_rate_control_unregister();
4666 }
4667
4668 module_exit(iwl_exit);
4669 module_init(iwl_init);
4670
4671 #ifdef CONFIG_IWLWIFI_DEBUG
4672 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
4673 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
4674 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4675 MODULE_PARM_DESC(debug, "debug output mask");
4676 #endif
4677
4678 module_param_named(swcrypto50, iwlagn_mod_params.sw_crypto, bool, S_IRUGO);
4679 MODULE_PARM_DESC(swcrypto50,
4680                  "using crypto in software (default 0 [hardware]) (deprecated)");
4681 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4682 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4683 module_param_named(queues_num50,
4684                    iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4685 MODULE_PARM_DESC(queues_num50,
4686                  "number of hw queues in 50xx series (deprecated)");
4687 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4688 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4689 module_param_named(11n_disable50, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4690 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality (deprecated)");
4691 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4692 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4693 module_param_named(amsdu_size_8K50, iwlagn_mod_params.amsdu_size_8K,
4694                    int, S_IRUGO);
4695 MODULE_PARM_DESC(amsdu_size_8K50,
4696                  "enable 8K amsdu size in 50XX series (deprecated)");
4697 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4698                    int, S_IRUGO);
4699 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4700 module_param_named(fw_restart50, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4701 MODULE_PARM_DESC(fw_restart50,
4702                  "restart firmware in case of error (deprecated)");
4703 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4704 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4705 module_param_named(
4706         disable_hw_scan, iwlagn_mod_params.disable_hw_scan, int, S_IRUGO);
4707 MODULE_PARM_DESC(disable_hw_scan,
4708                  "disable hardware scanning (default 0) (deprecated)");
4709
4710 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4711                    S_IRUGO);
4712 MODULE_PARM_DESC(ucode_alternative,
4713                  "specify ucode alternative to use from ucode file");
4714
4715 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4716 MODULE_PARM_DESC(antenna_coupling,
4717                  "specify antenna coupling in dB (defualt: 0 dB)");
4718
4719 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4720 MODULE_PARM_DESC(bt_ch_inhibition,
4721                  "Disable BT channel inhibition (default: enable)");
4722
4723 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4724 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4725
4726 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4727 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");