drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/wireless.h>
  35 #include <net/mac80211.h>
  36 #include <linux/etherdevice.h>
  37 #include <asm/unaligned.h>
  38
  39 #include "iwl-eeprom.h"
  40 #include "iwl-dev.h"
  41 #include "iwl-core.h"
  42 #include "iwl-io.h"
  43 #include "iwl-sta.h"
  44 #include "iwl-helpers.h"
  45 #include "iwl-5000-hw.h"
  46
  47 /* Highest firmware API version supported */
  48 #define IWL5000_UCODE_API_MAX 1
  49 #define IWL5150_UCODE_API_MAX 1
  50
  51 /* Lowest firmware API version supported */
  52 #define IWL5000_UCODE_API_MIN 1
  53 #define IWL5150_UCODE_API_MIN 1
  54
  55 #define IWL5000_FW_PRE "iwlwifi-5000-"
  56 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  57 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  58
  59 #define IWL5150_FW_PRE "iwlwifi-5150-"
  60 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  61 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  62
  63 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  64         IWL_TX_FIFO_AC3,
  65         IWL_TX_FIFO_AC2,
  66         IWL_TX_FIFO_AC1,
  67         IWL_TX_FIFO_AC0,
  68         IWL50_CMD_FIFO_NUM,
  69         IWL_TX_FIFO_HCCA_1,
  70         IWL_TX_FIFO_HCCA_2
  71 };
  72
  73 /* FIXME: same implementation as 4965 */
  74 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  75 {
  76         unsigned long flags;
  77
  78         spin_lock_irqsave(&priv->lock, flags);
  79
  80         /* set stop master bit */
  81         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  82
  83         iwl_poll_direct_bit(priv, CSR_RESET,
  84                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  85
  86         spin_unlock_irqrestore(&priv->lock, flags);
  87         IWL_DEBUG_INFO("stop master\n");
  88
  89         return 0;
  90 }
  91
  92
  93 static int iwl5000_apm_init(struct iwl_priv *priv)
  94 {
  95         int ret = 0;
  96
  97         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  98                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  99
 100         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 101         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 102                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 103
 104         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 105         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 106
 107         /* enable HAP INTA to move device L1a -> L0s */
 108         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 109                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 110
 111         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 112
 113         /* set "initialization complete" bit to move adapter
 114          * D0U* --> D0A* state */
 115         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 116
 117         /* wait for clock stabilization */
 118         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 119                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 120         if (ret < 0) {
 121                 IWL_DEBUG_INFO("Failed to init the card\n");
 122                 return ret;
 123         }
 124
 125         ret = iwl_grab_nic_access(priv);
 126         if (ret)
 127                 return ret;
 128
 129         /* enable DMA */
 130         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 131
 132         udelay(20);
 133
 134         /* disable L1-Active */
 135         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 136                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 137
 138         iwl_release_nic_access(priv);
 139
 140         return ret;
 141 }
 142
 143 /* FIXME: this is identical to 4965 */
 144 static void iwl5000_apm_stop(struct iwl_priv *priv)
 145 {
 146         unsigned long flags;
 147
 148         iwl5000_apm_stop_master(priv);
 149
 150         spin_lock_irqsave(&priv->lock, flags);
 151
 152         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 153
 154         udelay(10);
 155
 156         /* clear "init complete"  move adapter D0A* --> D0U state */
 157         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 158
 159         spin_unlock_irqrestore(&priv->lock, flags);
 160 }
 161
 162
 163 static int iwl5000_apm_reset(struct iwl_priv *priv)
 164 {
 165         int ret = 0;
 166         unsigned long flags;
 167
 168         iwl5000_apm_stop_master(priv);
 169
 170         spin_lock_irqsave(&priv->lock, flags);
 171
 172         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 173
 174         udelay(10);
 175
 176
 177         /* FIXME: put here L1A -L0S w/a */
 178
 179         iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 180
 181         /* set "initialization complete" bit to move adapter
 182          * D0U* --> D0A* state */
 183         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 184
 185         /* wait for clock stabilization */
 186         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 187                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 188         if (ret < 0) {
 189                 IWL_DEBUG_INFO("Failed to init the card\n");
 190                 goto out;
 191         }
 192
 193         ret = iwl_grab_nic_access(priv);
 194         if (ret)
 195                 goto out;
 196
 197         /* enable DMA */
 198         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 199
 200         udelay(20);
 201
 202         /* disable L1-Active */
 203         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 204                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 205
 206         iwl_release_nic_access(priv);
 207
 208 out:
 209         spin_unlock_irqrestore(&priv->lock, flags);
 210
 211         return ret;
 212 }
 213
 214
 215 static void iwl5000_nic_config(struct iwl_priv *priv)
 216 {
 217         unsigned long flags;
 218         u16 radio_cfg;
 219         u16 link;
 220
 221         spin_lock_irqsave(&priv->lock, flags);
 222
 223         pci_read_config_word(priv->pci_dev, PCI_CFG_LINK_CTRL, &link);
 224
 225         /* L1 is enabled by BIOS */
 226         if ((link & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
 227                 /* disable L0S disabled L1A enabled */
 228                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 229         else
 230                 /* L0S enabled L1A disabled */
 231                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 232
 233         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 234
 235         /* write radio config values to register */
 236         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 237                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 238                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 239                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 240                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 241
 242         /* set CSR_HW_CONFIG_REG for uCode use */
 243         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 244                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 245                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 246
 247         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 248          * (PCIe power is lost before PERST# is asserted),
 249          * causing ME FW to lose ownership and not being able to obtain it back.
 250          */
 251         iwl_grab_nic_access(priv);
 252         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 253                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 254                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 255         iwl_release_nic_access(priv);
 256
 257         spin_unlock_irqrestore(&priv->lock, flags);
 258 }
 259
 260
 261
 262 /*
 263  * EEPROM
 264  */
 265 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 266 {
 267         u16 offset = 0;
 268
 269         if ((address & INDIRECT_ADDRESS) == 0)
 270                 return address;
 271
 272         switch (address & INDIRECT_TYPE_MSK) {
 273         case INDIRECT_HOST:
 274                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 275                 break;
 276         case INDIRECT_GENERAL:
 277                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 278                 break;
 279         case INDIRECT_REGULATORY:
 280                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 281                 break;
 282         case INDIRECT_CALIBRATION:
 283                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 284                 break;
 285         case INDIRECT_PROCESS_ADJST:
 286                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 287                 break;
 288         case INDIRECT_OTHERS:
 289                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 290                 break;
 291         default:
 292                 IWL_ERROR("illegal indirect type: 0x%X\n",
 293                 address & INDIRECT_TYPE_MSK);
 294                 break;
 295         }
 296
 297         /* translate the offset from words to byte */
 298         return (address & ADDRESS_MSK) + (offset << 1);
 299 }
 300
 301 static u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 302 {
 303         struct iwl_eeprom_calib_hdr {
 304                 u8 version;
 305                 u8 pa_type;
 306                 u16 voltage;
 307         } *hdr;
 308
 309         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 310                                                         EEPROM_5000_CALIB_ALL);
 311         return hdr->version;
 312
 313 }
 314
 315 static void iwl5000_gain_computation(struct iwl_priv *priv,
 316                 u32 average_noise[NUM_RX_CHAINS],
 317                 u16 min_average_noise_antenna_i,
 318                 u32 min_average_noise)
 319 {
 320         int i;
 321         s32 delta_g;
 322         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 323
 324         /* Find Gain Code for the antennas B and C */
 325         for (i = 1; i < NUM_RX_CHAINS; i++) {
 326                 if ((data->disconn_array[i])) {
 327                         data->delta_gain_code[i] = 0;
 328                         continue;
 329                 }
 330                 delta_g = (1000 * ((s32)average_noise[0] -
 331                         (s32)average_noise[i])) / 1500;
 332                 /* bound gain by 2 bits value max, 3rd bit is sign */
 333                 data->delta_gain_code[i] =
 334                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 335
 336                 if (delta_g < 0)
 337                         /* set negative sign */
 338                         data->delta_gain_code[i] |= (1 << 2);
 339         }
 340
 341         IWL_DEBUG_CALIB("Delta gains: ANT_B = %d  ANT_C = %d\n",
 342                         data->delta_gain_code[1], data->delta_gain_code[2]);
 343
 344         if (!data->radio_write) {
 345                 struct iwl_calib_chain_noise_gain_cmd cmd;
 346
 347                 memset(&cmd, 0, sizeof(cmd));
 348
 349                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 350                 cmd.hdr.first_group = 0;
 351                 cmd.hdr.groups_num = 1;
 352                 cmd.hdr.data_valid = 1;
 353                 cmd.delta_gain_1 = data->delta_gain_code[1];
 354                 cmd.delta_gain_2 = data->delta_gain_code[2];
 355                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 356                         sizeof(cmd), &cmd, NULL);
 357
 358                 data->radio_write = 1;
 359                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 360         }
 361
 362         data->chain_noise_a = 0;
 363         data->chain_noise_b = 0;
 364         data->chain_noise_c = 0;
 365         data->chain_signal_a = 0;
 366         data->chain_signal_b = 0;
 367         data->chain_signal_c = 0;
 368         data->beacon_count = 0;
 369 }
 370
 371 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 372 {
 373         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 374         int ret;
 375
 376         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 377                 struct iwl_calib_chain_noise_reset_cmd cmd;
 378                 memset(&cmd, 0, sizeof(cmd));
 379
 380                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 381                 cmd.hdr.first_group = 0;
 382                 cmd.hdr.groups_num = 1;
 383                 cmd.hdr.data_valid = 1;
 384                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 385                                         sizeof(cmd), &cmd);
 386                 if (ret)
 387                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
 388                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 389                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
 390         }
 391 }
 392
 393 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 394                         __le32 *tx_flags)
 395 {
 396         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 397             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 398                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 399         else
 400                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 401 }
 402
 403 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 404         .min_nrg_cck = 95,
 405         .max_nrg_cck = 0,
 406         .auto_corr_min_ofdm = 90,
 407         .auto_corr_min_ofdm_mrc = 170,
 408         .auto_corr_min_ofdm_x1 = 120,
 409         .auto_corr_min_ofdm_mrc_x1 = 240,
 410
 411         .auto_corr_max_ofdm = 120,
 412         .auto_corr_max_ofdm_mrc = 210,
 413         .auto_corr_max_ofdm_x1 = 155,
 414         .auto_corr_max_ofdm_mrc_x1 = 290,
 415
 416         .auto_corr_min_cck = 125,
 417         .auto_corr_max_cck = 200,
 418         .auto_corr_min_cck_mrc = 170,
 419         .auto_corr_max_cck_mrc = 400,
 420         .nrg_th_cck = 95,
 421         .nrg_th_ofdm = 95,
 422 };
 423
 424 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 425                                            size_t offset)
 426 {
 427         u32 address = eeprom_indirect_address(priv, offset);
 428         BUG_ON(address >= priv->cfg->eeprom_size);
 429         return &priv->eeprom[address];
 430 }
 431
 432 static s32 iwl5150_get_ct_threshold(struct iwl_priv *priv)
 433 {
 434         const s32 volt2temp_coef = -5;
 435         u16 *temp_calib = (u16 *)iwl_eeprom_query_addr(priv,
 436                                                 EEPROM_5000_TEMPERATURE);
 437         /* offset =  temperate -  voltage / coef */
 438         s32 offset = temp_calib[0] - temp_calib[1] / volt2temp_coef;
 439         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD) - offset;
 440         return threshold * volt2temp_coef;
 441 }
 442
 443 /*
 444  *  Calibration
 445  */
 446 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 447 {
 448         struct iwl_calib_xtal_freq_cmd cmd;
 449         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 450
 451         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 452         cmd.hdr.first_group = 0;
 453         cmd.hdr.groups_num = 1;
 454         cmd.hdr.data_valid = 1;
 455         cmd.cap_pin1 = (u8)xtal_calib[0];
 456         cmd.cap_pin2 = (u8)xtal_calib[1];
 457         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 458                              (u8 *)&cmd, sizeof(cmd));
 459 }
 460
 461 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 462 {
 463         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 464         struct iwl_host_cmd cmd = {
 465                 .id = CALIBRATION_CFG_CMD,
 466                 .len = sizeof(struct iwl_calib_cfg_cmd),
 467                 .data = &calib_cfg_cmd,
 468         };
 469
 470         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 471         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 472         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 473         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 474         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 475
 476         return iwl_send_cmd(priv, &cmd);
 477 }
 478
 479 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 480                              struct iwl_rx_mem_buffer *rxb)
 481 {
 482         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 483         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 484         int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
 485         int index;
 486
 487         /* reduce the size of the length field itself */
 488         len -= 4;
 489
 490         /* Define the order in which the results will be sent to the runtime
 491          * uCode. iwl_send_calib_results sends them in a row according to their
 492          * index. We sort them here */
 493         switch (hdr->op_code) {
 494         case IWL_PHY_CALIBRATE_DC_CMD:
 495                 index = IWL_CALIB_DC;
 496                 break;
 497         case IWL_PHY_CALIBRATE_LO_CMD:
 498                 index = IWL_CALIB_LO;
 499                 break;
 500         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 501                 index = IWL_CALIB_TX_IQ;
 502                 break;
 503         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 504                 index = IWL_CALIB_TX_IQ_PERD;
 505                 break;
 506         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 507                 index = IWL_CALIB_BASE_BAND;
 508                 break;
 509         default:
 510                 IWL_ERROR("Unknown calibration notification %d\n",
 511                           hdr->op_code);
 512                 return;
 513         }
 514         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 515 }
 516
 517 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 518                                struct iwl_rx_mem_buffer *rxb)
 519 {
 520         IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
 521         queue_work(priv->workqueue, &priv->restart);
 522 }
 523
 524 /*
 525  * ucode
 526  */
 527 static int iwl5000_load_section(struct iwl_priv *priv,
 528                                 struct fw_desc *image,
 529                                 u32 dst_addr)
 530 {
 531         int ret = 0;
 532         unsigned long flags;
 533
 534         dma_addr_t phy_addr = image->p_addr;
 535         u32 byte_cnt = image->len;
 536
 537         spin_lock_irqsave(&priv->lock, flags);
 538         ret = iwl_grab_nic_access(priv);
 539         if (ret) {
 540                 spin_unlock_irqrestore(&priv->lock, flags);
 541                 return ret;
 542         }
 543
 544         iwl_write_direct32(priv,
 545                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 546                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 547
 548         iwl_write_direct32(priv,
 549                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 550
 551         iwl_write_direct32(priv,
 552                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 553                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 554
 555         iwl_write_direct32(priv,
 556                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 557                 (iwl_get_dma_hi_addr(phy_addr)
 558                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 559
 560         iwl_write_direct32(priv,
 561                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 562                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 563                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 564                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 565
 566         iwl_write_direct32(priv,
 567                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 568                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 569                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 570                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 571
 572         iwl_release_nic_access(priv);
 573         spin_unlock_irqrestore(&priv->lock, flags);
 574         return 0;
 575 }
 576
 577 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 578                 struct fw_desc *inst_image,
 579                 struct fw_desc *data_image)
 580 {
 581         int ret = 0;
 582
 583         ret = iwl5000_load_section(priv, inst_image,
 584                                    IWL50_RTC_INST_LOWER_BOUND);
 585         if (ret)
 586                 return ret;
 587
 588         IWL_DEBUG_INFO("INST uCode section being loaded...\n");
 589         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 590                                         priv->ucode_write_complete, 5 * HZ);
 591         if (ret == -ERESTARTSYS) {
 592                 IWL_ERROR("Could not load the INST uCode section due "
 593                         "to interrupt\n");
 594                 return ret;
 595         }
 596         if (!ret) {
 597                 IWL_ERROR("Could not load the INST uCode section\n");
 598                 return -ETIMEDOUT;
 599         }
 600
 601         priv->ucode_write_complete = 0;
 602
 603         ret = iwl5000_load_section(
 604                 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
 605         if (ret)
 606                 return ret;
 607
 608         IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
 609
 610         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 611                                 priv->ucode_write_complete, 5 * HZ);
 612         if (ret == -ERESTARTSYS) {
 613                 IWL_ERROR("Could not load the INST uCode section due "
 614                         "to interrupt\n");
 615                 return ret;
 616         } else if (!ret) {
 617                 IWL_ERROR("Could not load the DATA uCode section\n");
 618                 return -ETIMEDOUT;
 619         } else
 620                 ret = 0;
 621
 622         priv->ucode_write_complete = 0;
 623
 624         return ret;
 625 }
 626
 627 static int iwl5000_load_ucode(struct iwl_priv *priv)
 628 {
 629         int ret = 0;
 630
 631         /* check whether init ucode should be loaded, or rather runtime ucode */
 632         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 633                 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
 634                 ret = iwl5000_load_given_ucode(priv,
 635                         &priv->ucode_init, &priv->ucode_init_data);
 636                 if (!ret) {
 637                         IWL_DEBUG_INFO("Init ucode load complete.\n");
 638                         priv->ucode_type = UCODE_INIT;
 639                 }
 640         } else {
 641                 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
 642                         "Loading runtime ucode...\n");
 643                 ret = iwl5000_load_given_ucode(priv,
 644                         &priv->ucode_code, &priv->ucode_data);
 645                 if (!ret) {
 646                         IWL_DEBUG_INFO("Runtime ucode load complete.\n");
 647                         priv->ucode_type = UCODE_RT;
 648                 }
 649         }
 650
 651         return ret;
 652 }
 653
 654 static void iwl5000_init_alive_start(struct iwl_priv *priv)
 655 {
 656         int ret = 0;
 657
 658         /* Check alive response for "valid" sign from uCode */
 659         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 660                 /* We had an error bringing up the hardware, so take it
 661                  * all the way back down so we can try again */
 662                 IWL_DEBUG_INFO("Initialize Alive failed.\n");
 663                 goto restart;
 664         }
 665
 666         /* initialize uCode was loaded... verify inst image.
 667          * This is a paranoid check, because we would not have gotten the
 668          * "initialize" alive if code weren't properly loaded.  */
 669         if (iwl_verify_ucode(priv)) {
 670                 /* Runtime instruction load was bad;
 671                  * take it all the way back down so we can try again */
 672                 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
 673                 goto restart;
 674         }
 675
 676         iwl_clear_stations_table(priv);
 677         ret = priv->cfg->ops->lib->alive_notify(priv);
 678         if (ret) {
 679                 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
 680                 goto restart;
 681         }
 682
 683         iwl5000_send_calib_cfg(priv);
 684         return;
 685
 686 restart:
 687         /* real restart (first load init_ucode) */
 688         queue_work(priv->workqueue, &priv->restart);
 689 }
 690
 691 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 692                                 int txq_id, u32 index)
 693 {
 694         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 695                         (index & 0xff) | (txq_id << 8));
 696         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 697 }
 698
 699 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 700                                         struct iwl_tx_queue *txq,
 701                                         int tx_fifo_id, int scd_retry)
 702 {
 703         int txq_id = txq->q.id;
 704         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 705
 706         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 707                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 708                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 709                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 710                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 711
 712         txq->sched_retry = scd_retry;
 713
 714         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
 715                        active ? "Activate" : "Deactivate",
 716                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 717 }
 718
 719 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 720 {
 721         struct iwl_wimax_coex_cmd coex_cmd;
 722
 723         memset(&coex_cmd, 0, sizeof(coex_cmd));
 724
 725         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 726                                 sizeof(coex_cmd), &coex_cmd);
 727 }
 728
 729 static int iwl5000_alive_notify(struct iwl_priv *priv)
 730 {
 731         u32 a;
 732         unsigned long flags;
 733         int ret;
 734         int i, chan;
 735         u32 reg_val;
 736
 737         spin_lock_irqsave(&priv->lock, flags);
 738
 739         ret = iwl_grab_nic_access(priv);
 740         if (ret) {
 741                 spin_unlock_irqrestore(&priv->lock, flags);
 742                 return ret;
 743         }
 744
 745         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 746         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 747         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 748                 a += 4)
 749                 iwl_write_targ_mem(priv, a, 0);
 750         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 751                 a += 4)
 752                 iwl_write_targ_mem(priv, a, 0);
 753         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 754                 iwl_write_targ_mem(priv, a, 0);
 755
 756         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 757                        priv->scd_bc_tbls.dma >> 10);
 758
 759         /* Enable DMA channel */
 760         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 761                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 762                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 763                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 764
 765         /* Update FH chicken bits */
 766         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 767         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 768                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 769
 770         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 771                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 772         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 773
 774         /* initiate the queues */
 775         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 776                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 777                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 778                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 779                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 780                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 781                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 782                                 sizeof(u32),
 783                                 ((SCD_WIN_SIZE <<
 784                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 785                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 786                                 ((SCD_FRAME_LIMIT <<
 787                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 788                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 789         }
 790
 791         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 792                         IWL_MASK(0, priv->hw_params.max_txq_num));
 793
 794         /* Activate all Tx DMA/FIFO channels */
 795         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 796
 797         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 798
 799         /* map qos queues to fifos one-to-one */
 800         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 801                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 802                 iwl_txq_ctx_activate(priv, i);
 803                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 804         }
 805         /* TODO - need to initialize those FIFOs inside the loop above,
 806          * not only mark them as active */
 807         iwl_txq_ctx_activate(priv, 4);
 808         iwl_txq_ctx_activate(priv, 7);
 809         iwl_txq_ctx_activate(priv, 8);
 810         iwl_txq_ctx_activate(priv, 9);
 811
 812         iwl_release_nic_access(priv);
 813         spin_unlock_irqrestore(&priv->lock, flags);
 814
 815
 816         iwl5000_send_wimax_coex(priv);
 817
 818         iwl5000_set_Xtal_calib(priv);
 819         iwl_send_calib_results(priv);
 820
 821         return 0;
 822 }
 823
 824 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 825 {
 826         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 827             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 828                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
 829                           IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 830                 return -EINVAL;
 831         }
 832
 833         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 834         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 835         priv->hw_params.scd_bc_tbls_size =
 836                         IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
 837         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 838         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 839         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 840         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 841         priv->hw_params.max_bsm_size = 0;
 842         priv->hw_params.fat_channel =  BIT(IEEE80211_BAND_2GHZ) |
 843                                         BIT(IEEE80211_BAND_5GHZ);
 844         priv->hw_params.sens = &iwl5000_sensitivity;
 845
 846         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 847         case CSR_HW_REV_TYPE_5100:
 848                 priv->hw_params.tx_chains_num = 1;
 849                 priv->hw_params.rx_chains_num = 2;
 850                 priv->hw_params.valid_tx_ant = ANT_B;
 851                 priv->hw_params.valid_rx_ant = ANT_AB;
 852                 break;
 853         case CSR_HW_REV_TYPE_5150:
 854                 priv->hw_params.tx_chains_num = 1;
 855                 priv->hw_params.rx_chains_num = 2;
 856                 priv->hw_params.valid_tx_ant = ANT_A;
 857                 priv->hw_params.valid_rx_ant = ANT_AB;
 858                 break;
 859         case CSR_HW_REV_TYPE_5300:
 860         case CSR_HW_REV_TYPE_5350:
 861                 priv->hw_params.tx_chains_num = 3;
 862                 priv->hw_params.rx_chains_num = 3;
 863                 priv->hw_params.valid_tx_ant = ANT_ABC;
 864                 priv->hw_params.valid_rx_ant = ANT_ABC;
 865                 break;
 866         }
 867
 868         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 869         case CSR_HW_REV_TYPE_5100:
 870         case CSR_HW_REV_TYPE_5300:
 871         case CSR_HW_REV_TYPE_5350:
 872                 /* 5X00 and 5350 wants in Celsius */
 873                 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
 874                 break;
 875         case CSR_HW_REV_TYPE_5150:
 876                 /* 5150 wants in Kelvin */
 877                 priv->hw_params.ct_kill_threshold =
 878                                 iwl5150_get_ct_threshold(priv);
 879                 break;
 880         }
 881
 882         /* Set initial calibration set */
 883         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 884         case CSR_HW_REV_TYPE_5100:
 885         case CSR_HW_REV_TYPE_5300:
 886         case CSR_HW_REV_TYPE_5350:
 887                 priv->hw_params.calib_init_cfg =
 888                         BIT(IWL_CALIB_XTAL)             |
 889                         BIT(IWL_CALIB_LO)               |
 890                         BIT(IWL_CALIB_TX_IQ)            |
 891                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 892                         BIT(IWL_CALIB_BASE_BAND);
 893                 break;
 894         case CSR_HW_REV_TYPE_5150:
 895                 priv->hw_params.calib_init_cfg =
 896                         BIT(IWL_CALIB_DC)               |
 897                         BIT(IWL_CALIB_LO)               |
 898                         BIT(IWL_CALIB_TX_IQ)            |
 899                         BIT(IWL_CALIB_BASE_BAND);
 900
 901                 break;
 902         }
 903
 904
 905         return 0;
 906 }
 907
 908 /**
 909  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 910  */
 911 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 912                                             struct iwl_tx_queue *txq,
 913                                             u16 byte_cnt)
 914 {
 915         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 916         int write_ptr = txq->q.write_ptr;
 917         int txq_id = txq->q.id;
 918         u8 sec_ctl = 0;
 919         u8 sta_id = 0;
 920         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 921         __le16 bc_ent;
 922
 923         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 924
 925         if (txq_id != IWL_CMD_QUEUE_NUM) {
 926                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 927                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 928
 929                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 930                 case TX_CMD_SEC_CCM:
 931                         len += CCMP_MIC_LEN;
 932                         break;
 933                 case TX_CMD_SEC_TKIP:
 934                         len += TKIP_ICV_LEN;
 935                         break;
 936                 case TX_CMD_SEC_WEP:
 937                         len += WEP_IV_LEN + WEP_ICV_LEN;
 938                         break;
 939                 }
 940         }
 941
 942         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 943
 944         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 945
 946         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 947                 scd_bc_tbl[txq_id].
 948                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 949 }
 950
 951 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 952                                            struct iwl_tx_queue *txq)
 953 {
 954         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 955         int txq_id = txq->q.id;
 956         int read_ptr = txq->q.read_ptr;
 957         u8 sta_id = 0;
 958         __le16 bc_ent;
 959
 960         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 961
 962         if (txq_id != IWL_CMD_QUEUE_NUM)
 963                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 964
 965         bc_ent =  cpu_to_le16(1 | (sta_id << 12));
 966         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 967
 968         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 969                 scd_bc_tbl[txq_id].
 970                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
 971 }
 972
 973 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 974                                         u16 txq_id)
 975 {
 976         u32 tbl_dw_addr;
 977         u32 tbl_dw;
 978         u16 scd_q2ratid;
 979
 980         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 981
 982         tbl_dw_addr = priv->scd_base_addr +
 983                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 984
 985         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 986
 987         if (txq_id & 0x1)
 988                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 989         else
 990                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 991
 992         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 993
 994         return 0;
 995 }
 996 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 997 {
 998         /* Simply stop the queue, but don't change any configuration;
 999          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1000         iwl_write_prph(priv,
1001                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
1002                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1003                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1004 }
1005
1006 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1007                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1008 {
1009         unsigned long flags;
1010         int ret;
1011         u16 ra_tid;
1012
1013         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1014             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1015                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1016                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1017                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1018                 return -EINVAL;
1019         }
1020
1021         ra_tid = BUILD_RAxTID(sta_id, tid);
1022
1023         /* Modify device's station table to Tx this TID */
1024         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1025
1026         spin_lock_irqsave(&priv->lock, flags);
1027         ret = iwl_grab_nic_access(priv);
1028         if (ret) {
1029                 spin_unlock_irqrestore(&priv->lock, flags);
1030                 return ret;
1031         }
1032
1033         /* Stop this Tx queue before configuring it */
1034         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1035
1036         /* Map receiver-address / traffic-ID to this queue */
1037         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1038
1039         /* Set this queue as a chain-building queue */
1040         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1041
1042         /* enable aggregations for the queue */
1043         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1044
1045         /* Place first TFD at index corresponding to start sequence number.
1046          * Assumes that ssn_idx is valid (!= 0xFFF) */
1047         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1048         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1049         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1050
1051         /* Set up Tx window size and frame limit for this queue */
1052         iwl_write_targ_mem(priv, priv->scd_base_addr +
1053                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1054                         sizeof(u32),
1055                         ((SCD_WIN_SIZE <<
1056                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1057                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1058                         ((SCD_FRAME_LIMIT <<
1059                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1060                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1061
1062         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1063
1064         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1065         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1066
1067         iwl_release_nic_access(priv);
1068         spin_unlock_irqrestore(&priv->lock, flags);
1069
1070         return 0;
1071 }
1072
1073 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1074                                    u16 ssn_idx, u8 tx_fifo)
1075 {
1076         int ret;
1077
1078         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1079             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1080                 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1081                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1082                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1083                 return -EINVAL;
1084         }
1085
1086         ret = iwl_grab_nic_access(priv);
1087         if (ret)
1088                 return ret;
1089
1090         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1091
1092         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1093
1094         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1095         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1096         /* supposes that ssn_idx is valid (!= 0xFFF) */
1097         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1098
1099         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1100         iwl_txq_ctx_deactivate(priv, txq_id);
1101         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1102
1103         iwl_release_nic_access(priv);
1104
1105         return 0;
1106 }
1107
1108 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1109 {
1110         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1111         memcpy(data, cmd, size);
1112         return size;
1113 }
1114
1115
1116 /*
1117  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1118  * must be called under priv->lock and mac access
1119  */
1120 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1121 {
1122         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1123 }
1124
1125
1126 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1127 {
1128         return le32_to_cpup((__le32 *)&tx_resp->status +
1129                             tx_resp->frame_count) & MAX_SN;
1130 }
1131
1132 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1133                                       struct iwl_ht_agg *agg,
1134                                       struct iwl5000_tx_resp *tx_resp,
1135                                       int txq_id, u16 start_idx)
1136 {
1137         u16 status;
1138         struct agg_tx_status *frame_status = &tx_resp->status;
1139         struct ieee80211_tx_info *info = NULL;
1140         struct ieee80211_hdr *hdr = NULL;
1141         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1142         int i, sh, idx;
1143         u16 seq;
1144
1145         if (agg->wait_for_ba)
1146                 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1147
1148         agg->frame_count = tx_resp->frame_count;
1149         agg->start_idx = start_idx;
1150         agg->rate_n_flags = rate_n_flags;
1151         agg->bitmap = 0;
1152
1153         /* # frames attempted by Tx command */
1154         if (agg->frame_count == 1) {
1155                 /* Only one frame was attempted; no block-ack will arrive */
1156                 status = le16_to_cpu(frame_status[0].status);
1157                 idx = start_idx;
1158
1159                 /* FIXME: code repetition */
1160                 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1161                                    agg->frame_count, agg->start_idx, idx);
1162
1163                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1164                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1165                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1166                 info->flags |= iwl_is_tx_success(status) ?
1167                                         IEEE80211_TX_STAT_ACK : 0;
1168                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1169
1170                 /* FIXME: code repetition end */
1171
1172                 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1173                                     status & 0xff, tx_resp->failure_frame);
1174                 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1175
1176                 agg->wait_for_ba = 0;
1177         } else {
1178                 /* Two or more frames were attempted; expect block-ack */
1179                 u64 bitmap = 0;
1180                 int start = agg->start_idx;
1181
1182                 /* Construct bit-map of pending frames within Tx window */
1183                 for (i = 0; i < agg->frame_count; i++) {
1184                         u16 sc;
1185                         status = le16_to_cpu(frame_status[i].status);
1186                         seq  = le16_to_cpu(frame_status[i].sequence);
1187                         idx = SEQ_TO_INDEX(seq);
1188                         txq_id = SEQ_TO_QUEUE(seq);
1189
1190                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1191                                       AGG_TX_STATE_ABORT_MSK))
1192                                 continue;
1193
1194                         IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1195                                            agg->frame_count, txq_id, idx);
1196
1197                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1198
1199                         sc = le16_to_cpu(hdr->seq_ctrl);
1200                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1201                                 IWL_ERROR("BUG_ON idx doesn't match seq control"
1202                                           " idx=%d, seq_idx=%d, seq=%d\n",
1203                                           idx, SEQ_TO_SN(sc),
1204                                           hdr->seq_ctrl);
1205                                 return -1;
1206                         }
1207
1208                         IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1209                                            i, idx, SEQ_TO_SN(sc));
1210
1211                         sh = idx - start;
1212                         if (sh > 64) {
1213                                 sh = (start - idx) + 0xff;
1214                                 bitmap = bitmap << sh;
1215                                 sh = 0;
1216                                 start = idx;
1217                         } else if (sh < -64)
1218                                 sh  = 0xff - (start - idx);
1219                         else if (sh < 0) {
1220                                 sh = start - idx;
1221                                 start = idx;
1222                                 bitmap = bitmap << sh;
1223                                 sh = 0;
1224                         }
1225                         bitmap |= 1ULL << sh;
1226                         IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1227                                            start, (unsigned long long)bitmap);
1228                 }
1229
1230                 agg->bitmap = bitmap;
1231                 agg->start_idx = start;
1232                 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1233                                    agg->frame_count, agg->start_idx,
1234                                    (unsigned long long)agg->bitmap);
1235
1236                 if (bitmap)
1237                         agg->wait_for_ba = 1;
1238         }
1239         return 0;
1240 }
1241
1242 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1243                                 struct iwl_rx_mem_buffer *rxb)
1244 {
1245         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1246         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1247         int txq_id = SEQ_TO_QUEUE(sequence);
1248         int index = SEQ_TO_INDEX(sequence);
1249         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1250         struct ieee80211_tx_info *info;
1251         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1252         u32  status = le16_to_cpu(tx_resp->status.status);
1253         int tid;
1254         int sta_id;
1255         int freed;
1256
1257         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1258                 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1259                           "is out of range [0-%d] %d %d\n", txq_id,
1260                           index, txq->q.n_bd, txq->q.write_ptr,
1261                           txq->q.read_ptr);
1262                 return;
1263         }
1264
1265         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1266         memset(&info->status, 0, sizeof(info->status));
1267
1268         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1269         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1270
1271         if (txq->sched_retry) {
1272                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1273                 struct iwl_ht_agg *agg = NULL;
1274
1275                 agg = &priv->stations[sta_id].tid[tid].agg;
1276
1277                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1278
1279                 /* check if BAR is needed */
1280                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1281                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1282
1283                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1284                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1285                         IWL_DEBUG_TX_REPLY("Retry scheduler reclaim "
1286                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1287                                         scd_ssn , index, txq_id, txq->swq_id);
1288
1289                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1290                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1291
1292                         if (priv->mac80211_registered &&
1293                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1294                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1295                                 if (agg->state == IWL_AGG_OFF)
1296                                         ieee80211_wake_queue(priv->hw, txq_id);
1297                                 else
1298                                         ieee80211_wake_queue(priv->hw,
1299                                                              txq->swq_id);
1300                         }
1301                 }
1302         } else {
1303                 BUG_ON(txq_id != txq->swq_id);
1304
1305                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1306                 info->flags |= iwl_is_tx_success(status) ?
1307                                         IEEE80211_TX_STAT_ACK : 0;
1308                 iwl_hwrate_to_tx_control(priv,
1309                                         le32_to_cpu(tx_resp->rate_n_flags),
1310                                         info);
1311
1312                 IWL_DEBUG_TX_REPLY("TXQ %d status %s (0x%08x) rate_n_flags "
1313                                    "0x%x retries %d\n",
1314                                    txq_id,
1315                                    iwl_get_tx_fail_reason(status), status,
1316                                    le32_to_cpu(tx_resp->rate_n_flags),
1317                                    tx_resp->failure_frame);
1318
1319                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1320                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1321                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1322
1323                 if (priv->mac80211_registered &&
1324                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1325                         ieee80211_wake_queue(priv->hw, txq_id);
1326         }
1327
1328         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1329                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1330
1331         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1332                 IWL_ERROR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
1333 }
1334
1335 /* Currently 5000 is the superset of everything */
1336 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1337 {
1338         return len;
1339 }
1340
1341 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1342 {
1343         /* in 5000 the tx power calibration is done in uCode */
1344         priv->disable_tx_power_cal = 1;
1345 }
1346
1347 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1348 {
1349         /* init calibration handlers */
1350         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1351                                         iwl5000_rx_calib_result;
1352         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1353                                         iwl5000_rx_calib_complete;
1354         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1355 }
1356
1357
1358 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1359 {
1360         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1361                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1362 }
1363
1364 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1365 {
1366         int ret = 0;
1367         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1368         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1369         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1370
1371         if ((rxon1->flags == rxon2->flags) &&
1372             (rxon1->filter_flags == rxon2->filter_flags) &&
1373             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1374             (rxon1->ofdm_ht_single_stream_basic_rates ==
1375              rxon2->ofdm_ht_single_stream_basic_rates) &&
1376             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1377              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1378             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1379              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1380             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1381             (rxon1->rx_chain == rxon2->rx_chain) &&
1382             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1383                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
1384                 return 0;
1385         }
1386
1387         rxon_assoc.flags = priv->staging_rxon.flags;
1388         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1389         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1390         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1391         rxon_assoc.reserved1 = 0;
1392         rxon_assoc.reserved2 = 0;
1393         rxon_assoc.reserved3 = 0;
1394         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1395             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1396         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1397             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1398         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1399         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1400                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1401         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1402
1403         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1404                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1405         if (ret)
1406                 return ret;
1407
1408         return ret;
1409 }
1410 static int  iwl5000_send_tx_power(struct iwl_priv *priv)
1411 {
1412         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1413
1414         /* half dBm need to multiply */
1415         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1416         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1417         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1418         return  iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1419                                        sizeof(tx_power_cmd), &tx_power_cmd,
1420                                        NULL);
1421 }
1422
1423 static void iwl5000_temperature(struct iwl_priv *priv)
1424 {
1425         /* store temperature from statistics (in Celsius) */
1426         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1427 }
1428
1429 /* Calc max signal level (dBm) among 3 possible receivers */
1430 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1431                              struct iwl_rx_phy_res *rx_resp)
1432 {
1433         /* data from PHY/DSP regarding signal strength, etc.,
1434          *   contents are always there, not configurable by host
1435          */
1436         struct iwl5000_non_cfg_phy *ncphy =
1437                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1438         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1439         u8 agc;
1440
1441         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1442         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1443
1444         /* Find max rssi among 3 possible receivers.
1445          * These values are measured by the digital signal processor (DSP).
1446          * They should stay fairly constant even as the signal strength varies,
1447          *   if the radio's automatic gain control (AGC) is working right.
1448          * AGC value (see below) will provide the "interesting" info.
1449          */
1450         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1451         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1452         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1453         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1454         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1455
1456         max_rssi = max_t(u32, rssi_a, rssi_b);
1457         max_rssi = max_t(u32, max_rssi, rssi_c);
1458
1459         IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1460                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1461
1462         /* dBm = max_rssi dB - agc dB - constant.
1463          * Higher AGC (higher radio gain) means lower signal. */
1464         return max_rssi - agc - IWL49_RSSI_OFFSET;
1465 }
1466
1467 static struct iwl_hcmd_ops iwl5000_hcmd = {
1468         .rxon_assoc = iwl5000_send_rxon_assoc,
1469 };
1470
1471 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1472         .get_hcmd_size = iwl5000_get_hcmd_size,
1473         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1474         .gain_computation = iwl5000_gain_computation,
1475         .chain_noise_reset = iwl5000_chain_noise_reset,
1476         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1477         .calc_rssi = iwl5000_calc_rssi,
1478 };
1479
1480 static struct iwl_lib_ops iwl5000_lib = {
1481         .set_hw_params = iwl5000_hw_set_hw_params,
1482         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1483         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1484         .txq_set_sched = iwl5000_txq_set_sched,
1485         .txq_agg_enable = iwl5000_txq_agg_enable,
1486         .txq_agg_disable = iwl5000_txq_agg_disable,
1487         .rx_handler_setup = iwl5000_rx_handler_setup,
1488         .setup_deferred_work = iwl5000_setup_deferred_work,
1489         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1490         .load_ucode = iwl5000_load_ucode,
1491         .init_alive_start = iwl5000_init_alive_start,
1492         .alive_notify = iwl5000_alive_notify,
1493         .send_tx_power = iwl5000_send_tx_power,
1494         .temperature = iwl5000_temperature,
1495         .update_chain_flags = iwl_update_chain_flags,
1496         .apm_ops = {
1497                 .init = iwl5000_apm_init,
1498                 .reset = iwl5000_apm_reset,
1499                 .stop = iwl5000_apm_stop,
1500                 .config = iwl5000_nic_config,
1501                 .set_pwr_src = iwl_set_pwr_src,
1502         },
1503         .eeprom_ops = {
1504                 .regulatory_bands = {
1505                         EEPROM_5000_REG_BAND_1_CHANNELS,
1506                         EEPROM_5000_REG_BAND_2_CHANNELS,
1507                         EEPROM_5000_REG_BAND_3_CHANNELS,
1508                         EEPROM_5000_REG_BAND_4_CHANNELS,
1509                         EEPROM_5000_REG_BAND_5_CHANNELS,
1510                         EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1511                         EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1512                 },
1513                 .verify_signature  = iwlcore_eeprom_verify_signature,
1514                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1515                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1516                 .calib_version  = iwl5000_eeprom_calib_version,
1517                 .query_addr = iwl5000_eeprom_query_addr,
1518         },
1519 };
1520
1521 static struct iwl_ops iwl5000_ops = {
1522         .lib = &iwl5000_lib,
1523         .hcmd = &iwl5000_hcmd,
1524         .utils = &iwl5000_hcmd_utils,
1525 };
1526
1527 static struct iwl_mod_params iwl50_mod_params = {
1528         .num_of_queues = IWL50_NUM_QUEUES,
1529         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1530         .amsdu_size_8K = 1,
1531         .restart_fw = 1,
1532         /* the rest are 0 by default */
1533 };
1534
1535
1536 struct iwl_cfg iwl5300_agn_cfg = {
1537         .name = "5300AGN",
1538         .fw_name_pre = IWL5000_FW_PRE,
1539         .ucode_api_max = IWL5000_UCODE_API_MAX,
1540         .ucode_api_min = IWL5000_UCODE_API_MIN,
1541         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1542         .ops = &iwl5000_ops,
1543         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1544         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1545         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1546         .mod_params = &iwl50_mod_params,
1547 };
1548
1549 struct iwl_cfg iwl5100_bg_cfg = {
1550         .name = "5100BG",
1551         .fw_name_pre = IWL5000_FW_PRE,
1552         .ucode_api_max = IWL5000_UCODE_API_MAX,
1553         .ucode_api_min = IWL5000_UCODE_API_MIN,
1554         .sku = IWL_SKU_G,
1555         .ops = &iwl5000_ops,
1556         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1557         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1558         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1559         .mod_params = &iwl50_mod_params,
1560 };
1561
1562 struct iwl_cfg iwl5100_abg_cfg = {
1563         .name = "5100ABG",
1564         .fw_name_pre = IWL5000_FW_PRE,
1565         .ucode_api_max = IWL5000_UCODE_API_MAX,
1566         .ucode_api_min = IWL5000_UCODE_API_MIN,
1567         .sku = IWL_SKU_A|IWL_SKU_G,
1568         .ops = &iwl5000_ops,
1569         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1570         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1571         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1572         .mod_params = &iwl50_mod_params,
1573 };
1574
1575 struct iwl_cfg iwl5100_agn_cfg = {
1576         .name = "5100AGN",
1577         .fw_name_pre = IWL5000_FW_PRE,
1578         .ucode_api_max = IWL5000_UCODE_API_MAX,
1579         .ucode_api_min = IWL5000_UCODE_API_MIN,
1580         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1581         .ops = &iwl5000_ops,
1582         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1583         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1584         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1585         .mod_params = &iwl50_mod_params,
1586 };
1587
1588 struct iwl_cfg iwl5350_agn_cfg = {
1589         .name = "5350AGN",
1590         .fw_name_pre = IWL5000_FW_PRE,
1591         .ucode_api_max = IWL5000_UCODE_API_MAX,
1592         .ucode_api_min = IWL5000_UCODE_API_MIN,
1593         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1594         .ops = &iwl5000_ops,
1595         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1596         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1597         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1598         .mod_params = &iwl50_mod_params,
1599 };
1600
1601 struct iwl_cfg iwl5150_agn_cfg = {
1602         .name = "5150AGN",
1603         .fw_name_pre = IWL5150_FW_PRE,
1604         .ucode_api_max = IWL5150_UCODE_API_MAX,
1605         .ucode_api_min = IWL5150_UCODE_API_MIN,
1606         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1607         .ops = &iwl5000_ops,
1608         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1609         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1610         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1611         .mod_params = &iwl50_mod_params,
1612 };
1613
1614 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1615 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1616
1617 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1618 MODULE_PARM_DESC(disable50,
1619                   "manually disable the 50XX radio (default 0 [radio on])");
1620 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1621 MODULE_PARM_DESC(swcrypto50,
1622                   "using software crypto engine (default 0 [hardware])\n");
1623 module_param_named(debug50, iwl50_mod_params.debug, uint, 0444);
1624 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1625 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1626 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1627 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1628 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1629 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1630 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1631 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1632 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");