drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39 #include <net/mac80211.h>
  40
  41 #include "iwl-fh.h"
  42 #include "iwl-3945-fh.h"
  43 #include "iwl-commands.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-3945.h"
  46 #include "iwl-eeprom.h"
  47 #include "iwl-helpers.h"
  48 #include "iwl-core.h"
  49 #include "iwl-agn-rs.h"
  50
  51 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  52         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  53                                     IWL_RATE_##r##M_IEEE,   \
  54                                     IWL_RATE_##ip##M_INDEX, \
  55                                     IWL_RATE_##in##M_INDEX, \
  56                                     IWL_RATE_##rp##M_INDEX, \
  57                                     IWL_RATE_##rn##M_INDEX, \
  58                                     IWL_RATE_##pp##M_INDEX, \
  59                                     IWL_RATE_##np##M_INDEX, \
  60                                     IWL_RATE_##r##M_INDEX_TABLE, \
  61                                     IWL_RATE_##ip##M_INDEX_TABLE }
  62
  63 /*
  64  * Parameter order:
  65  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  66  *
  67  * If there isn't a valid next or previous rate then INV is used which
  68  * maps to IWL_RATE_INVALID
  69  *
  70  */
  71 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  72         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  73         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  74         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  75         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  76         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  77         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  78         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  79         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  80         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  81         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  82         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  83         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  84 };
  85
  86 /* 1 = enable the iwl3945_disable_events() function */
  87 #define IWL_EVT_DISABLE (0)
  88 #define IWL_EVT_DISABLE_SIZE (1532/32)
  89
  90 /**
  91  * iwl3945_disable_events - Disable selected events in uCode event log
  92  *
  93  * Disable an event by writing "1"s into "disable"
  94  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  95  *   Default values of 0 enable uCode events to be logged.
  96  * Use for only special debugging.  This function is just a placeholder as-is,
  97  *   you'll need to provide the special bits! ...
  98  *   ... and set IWL_EVT_DISABLE to 1. */
  99 void iwl3945_disable_events(struct iwl_priv *priv)
 100 {
 101         int i;
 102         u32 base;               /* SRAM address of event log header */
 103         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 104         u32 array_size;         /* # of u32 entries in array */
 105         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 106                 0x00000000,     /*   31 -    0  Event id numbers */
 107                 0x00000000,     /*   63 -   32 */
 108                 0x00000000,     /*   95 -   64 */
 109                 0x00000000,     /*  127 -   96 */
 110                 0x00000000,     /*  159 -  128 */
 111                 0x00000000,     /*  191 -  160 */
 112                 0x00000000,     /*  223 -  192 */
 113                 0x00000000,     /*  255 -  224 */
 114                 0x00000000,     /*  287 -  256 */
 115                 0x00000000,     /*  319 -  288 */
 116                 0x00000000,     /*  351 -  320 */
 117                 0x00000000,     /*  383 -  352 */
 118                 0x00000000,     /*  415 -  384 */
 119                 0x00000000,     /*  447 -  416 */
 120                 0x00000000,     /*  479 -  448 */
 121                 0x00000000,     /*  511 -  480 */
 122                 0x00000000,     /*  543 -  512 */
 123                 0x00000000,     /*  575 -  544 */
 124                 0x00000000,     /*  607 -  576 */
 125                 0x00000000,     /*  639 -  608 */
 126                 0x00000000,     /*  671 -  640 */
 127                 0x00000000,     /*  703 -  672 */
 128                 0x00000000,     /*  735 -  704 */
 129                 0x00000000,     /*  767 -  736 */
 130                 0x00000000,     /*  799 -  768 */
 131                 0x00000000,     /*  831 -  800 */
 132                 0x00000000,     /*  863 -  832 */
 133                 0x00000000,     /*  895 -  864 */
 134                 0x00000000,     /*  927 -  896 */
 135                 0x00000000,     /*  959 -  928 */
 136                 0x00000000,     /*  991 -  960 */
 137                 0x00000000,     /* 1023 -  992 */
 138                 0x00000000,     /* 1055 - 1024 */
 139                 0x00000000,     /* 1087 - 1056 */
 140                 0x00000000,     /* 1119 - 1088 */
 141                 0x00000000,     /* 1151 - 1120 */
 142                 0x00000000,     /* 1183 - 1152 */
 143                 0x00000000,     /* 1215 - 1184 */
 144                 0x00000000,     /* 1247 - 1216 */
 145                 0x00000000,     /* 1279 - 1248 */
 146                 0x00000000,     /* 1311 - 1280 */
 147                 0x00000000,     /* 1343 - 1312 */
 148                 0x00000000,     /* 1375 - 1344 */
 149                 0x00000000,     /* 1407 - 1376 */
 150                 0x00000000,     /* 1439 - 1408 */
 151                 0x00000000,     /* 1471 - 1440 */
 152                 0x00000000,     /* 1503 - 1472 */
 153         };
 154
 155         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 156         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 157                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 158                 return;
 159         }
 160
 161         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 162         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 163
 164         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 165                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 166                                disable_ptr);
 167                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 168                         iwl_write_targ_mem(priv,
 169                                            disable_ptr + (i * sizeof(u32)),
 170                                            evt_disable[i]);
 171
 172         } else {
 173                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 174                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 175                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 176                                disable_ptr, array_size);
 177         }
 178
 179 }
 180
 181 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 182 {
 183         int idx;
 184
 185         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
 186                 if (iwl3945_rates[idx].plcp == plcp)
 187                         return idx;
 188         return -1;
 189 }
 190
 191 #ifdef CONFIG_IWLWIFI_DEBUG
 192 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 193
 194 static const char *iwl3945_get_tx_fail_reason(u32 status)
 195 {
 196         switch (status & TX_STATUS_MSK) {
 197         case TX_STATUS_SUCCESS:
 198                 return "SUCCESS";
 199                 TX_STATUS_ENTRY(SHORT_LIMIT);
 200                 TX_STATUS_ENTRY(LONG_LIMIT);
 201                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 202                 TX_STATUS_ENTRY(MGMNT_ABORT);
 203                 TX_STATUS_ENTRY(NEXT_FRAG);
 204                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 205                 TX_STATUS_ENTRY(DEST_PS);
 206                 TX_STATUS_ENTRY(ABORTED);
 207                 TX_STATUS_ENTRY(BT_RETRY);
 208                 TX_STATUS_ENTRY(STA_INVALID);
 209                 TX_STATUS_ENTRY(FRAG_DROPPED);
 210                 TX_STATUS_ENTRY(TID_DISABLE);
 211                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 212                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 213                 TX_STATUS_ENTRY(TX_LOCKED);
 214                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 215         }
 216
 217         return "UNKNOWN";
 218 }
 219 #else
 220 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 221 {
 222         return "";
 223 }
 224 #endif
 225
 226 /*
 227  * get ieee prev rate from rate scale table.
 228  * for A and B mode we need to overright prev
 229  * value
 230  */
 231 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 232 {
 233         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 234
 235         switch (priv->band) {
 236         case IEEE80211_BAND_5GHZ:
 237                 if (rate == IWL_RATE_12M_INDEX)
 238                         next_rate = IWL_RATE_9M_INDEX;
 239                 else if (rate == IWL_RATE_6M_INDEX)
 240                         next_rate = IWL_RATE_6M_INDEX;
 241                 break;
 242         case IEEE80211_BAND_2GHZ:
 243                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 244                     iwl_is_associated(priv)) {
 245                         if (rate == IWL_RATE_11M_INDEX)
 246                                 next_rate = IWL_RATE_5M_INDEX;
 247                 }
 248                 break;
 249
 250         default:
 251                 break;
 252         }
 253
 254         return next_rate;
 255 }
 256
 257
 258 /**
 259  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 260  *
 261  * When FW advances 'R' index, all entries between old and new 'R' index
 262  * need to be reclaimed. As result, some free space forms. If there is
 263  * enough free space (> low mark), wake the stack that feeds us.
 264  */
 265 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 266                                      int txq_id, int index)
 267 {
 268         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 269         struct iwl_queue *q = &txq->q;
 270         struct iwl_tx_info *tx_info;
 271
 272         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 273
 274         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 275                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 276
 277                 tx_info = &txq->txb[txq->q.read_ptr];
 278                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 279                 tx_info->skb[0] = NULL;
 280                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 281         }
 282
 283         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 284                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 285                         priv->mac80211_registered)
 286                 iwl_wake_queue(priv, txq_id);
 287 }
 288
 289 /**
 290  * iwl3945_rx_reply_tx - Handle Tx response
 291  */
 292 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 293                             struct iwl_rx_mem_buffer *rxb)
 294 {
 295         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 296         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 297         int txq_id = SEQ_TO_QUEUE(sequence);
 298         int index = SEQ_TO_INDEX(sequence);
 299         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 300         struct ieee80211_tx_info *info;
 301         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 302         u32  status = le32_to_cpu(tx_resp->status);
 303         int rate_idx;
 304         int fail;
 305
 306         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 307                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 308                           "is out of range [0-%d] %d %d\n", txq_id,
 309                           index, txq->q.n_bd, txq->q.write_ptr,
 310                           txq->q.read_ptr);
 311                 return;
 312         }
 313
 314         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 315         ieee80211_tx_info_clear_status(info);
 316
 317         /* Fill the MRR chain with some info about on-chip retransmissions */
 318         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 319         if (info->band == IEEE80211_BAND_5GHZ)
 320                 rate_idx -= IWL_FIRST_OFDM_RATE;
 321
 322         fail = tx_resp->failure_frame;
 323
 324         info->status.rates[0].idx = rate_idx;
 325         info->status.rates[0].count = fail + 1; /* add final attempt */
 326
 327         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 328         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 329                                 IEEE80211_TX_STAT_ACK : 0;
 330
 331         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 332                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 333                         tx_resp->rate, tx_resp->failure_frame);
 334
 335         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 336         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 337
 338         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 339                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 340 }
 341
 342
 343
 344 /*****************************************************************************
 345  *
 346  * Intel PRO/Wireless 3945ABG/BG Network Connection
 347  *
 348  *  RX handler implementations
 349  *
 350  *****************************************************************************/
 351
 352 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 353                 struct iwl_rx_mem_buffer *rxb)
 354 {
 355         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 356         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 357                      (int)sizeof(struct iwl3945_notif_statistics),
 358                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 359
 360         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
 361
 362         iwl3945_led_background(priv);
 363
 364         priv->last_statistics_time = jiffies;
 365 }
 366
 367 /******************************************************************************
 368  *
 369  * Misc. internal state and helper functions
 370  *
 371  ******************************************************************************/
 372 #ifdef CONFIG_IWLWIFI_DEBUG
 373
 374 /**
 375  * iwl3945_report_frame - dump frame to syslog during debug sessions
 376  *
 377  * You may hack this function to show different aspects of received frames,
 378  * including selective frame dumps.
 379  * group100 parameter selects whether to show 1 out of 100 good frames.
 380  */
 381 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 382                       struct iwl_rx_packet *pkt,
 383                       struct ieee80211_hdr *header, int group100)
 384 {
 385         u32 to_us;
 386         u32 print_summary = 0;
 387         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 388         u32 hundred = 0;
 389         u32 dataframe = 0;
 390         __le16 fc;
 391         u16 seq_ctl;
 392         u16 channel;
 393         u16 phy_flags;
 394         u16 length;
 395         u16 status;
 396         u16 bcn_tmr;
 397         u32 tsf_low;
 398         u64 tsf;
 399         u8 rssi;
 400         u8 agc;
 401         u16 sig_avg;
 402         u16 noise_diff;
 403         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 404         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 405         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 406         u8 *data = IWL_RX_DATA(pkt);
 407
 408         /* MAC header */
 409         fc = header->frame_control;
 410         seq_ctl = le16_to_cpu(header->seq_ctrl);
 411
 412         /* metadata */
 413         channel = le16_to_cpu(rx_hdr->channel);
 414         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 415         length = le16_to_cpu(rx_hdr->len);
 416
 417         /* end-of-frame status and timestamp */
 418         status = le32_to_cpu(rx_end->status);
 419         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 420         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 421         tsf = le64_to_cpu(rx_end->timestamp);
 422
 423         /* signal statistics */
 424         rssi = rx_stats->rssi;
 425         agc = rx_stats->agc;
 426         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 427         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 428
 429         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 430
 431         /* if data frame is to us and all is good,
 432          *   (optionally) print summary for only 1 out of every 100 */
 433         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 434             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 435                 dataframe = 1;
 436                 if (!group100)
 437                         print_summary = 1;      /* print each frame */
 438                 else if (priv->framecnt_to_us < 100) {
 439                         priv->framecnt_to_us++;
 440                         print_summary = 0;
 441                 } else {
 442                         priv->framecnt_to_us = 0;
 443                         print_summary = 1;
 444                         hundred = 1;
 445                 }
 446         } else {
 447                 /* print summary for all other frames */
 448                 print_summary = 1;
 449         }
 450
 451         if (print_summary) {
 452                 char *title;
 453                 int rate;
 454
 455                 if (hundred)
 456                         title = "100Frames";
 457                 else if (ieee80211_has_retry(fc))
 458                         title = "Retry";
 459                 else if (ieee80211_is_assoc_resp(fc))
 460                         title = "AscRsp";
 461                 else if (ieee80211_is_reassoc_resp(fc))
 462                         title = "RasRsp";
 463                 else if (ieee80211_is_probe_resp(fc)) {
 464                         title = "PrbRsp";
 465                         print_dump = 1; /* dump frame contents */
 466                 } else if (ieee80211_is_beacon(fc)) {
 467                         title = "Beacon";
 468                         print_dump = 1; /* dump frame contents */
 469                 } else if (ieee80211_is_atim(fc))
 470                         title = "ATIM";
 471                 else if (ieee80211_is_auth(fc))
 472                         title = "Auth";
 473                 else if (ieee80211_is_deauth(fc))
 474                         title = "DeAuth";
 475                 else if (ieee80211_is_disassoc(fc))
 476                         title = "DisAssoc";
 477                 else
 478                         title = "Frame";
 479
 480                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 481                 if (rate == -1)
 482                         rate = 0;
 483                 else
 484                         rate = iwl3945_rates[rate].ieee / 2;
 485
 486                 /* print frame summary.
 487                  * MAC addresses show just the last byte (for brevity),
 488                  *    but you can hack it to show more, if you'd like to. */
 489                 if (dataframe)
 490                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
 491                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 492                                      title, le16_to_cpu(fc), header->addr1[5],
 493                                      length, rssi, channel, rate);
 494                 else {
 495                         /* src/dst addresses assume managed mode */
 496                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
 497                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 498                                      "phy=0x%02x, chnl=%d\n",
 499                                      title, le16_to_cpu(fc), header->addr1[5],
 500                                      header->addr3[5], rssi,
 501                                      tsf_low - priv->scan_start_tsf,
 502                                      phy_flags, channel);
 503                 }
 504         }
 505         if (print_dump)
 506                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 507 }
 508
 509 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 510                       struct iwl_rx_packet *pkt,
 511                       struct ieee80211_hdr *header, int group100)
 512 {
 513         if (iwl_get_debug_level(priv) & IWL_DL_RX)
 514                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 515 }
 516
 517 #else
 518 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 519                       struct iwl_rx_packet *pkt,
 520                       struct ieee80211_hdr *header, int group100)
 521 {
 522 }
 523 #endif
 524
 525 /* This is necessary only for a number of statistics, see the caller. */
 526 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 527                 struct ieee80211_hdr *header)
 528 {
 529         /* Filter incoming packets to determine if they are targeted toward
 530          * this network, discarding packets coming from ourselves */
 531         switch (priv->iw_mode) {
 532         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 533                 /* packets to our IBSS update information */
 534                 return !compare_ether_addr(header->addr3, priv->bssid);
 535         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 536                 /* packets to our IBSS update information */
 537                 return !compare_ether_addr(header->addr2, priv->bssid);
 538         default:
 539                 return 1;
 540         }
 541 }
 542
 543 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 544                                    struct iwl_rx_mem_buffer *rxb,
 545                                    struct ieee80211_rx_status *stats)
 546 {
 547         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
 548         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 549         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 550         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 551         short len = le16_to_cpu(rx_hdr->len);
 552
 553         /* We received data from the HW, so stop the watchdog */
 554         if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
 555                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 556                 return;
 557         }
 558
 559         /* We only process data packets if the interface is open */
 560         if (unlikely(!priv->is_open)) {
 561                 IWL_DEBUG_DROP_LIMIT(priv,
 562                         "Dropping packet while interface is not open.\n");
 563                 return;
 564         }
 565
 566         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
 567         /* Set the size of the skb to the size of the frame */
 568         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
 569
 570         if (!iwl3945_mod_params.sw_crypto)
 571                 iwl_set_decrypted_flag(priv,
 572                                        (struct ieee80211_hdr *)rxb->skb->data,
 573                                        le32_to_cpu(rx_end->status), stats);
 574
 575 #ifdef CONFIG_IWLWIFI_LEDS
 576         if (ieee80211_is_data(hdr->frame_control))
 577                 priv->rxtxpackets += len;
 578 #endif
 579         iwl_update_stats(priv, false, hdr->frame_control, len);
 580
 581         memcpy(IEEE80211_SKB_RXCB(rxb->skb), stats, sizeof(*stats));
 582         ieee80211_rx_irqsafe(priv->hw, rxb->skb);
 583         rxb->skb = NULL;
 584 }
 585
 586 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 587
 588 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 589                                 struct iwl_rx_mem_buffer *rxb)
 590 {
 591         struct ieee80211_hdr *header;
 592         struct ieee80211_rx_status rx_status;
 593         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 594         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 595         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 596         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 597         int snr;
 598         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 599         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 600         u8 network_packet;
 601
 602         rx_status.flag = 0;
 603         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 604         rx_status.freq =
 605                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 606         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 607                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 608
 609         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 610         if (rx_status.band == IEEE80211_BAND_5GHZ)
 611                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 612
 613         rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
 614                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 615
 616         /* set the preamble flag if appropriate */
 617         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 618                 rx_status.flag |= RX_FLAG_SHORTPRE;
 619
 620         if ((unlikely(rx_stats->phy_count > 20))) {
 621                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 622                                 rx_stats->phy_count);
 623                 return;
 624         }
 625
 626         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 627             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 628                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 629                 return;
 630         }
 631
 632
 633
 634         /* Convert 3945's rssi indicator to dBm */
 635         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 636
 637         /* Set default noise value to -127 */
 638         if (priv->last_rx_noise == 0)
 639                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 640
 641         /* 3945 provides noise info for OFDM frames only.
 642          * sig_avg and noise_diff are measured by the 3945's digital signal
 643          *   processor (DSP), and indicate linear levels of signal level and
 644          *   distortion/noise within the packet preamble after
 645          *   automatic gain control (AGC).  sig_avg should stay fairly
 646          *   constant if the radio's AGC is working well.
 647          * Since these values are linear (not dB or dBm), linear
 648          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 649          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 650          *   to obtain noise level in dBm.
 651          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 652         if (rx_stats_noise_diff) {
 653                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 654                 rx_status.noise = rx_status.signal -
 655                                         iwl3945_calc_db_from_ratio(snr);
 656                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
 657                                                          rx_status.noise);
 658
 659         /* If noise info not available, calculate signal quality indicator (%)
 660          *   using just the dBm signal level. */
 661         } else {
 662                 rx_status.noise = priv->last_rx_noise;
 663                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
 664         }
 665
 666
 667         IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
 668                         rx_status.signal, rx_status.noise, rx_status.qual,
 669                         rx_stats_sig_avg, rx_stats_noise_diff);
 670
 671         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 672
 673         network_packet = iwl3945_is_network_packet(priv, header);
 674
 675         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 676                               network_packet ? '*' : ' ',
 677                               le16_to_cpu(rx_hdr->channel),
 678                               rx_status.signal, rx_status.signal,
 679                               rx_status.noise, rx_status.rate_idx);
 680
 681         /* Set "1" to report good data frames in groups of 100 */
 682         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 683         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 684
 685         if (network_packet) {
 686                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
 687                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
 688                 priv->last_rx_rssi = rx_status.signal;
 689                 priv->last_rx_noise = rx_status.noise;
 690         }
 691
 692         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 693 }
 694
 695 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 696                                      struct iwl_tx_queue *txq,
 697                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 698 {
 699         int count;
 700         struct iwl_queue *q;
 701         struct iwl3945_tfd *tfd, *tfd_tmp;
 702
 703         q = &txq->q;
 704         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 705         tfd = &tfd_tmp[q->write_ptr];
 706
 707         if (reset)
 708                 memset(tfd, 0, sizeof(*tfd));
 709
 710         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 711
 712         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 713                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 714                           NUM_TFD_CHUNKS);
 715                 return -EINVAL;
 716         }
 717
 718         tfd->tbs[count].addr = cpu_to_le32(addr);
 719         tfd->tbs[count].len = cpu_to_le32(len);
 720
 721         count++;
 722
 723         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 724                                          TFD_CTL_PAD_SET(pad));
 725
 726         return 0;
 727 }
 728
 729 /**
 730  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 731  *
 732  * Does NOT advance any indexes
 733  */
 734 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 735 {
 736         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 737         int index = txq->q.read_ptr;
 738         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 739         struct pci_dev *dev = priv->pci_dev;
 740         int i;
 741         int counter;
 742
 743         /* sanity check */
 744         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 745         if (counter > NUM_TFD_CHUNKS) {
 746                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 747                 /* @todo issue fatal error, it is quite serious situation */
 748                 return;
 749         }
 750
 751         /* Unmap tx_cmd */
 752         if (counter)
 753                 pci_unmap_single(dev,
 754                                 pci_unmap_addr(&txq->meta[index], mapping),
 755                                 pci_unmap_len(&txq->meta[index], len),
 756                                 PCI_DMA_TODEVICE);
 757
 758         /* unmap chunks if any */
 759
 760         for (i = 1; i < counter; i++) {
 761                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 762                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 763                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 764                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 765                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 766                                 /* Can be called from interrupt context */
 767                                 dev_kfree_skb_any(skb);
 768                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 769                         }
 770                 }
 771         }
 772         return ;
 773 }
 774
 775 /**
 776  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 777  *
 778 */
 779 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 780                                   struct iwl_device_cmd *cmd,
 781                                   struct ieee80211_tx_info *info,
 782                                   struct ieee80211_hdr *hdr,
 783                                   int sta_id, int tx_id)
 784 {
 785         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 786         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
 787         u16 rate_mask;
 788         int rate;
 789         u8 rts_retry_limit;
 790         u8 data_retry_limit;
 791         __le32 tx_flags;
 792         __le16 fc = hdr->frame_control;
 793         struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 794
 795         rate = iwl3945_rates[rate_index].plcp;
 796         tx_flags = tx->tx_flags;
 797
 798         /* We need to figure out how to get the sta->supp_rates while
 799          * in this running context */
 800         rate_mask = IWL_RATES_MASK;
 801
 802         if (tx_id >= IWL_CMD_QUEUE_NUM)
 803                 rts_retry_limit = 3;
 804         else
 805                 rts_retry_limit = 7;
 806
 807         if (ieee80211_is_probe_resp(fc)) {
 808                 data_retry_limit = 3;
 809                 if (data_retry_limit < rts_retry_limit)
 810                         rts_retry_limit = data_retry_limit;
 811         } else
 812                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 813
 814         if (priv->data_retry_limit != -1)
 815                 data_retry_limit = priv->data_retry_limit;
 816
 817         if (ieee80211_is_mgmt(fc)) {
 818                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 819                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 820                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 821                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 822                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 823                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 824                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 825                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 826                         }
 827                         break;
 828                 default:
 829                         break;
 830                 }
 831         }
 832
 833         tx->rts_retry_limit = rts_retry_limit;
 834         tx->data_retry_limit = data_retry_limit;
 835         tx->rate = rate;
 836         tx->tx_flags = tx_flags;
 837
 838         /* OFDM */
 839         tx->supp_rates[0] =
 840            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 841
 842         /* CCK */
 843         tx->supp_rates[1] = (rate_mask & 0xF);
 844
 845         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 846                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 847                        tx->rate, le32_to_cpu(tx->tx_flags),
 848                        tx->supp_rates[1], tx->supp_rates[0]);
 849 }
 850
 851 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 852 {
 853         unsigned long flags_spin;
 854         struct iwl_station_entry *station;
 855
 856         if (sta_id == IWL_INVALID_STATION)
 857                 return IWL_INVALID_STATION;
 858
 859         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 860         station = &priv->stations[sta_id];
 861
 862         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 863         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 864         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 865
 866         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 867
 868         iwl_send_add_sta(priv, &station->sta, flags);
 869         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 870                         sta_id, tx_rate);
 871         return sta_id;
 872 }
 873
 874 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 875 {
 876         if (src == IWL_PWR_SRC_VAUX) {
 877                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 878                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 879                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 880                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 881
 882                         iwl_poll_bit(priv, CSR_GPIO_IN,
 883                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 884                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 885                 }
 886         } else {
 887                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 888                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 889                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 890
 891                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 892                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 893         }
 894
 895         return 0;
 896 }
 897
 898 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 899 {
 900         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 901         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 902         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 903         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 904                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 905                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 906                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 907                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 908                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 909                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 910                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 911                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 912
 913         /* fake read to flush all prev I/O */
 914         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 915
 916         return 0;
 917 }
 918
 919 static int iwl3945_tx_reset(struct iwl_priv *priv)
 920 {
 921
 922         /* bypass mode */
 923         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 924
 925         /* RA 0 is active */
 926         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 927
 928         /* all 6 fifo are active */
 929         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 930
 931         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 932         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 933         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 934         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 935
 936         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 937                              priv->shared_phys);
 938
 939         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 940                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 941                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 942                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 943                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 944                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 945                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 946                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 947
 948
 949         return 0;
 950 }
 951
 952 /**
 953  * iwl3945_txq_ctx_reset - Reset TX queue context
 954  *
 955  * Destroys all DMA structures and initialize them again
 956  */
 957 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 958 {
 959         int rc;
 960         int txq_id, slots_num;
 961
 962         iwl3945_hw_txq_ctx_free(priv);
 963
 964         /* Tx CMD queue */
 965         rc = iwl3945_tx_reset(priv);
 966         if (rc)
 967                 goto error;
 968
 969         /* Tx queue(s) */
 970         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 971                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
 972                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 973                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 974                                        txq_id);
 975                 if (rc) {
 976                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
 977                         goto error;
 978                 }
 979         }
 980
 981         return rc;
 982
 983  error:
 984         iwl3945_hw_txq_ctx_free(priv);
 985         return rc;
 986 }
 987
 988 static int iwl3945_apm_init(struct iwl_priv *priv)
 989 {
 990         int ret;
 991
 992         iwl_power_initialize(priv);
 993
 994         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 995                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 996
 997         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 998         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 999                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1000
1001         /* set "initialization complete" bit to move adapter
1002         * D0U* --> D0A* state */
1003         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1004
1005         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1006                             CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1007         if (ret < 0) {
1008                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1009                 goto out;
1010         }
1011
1012         /* enable DMA */
1013         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1014                                                 APMG_CLK_VAL_BSM_CLK_RQT);
1015
1016         udelay(20);
1017
1018         /* disable L1-Active */
1019         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1020                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1021
1022 out:
1023         return ret;
1024 }
1025
1026 static void iwl3945_nic_config(struct iwl_priv *priv)
1027 {
1028         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1029         unsigned long flags;
1030         u8 rev_id = 0;
1031
1032         spin_lock_irqsave(&priv->lock, flags);
1033
1034         /* Determine HW type */
1035         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1036
1037         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1038
1039         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1040                 IWL_DEBUG_INFO(priv, "RTP type \n");
1041         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1042                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1043                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1044                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1045         } else {
1046                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1047                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1048                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1049         }
1050
1051         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1052                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1053                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1054                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1055         } else
1056                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1057
1058         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1059                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1060                                eeprom->board_revision);
1061                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1062                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1063         } else {
1064                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1065                                eeprom->board_revision);
1066                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1067                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1068         }
1069
1070         if (eeprom->almgor_m_version <= 1) {
1071                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1072                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1073                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1074                                eeprom->almgor_m_version);
1075         } else {
1076                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1077                                eeprom->almgor_m_version);
1078                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1079                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1080         }
1081         spin_unlock_irqrestore(&priv->lock, flags);
1082
1083         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1084                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1085
1086         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1087                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1088 }
1089
1090 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1091 {
1092         int rc;
1093         unsigned long flags;
1094         struct iwl_rx_queue *rxq = &priv->rxq;
1095
1096         spin_lock_irqsave(&priv->lock, flags);
1097         priv->cfg->ops->lib->apm_ops.init(priv);
1098         spin_unlock_irqrestore(&priv->lock, flags);
1099
1100         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1101         if (rc)
1102                 return rc;
1103
1104         priv->cfg->ops->lib->apm_ops.config(priv);
1105
1106         /* Allocate the RX queue, or reset if it is already allocated */
1107         if (!rxq->bd) {
1108                 rc = iwl_rx_queue_alloc(priv);
1109                 if (rc) {
1110                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1111                         return -ENOMEM;
1112                 }
1113         } else
1114                 iwl3945_rx_queue_reset(priv, rxq);
1115
1116         iwl3945_rx_replenish(priv);
1117
1118         iwl3945_rx_init(priv, rxq);
1119
1120
1121         /* Look at using this instead:
1122         rxq->need_update = 1;
1123         iwl_rx_queue_update_write_ptr(priv, rxq);
1124         */
1125
1126         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1127
1128         rc = iwl3945_txq_ctx_reset(priv);
1129         if (rc)
1130                 return rc;
1131
1132         set_bit(STATUS_INIT, &priv->status);
1133
1134         return 0;
1135 }
1136
1137 /**
1138  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1139  *
1140  * Destroy all TX DMA queues and structures
1141  */
1142 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1143 {
1144         int txq_id;
1145
1146         /* Tx queues */
1147         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1148                 if (txq_id == IWL_CMD_QUEUE_NUM)
1149                         iwl_cmd_queue_free(priv);
1150                 else
1151                         iwl_tx_queue_free(priv, txq_id);
1152
1153 }
1154
1155 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1156 {
1157         int txq_id;
1158
1159         /* stop SCD */
1160         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1161
1162         /* reset TFD queues */
1163         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1164                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1165                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1166                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1167                                 1000);
1168         }
1169
1170         iwl3945_hw_txq_ctx_free(priv);
1171 }
1172
1173 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1174 {
1175         int ret = 0;
1176         unsigned long flags;
1177
1178         spin_lock_irqsave(&priv->lock, flags);
1179
1180         /* set stop master bit */
1181         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1182
1183         iwl_poll_direct_bit(priv, CSR_RESET,
1184                             CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1185
1186         if (ret < 0)
1187                 goto out;
1188
1189 out:
1190         spin_unlock_irqrestore(&priv->lock, flags);
1191         IWL_DEBUG_INFO(priv, "stop master\n");
1192
1193         return ret;
1194 }
1195
1196 static void iwl3945_apm_stop(struct iwl_priv *priv)
1197 {
1198         unsigned long flags;
1199
1200         iwl3945_apm_stop_master(priv);
1201
1202         spin_lock_irqsave(&priv->lock, flags);
1203
1204         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1205
1206         udelay(10);
1207         /* clear "init complete"  move adapter D0A* --> D0U state */
1208         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1209         spin_unlock_irqrestore(&priv->lock, flags);
1210 }
1211
1212 static int iwl3945_apm_reset(struct iwl_priv *priv)
1213 {
1214         iwl3945_apm_stop_master(priv);
1215
1216
1217         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1218         udelay(10);
1219
1220         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1221
1222         iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1223                          CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1224
1225         iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1226                                 APMG_CLK_VAL_BSM_CLK_RQT);
1227
1228         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1229         iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1230                                         0xFFFFFFFF);
1231
1232         /* enable DMA */
1233         iwl_write_prph(priv, APMG_CLK_EN_REG,
1234                                 APMG_CLK_VAL_DMA_CLK_RQT |
1235                                 APMG_CLK_VAL_BSM_CLK_RQT);
1236         udelay(10);
1237
1238         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1239                                 APMG_PS_CTRL_VAL_RESET_REQ);
1240         udelay(5);
1241         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1242                                 APMG_PS_CTRL_VAL_RESET_REQ);
1243
1244         /* Clear the 'host command active' bit... */
1245         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1246
1247         wake_up_interruptible(&priv->wait_command_queue);
1248
1249         return 0;
1250 }
1251
1252 /**
1253  * iwl3945_hw_reg_adjust_power_by_temp
1254  * return index delta into power gain settings table
1255 */
1256 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1257 {
1258         return (new_reading - old_reading) * (-11) / 100;
1259 }
1260
1261 /**
1262  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1263  */
1264 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1265 {
1266         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1267 }
1268
1269 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1270 {
1271         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1272 }
1273
1274 /**
1275  * iwl3945_hw_reg_txpower_get_temperature
1276  * get the current temperature by reading from NIC
1277 */
1278 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1279 {
1280         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1281         int temperature;
1282
1283         temperature = iwl3945_hw_get_temperature(priv);
1284
1285         /* driver's okay range is -260 to +25.
1286          *   human readable okay range is 0 to +285 */
1287         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1288
1289         /* handle insane temp reading */
1290         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1291                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1292
1293                 /* if really really hot(?),
1294                  *   substitute the 3rd band/group's temp measured at factory */
1295                 if (priv->last_temperature > 100)
1296                         temperature = eeprom->groups[2].temperature;
1297                 else /* else use most recent "sane" value from driver */
1298                         temperature = priv->last_temperature;
1299         }
1300
1301         return temperature;     /* raw, not "human readable" */
1302 }
1303
1304 /* Adjust Txpower only if temperature variance is greater than threshold.
1305  *
1306  * Both are lower than older versions' 9 degrees */
1307 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1308
1309 /**
1310  * is_temp_calib_needed - determines if new calibration is needed
1311  *
1312  * records new temperature in tx_mgr->temperature.
1313  * replaces tx_mgr->last_temperature *only* if calib needed
1314  *    (assumes caller will actually do the calibration!). */
1315 static int is_temp_calib_needed(struct iwl_priv *priv)
1316 {
1317         int temp_diff;
1318
1319         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1320         temp_diff = priv->temperature - priv->last_temperature;
1321
1322         /* get absolute value */
1323         if (temp_diff < 0) {
1324                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1325                 temp_diff = -temp_diff;
1326         } else if (temp_diff == 0)
1327                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1328         else
1329                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1330
1331         /* if we don't need calibration, *don't* update last_temperature */
1332         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1333                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1334                 return 0;
1335         }
1336
1337         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1338
1339         /* assume that caller will actually do calib ...
1340          *   update the "last temperature" value */
1341         priv->last_temperature = priv->temperature;
1342         return 1;
1343 }
1344
1345 #define IWL_MAX_GAIN_ENTRIES 78
1346 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1347 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1348
1349 /* radio and DSP power table, each step is 1/2 dB.
1350  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1351 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1352         {
1353          {251, 127},            /* 2.4 GHz, highest power */
1354          {251, 127},
1355          {251, 127},
1356          {251, 127},
1357          {251, 125},
1358          {251, 110},
1359          {251, 105},
1360          {251, 98},
1361          {187, 125},
1362          {187, 115},
1363          {187, 108},
1364          {187, 99},
1365          {243, 119},
1366          {243, 111},
1367          {243, 105},
1368          {243, 97},
1369          {243, 92},
1370          {211, 106},
1371          {211, 100},
1372          {179, 120},
1373          {179, 113},
1374          {179, 107},
1375          {147, 125},
1376          {147, 119},
1377          {147, 112},
1378          {147, 106},
1379          {147, 101},
1380          {147, 97},
1381          {147, 91},
1382          {115, 107},
1383          {235, 121},
1384          {235, 115},
1385          {235, 109},
1386          {203, 127},
1387          {203, 121},
1388          {203, 115},
1389          {203, 108},
1390          {203, 102},
1391          {203, 96},
1392          {203, 92},
1393          {171, 110},
1394          {171, 104},
1395          {171, 98},
1396          {139, 116},
1397          {227, 125},
1398          {227, 119},
1399          {227, 113},
1400          {227, 107},
1401          {227, 101},
1402          {227, 96},
1403          {195, 113},
1404          {195, 106},
1405          {195, 102},
1406          {195, 95},
1407          {163, 113},
1408          {163, 106},
1409          {163, 102},
1410          {163, 95},
1411          {131, 113},
1412          {131, 106},
1413          {131, 102},
1414          {131, 95},
1415          {99, 113},
1416          {99, 106},
1417          {99, 102},
1418          {99, 95},
1419          {67, 113},
1420          {67, 106},
1421          {67, 102},
1422          {67, 95},
1423          {35, 113},
1424          {35, 106},
1425          {35, 102},
1426          {35, 95},
1427          {3, 113},
1428          {3, 106},
1429          {3, 102},
1430          {3, 95} },             /* 2.4 GHz, lowest power */
1431         {
1432          {251, 127},            /* 5.x GHz, highest power */
1433          {251, 120},
1434          {251, 114},
1435          {219, 119},
1436          {219, 101},
1437          {187, 113},
1438          {187, 102},
1439          {155, 114},
1440          {155, 103},
1441          {123, 117},
1442          {123, 107},
1443          {123, 99},
1444          {123, 92},
1445          {91, 108},
1446          {59, 125},
1447          {59, 118},
1448          {59, 109},
1449          {59, 102},
1450          {59, 96},
1451          {59, 90},
1452          {27, 104},
1453          {27, 98},
1454          {27, 92},
1455          {115, 118},
1456          {115, 111},
1457          {115, 104},
1458          {83, 126},
1459          {83, 121},
1460          {83, 113},
1461          {83, 105},
1462          {83, 99},
1463          {51, 118},
1464          {51, 111},
1465          {51, 104},
1466          {51, 98},
1467          {19, 116},
1468          {19, 109},
1469          {19, 102},
1470          {19, 98},
1471          {19, 93},
1472          {171, 113},
1473          {171, 107},
1474          {171, 99},
1475          {139, 120},
1476          {139, 113},
1477          {139, 107},
1478          {139, 99},
1479          {107, 120},
1480          {107, 113},
1481          {107, 107},
1482          {107, 99},
1483          {75, 120},
1484          {75, 113},
1485          {75, 107},
1486          {75, 99},
1487          {43, 120},
1488          {43, 113},
1489          {43, 107},
1490          {43, 99},
1491          {11, 120},
1492          {11, 113},
1493          {11, 107},
1494          {11, 99},
1495          {131, 107},
1496          {131, 99},
1497          {99, 120},
1498          {99, 113},
1499          {99, 107},
1500          {99, 99},
1501          {67, 120},
1502          {67, 113},
1503          {67, 107},
1504          {67, 99},
1505          {35, 120},
1506          {35, 113},
1507          {35, 107},
1508          {35, 99},
1509          {3, 120} }             /* 5.x GHz, lowest power */
1510 };
1511
1512 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1513 {
1514         if (index < 0)
1515                 return 0;
1516         if (index >= IWL_MAX_GAIN_ENTRIES)
1517                 return IWL_MAX_GAIN_ENTRIES - 1;
1518         return (u8) index;
1519 }
1520
1521 /* Kick off thermal recalibration check every 60 seconds */
1522 #define REG_RECALIB_PERIOD (60)
1523
1524 /**
1525  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1526  *
1527  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1528  * or 6 Mbit (OFDM) rates.
1529  */
1530 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1531                                s32 rate_index, const s8 *clip_pwrs,
1532                                struct iwl_channel_info *ch_info,
1533                                int band_index)
1534 {
1535         struct iwl3945_scan_power_info *scan_power_info;
1536         s8 power;
1537         u8 power_index;
1538
1539         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1540
1541         /* use this channel group's 6Mbit clipping/saturation pwr,
1542          *   but cap at regulatory scan power restriction (set during init
1543          *   based on eeprom channel data) for this channel.  */
1544         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1545
1546         /* further limit to user's max power preference.
1547          * FIXME:  Other spectrum management power limitations do not
1548          *   seem to apply?? */
1549         power = min(power, priv->tx_power_user_lmt);
1550         scan_power_info->requested_power = power;
1551
1552         /* find difference between new scan *power* and current "normal"
1553          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1554          *   current "normal" temperature-compensated Tx power *index* for
1555          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1556          *   *index*. */
1557         power_index = ch_info->power_info[rate_index].power_table_index
1558             - (power - ch_info->power_info
1559                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1560
1561         /* store reference index that we use when adjusting *all* scan
1562          *   powers.  So we can accommodate user (all channel) or spectrum
1563          *   management (single channel) power changes "between" temperature
1564          *   feedback compensation procedures.
1565          * don't force fit this reference index into gain table; it may be a
1566          *   negative number.  This will help avoid errors when we're at
1567          *   the lower bounds (highest gains, for warmest temperatures)
1568          *   of the table. */
1569
1570         /* don't exceed table bounds for "real" setting */
1571         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1572
1573         scan_power_info->power_table_index = power_index;
1574         scan_power_info->tpc.tx_gain =
1575             power_gain_table[band_index][power_index].tx_gain;
1576         scan_power_info->tpc.dsp_atten =
1577             power_gain_table[band_index][power_index].dsp_atten;
1578 }
1579
1580 /**
1581  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1582  *
1583  * Configures power settings for all rates for the current channel,
1584  * using values from channel info struct, and send to NIC
1585  */
1586 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1587 {
1588         int rate_idx, i;
1589         const struct iwl_channel_info *ch_info = NULL;
1590         struct iwl3945_txpowertable_cmd txpower = {
1591                 .channel = priv->active_rxon.channel,
1592         };
1593
1594         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1595         ch_info = iwl_get_channel_info(priv,
1596                                        priv->band,
1597                                        le16_to_cpu(priv->active_rxon.channel));
1598         if (!ch_info) {
1599                 IWL_ERR(priv,
1600                         "Failed to get channel info for channel %d [%d]\n",
1601                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1602                 return -EINVAL;
1603         }
1604
1605         if (!is_channel_valid(ch_info)) {
1606                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1607                                 "non-Tx channel.\n");
1608                 return 0;
1609         }
1610
1611         /* fill cmd with power settings for all rates for current channel */
1612         /* Fill OFDM rate */
1613         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1614              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1615
1616                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1617                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1618
1619                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1620                                 le16_to_cpu(txpower.channel),
1621                                 txpower.band,
1622                                 txpower.power[i].tpc.tx_gain,
1623                                 txpower.power[i].tpc.dsp_atten,
1624                                 txpower.power[i].rate);
1625         }
1626         /* Fill CCK rates */
1627         for (rate_idx = IWL_FIRST_CCK_RATE;
1628              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1629                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1630                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1631
1632                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1633                                 le16_to_cpu(txpower.channel),
1634                                 txpower.band,
1635                                 txpower.power[i].tpc.tx_gain,
1636                                 txpower.power[i].tpc.dsp_atten,
1637                                 txpower.power[i].rate);
1638         }
1639
1640         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1641                                 sizeof(struct iwl3945_txpowertable_cmd),
1642                                 &txpower);
1643
1644 }
1645
1646 /**
1647  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1648  * @ch_info: Channel to update.  Uses power_info.requested_power.
1649  *
1650  * Replace requested_power and base_power_index ch_info fields for
1651  * one channel.
1652  *
1653  * Called if user or spectrum management changes power preferences.
1654  * Takes into account h/w and modulation limitations (clip power).
1655  *
1656  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1657  *
1658  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1659  *       properly fill out the scan powers, and actual h/w gain settings,
1660  *       and send changes to NIC
1661  */
1662 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1663                              struct iwl_channel_info *ch_info)
1664 {
1665         struct iwl3945_channel_power_info *power_info;
1666         int power_changed = 0;
1667         int i;
1668         const s8 *clip_pwrs;
1669         int power;
1670
1671         /* Get this chnlgrp's rate-to-max/clip-powers table */
1672         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1673
1674         /* Get this channel's rate-to-current-power settings table */
1675         power_info = ch_info->power_info;
1676
1677         /* update OFDM Txpower settings */
1678         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1679              i++, ++power_info) {
1680                 int delta_idx;
1681
1682                 /* limit new power to be no more than h/w capability */
1683                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1684                 if (power == power_info->requested_power)
1685                         continue;
1686
1687                 /* find difference between old and new requested powers,
1688                  *    update base (non-temp-compensated) power index */
1689                 delta_idx = (power - power_info->requested_power) * 2;
1690                 power_info->base_power_index -= delta_idx;
1691
1692                 /* save new requested power value */
1693                 power_info->requested_power = power;
1694
1695                 power_changed = 1;
1696         }
1697
1698         /* update CCK Txpower settings, based on OFDM 12M setting ...
1699          *    ... all CCK power settings for a given channel are the *same*. */
1700         if (power_changed) {
1701                 power =
1702                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1703                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1704
1705                 /* do all CCK rates' iwl3945_channel_power_info structures */
1706                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1707                         power_info->requested_power = power;
1708                         power_info->base_power_index =
1709                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1710                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1711                         ++power_info;
1712                 }
1713         }
1714
1715         return 0;
1716 }
1717
1718 /**
1719  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1720  *
1721  * NOTE: Returned power limit may be less (but not more) than requested,
1722  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1723  *       (no consideration for h/w clipping limitations).
1724  */
1725 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1726 {
1727         s8 max_power;
1728
1729 #if 0
1730         /* if we're using TGd limits, use lower of TGd or EEPROM */
1731         if (ch_info->tgd_data.max_power != 0)
1732                 max_power = min(ch_info->tgd_data.max_power,
1733                                 ch_info->eeprom.max_power_avg);
1734
1735         /* else just use EEPROM limits */
1736         else
1737 #endif
1738                 max_power = ch_info->eeprom.max_power_avg;
1739
1740         return min(max_power, ch_info->max_power_avg);
1741 }
1742
1743 /**
1744  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1745  *
1746  * Compensate txpower settings of *all* channels for temperature.
1747  * This only accounts for the difference between current temperature
1748  *   and the factory calibration temperatures, and bases the new settings
1749  *   on the channel's base_power_index.
1750  *
1751  * If RxOn is "associated", this sends the new Txpower to NIC!
1752  */
1753 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1754 {
1755         struct iwl_channel_info *ch_info = NULL;
1756         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1757         int delta_index;
1758         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1759         u8 a_band;
1760         u8 rate_index;
1761         u8 scan_tbl_index;
1762         u8 i;
1763         int ref_temp;
1764         int temperature = priv->temperature;
1765
1766         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1767         for (i = 0; i < priv->channel_count; i++) {
1768                 ch_info = &priv->channel_info[i];
1769                 a_band = is_channel_a_band(ch_info);
1770
1771                 /* Get this chnlgrp's factory calibration temperature */
1772                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1773                     temperature;
1774
1775                 /* get power index adjustment based on current and factory
1776                  * temps */
1777                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1778                                                               ref_temp);
1779
1780                 /* set tx power value for all rates, OFDM and CCK */
1781                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1782                      rate_index++) {
1783                         int power_idx =
1784                             ch_info->power_info[rate_index].base_power_index;
1785
1786                         /* temperature compensate */
1787                         power_idx += delta_index;
1788
1789                         /* stay within table range */
1790                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1791                         ch_info->power_info[rate_index].
1792                             power_table_index = (u8) power_idx;
1793                         ch_info->power_info[rate_index].tpc =
1794                             power_gain_table[a_band][power_idx];
1795                 }
1796
1797                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1798                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1799
1800                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1801                 for (scan_tbl_index = 0;
1802                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1803                         s32 actual_index = (scan_tbl_index == 0) ?
1804                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1805                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1806                                            actual_index, clip_pwrs,
1807                                            ch_info, a_band);
1808                 }
1809         }
1810
1811         /* send Txpower command for current channel to ucode */
1812         return priv->cfg->ops->lib->send_tx_power(priv);
1813 }
1814
1815 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1816 {
1817         struct iwl_channel_info *ch_info;
1818         s8 max_power;
1819         u8 a_band;
1820         u8 i;
1821
1822         if (priv->tx_power_user_lmt == power) {
1823                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1824                                 "limit: %ddBm.\n", power);
1825                 return 0;
1826         }
1827
1828         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1829         priv->tx_power_user_lmt = power;
1830
1831         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1832
1833         for (i = 0; i < priv->channel_count; i++) {
1834                 ch_info = &priv->channel_info[i];
1835                 a_band = is_channel_a_band(ch_info);
1836
1837                 /* find minimum power of all user and regulatory constraints
1838                  *    (does not consider h/w clipping limitations) */
1839                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1840                 max_power = min(power, max_power);
1841                 if (max_power != ch_info->curr_txpow) {
1842                         ch_info->curr_txpow = max_power;
1843
1844                         /* this considers the h/w clipping limitations */
1845                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1846                 }
1847         }
1848
1849         /* update txpower settings for all channels,
1850          *   send to NIC if associated. */
1851         is_temp_calib_needed(priv);
1852         iwl3945_hw_reg_comp_txpower_temp(priv);
1853
1854         return 0;
1855 }
1856
1857 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1858 {
1859         int rc = 0;
1860         struct iwl_rx_packet *res = NULL;
1861         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1862         struct iwl_host_cmd cmd = {
1863                 .id = REPLY_RXON_ASSOC,
1864                 .len = sizeof(rxon_assoc),
1865                 .flags = CMD_WANT_SKB,
1866                 .data = &rxon_assoc,
1867         };
1868         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1869         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1870
1871         if ((rxon1->flags == rxon2->flags) &&
1872             (rxon1->filter_flags == rxon2->filter_flags) &&
1873             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1874             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1875                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1876                 return 0;
1877         }
1878
1879         rxon_assoc.flags = priv->staging_rxon.flags;
1880         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1881         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1882         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1883         rxon_assoc.reserved = 0;
1884
1885         rc = iwl_send_cmd_sync(priv, &cmd);
1886         if (rc)
1887                 return rc;
1888
1889         res = (struct iwl_rx_packet *)cmd.reply_skb->data;
1890         if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1891                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1892                 rc = -EIO;
1893         }
1894
1895         priv->alloc_rxb_skb--;
1896         dev_kfree_skb_any(cmd.reply_skb);
1897
1898         return rc;
1899 }
1900
1901 /**
1902  * iwl3945_commit_rxon - commit staging_rxon to hardware
1903  *
1904  * The RXON command in staging_rxon is committed to the hardware and
1905  * the active_rxon structure is updated with the new data.  This
1906  * function correctly transitions out of the RXON_ASSOC_MSK state if
1907  * a HW tune is required based on the RXON structure changes.
1908  */
1909 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1910 {
1911         /* cast away the const for active_rxon in this function */
1912         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1913         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1914         int rc = 0;
1915         bool new_assoc =
1916                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1917
1918         if (!iwl_is_alive(priv))
1919                 return -1;
1920
1921         /* always get timestamp with Rx frame */
1922         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1923
1924         /* select antenna */
1925         staging_rxon->flags &=
1926             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1927         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1928
1929         rc = iwl_check_rxon_cmd(priv);
1930         if (rc) {
1931                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1932                 return -EINVAL;
1933         }
1934
1935         /* If we don't need to send a full RXON, we can use
1936          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1937          * and other flags for the current radio configuration. */
1938         if (!iwl_full_rxon_required(priv)) {
1939                 rc = iwl_send_rxon_assoc(priv);
1940                 if (rc) {
1941                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1942                                   "configuration (%d).\n", rc);
1943                         return rc;
1944                 }
1945
1946                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1947
1948                 return 0;
1949         }
1950
1951         /* If we are currently associated and the new config requires
1952          * an RXON_ASSOC and the new config wants the associated mask enabled,
1953          * we must clear the associated from the active configuration
1954          * before we apply the new config */
1955         if (iwl_is_associated(priv) && new_assoc) {
1956                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1957                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1958
1959                 /*
1960                  * reserved4 and 5 could have been filled by the iwlcore code.
1961                  * Let's clear them before pushing to the 3945.
1962                  */
1963                 active_rxon->reserved4 = 0;
1964                 active_rxon->reserved5 = 0;
1965                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1966                                       sizeof(struct iwl3945_rxon_cmd),
1967                                       &priv->active_rxon);
1968
1969                 /* If the mask clearing failed then we set
1970                  * active_rxon back to what it was previously */
1971                 if (rc) {
1972                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1973                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1974                                   "configuration (%d).\n", rc);
1975                         return rc;
1976                 }
1977         }
1978
1979         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1980                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1981                        "* channel = %d\n"
1982                        "* bssid = %pM\n",
1983                        (new_assoc ? "" : "out"),
1984                        le16_to_cpu(staging_rxon->channel),
1985                        staging_rxon->bssid_addr);
1986
1987         /*
1988          * reserved4 and 5 could have been filled by the iwlcore code.
1989          * Let's clear them before pushing to the 3945.
1990          */
1991         staging_rxon->reserved4 = 0;
1992         staging_rxon->reserved5 = 0;
1993
1994         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1995
1996         /* Apply the new configuration */
1997         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1998                               sizeof(struct iwl3945_rxon_cmd),
1999                               staging_rxon);
2000         if (rc) {
2001                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
2002                 return rc;
2003         }
2004
2005         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
2006
2007         iwl_clear_stations_table(priv);
2008
2009         /* If we issue a new RXON command which required a tune then we must
2010          * send a new TXPOWER command or we won't be able to Tx any frames */
2011         rc = priv->cfg->ops->lib->send_tx_power(priv);
2012         if (rc) {
2013                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
2014                 return rc;
2015         }
2016
2017         /* Add the broadcast address so we can send broadcast frames */
2018         if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
2019             IWL_INVALID_STATION) {
2020                 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
2021                 return -EIO;
2022         }
2023
2024         /* If we have set the ASSOC_MSK and we are in BSS mode then
2025          * add the IWL_AP_ID to the station rate table */
2026         if (iwl_is_associated(priv) &&
2027             (priv->iw_mode == NL80211_IFTYPE_STATION))
2028                 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
2029                                 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
2030                         IWL_ERR(priv, "Error adding AP address for transmit\n");
2031                         return -EIO;
2032                 }
2033
2034         /* Init the hardware's rate fallback order based on the band */
2035         rc = iwl3945_init_hw_rate_table(priv);
2036         if (rc) {
2037                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
2038                 return -EIO;
2039         }
2040
2041         return 0;
2042 }
2043
2044 /* will add 3945 channel switch cmd handling later */
2045 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2046 {
2047         return 0;
2048 }
2049
2050 /**
2051  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
2052  *
2053  * -- reset periodic timer
2054  * -- see if temp has changed enough to warrant re-calibration ... if so:
2055  *     -- correct coeffs for temp (can reset temp timer)
2056  *     -- save this temp as "last",
2057  *     -- send new set of gain settings to NIC
2058  * NOTE:  This should continue working, even when we're not associated,
2059  *   so we can keep our internal table of scan powers current. */
2060 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
2061 {
2062         /* This will kick in the "brute force"
2063          * iwl3945_hw_reg_comp_txpower_temp() below */
2064         if (!is_temp_calib_needed(priv))
2065                 goto reschedule;
2066
2067         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2068          * This is based *only* on current temperature,
2069          * ignoring any previous power measurements */
2070         iwl3945_hw_reg_comp_txpower_temp(priv);
2071
2072  reschedule:
2073         queue_delayed_work(priv->workqueue,
2074                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2075 }
2076
2077 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2078 {
2079         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2080                                              thermal_periodic.work);
2081
2082         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2083                 return;
2084
2085         mutex_lock(&priv->mutex);
2086         iwl3945_reg_txpower_periodic(priv);
2087         mutex_unlock(&priv->mutex);
2088 }
2089
2090 /**
2091  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2092  *                                 for the channel.
2093  *
2094  * This function is used when initializing channel-info structs.
2095  *
2096  * NOTE: These channel groups do *NOT* match the bands above!
2097  *       These channel groups are based on factory-tested channels;
2098  *       on A-band, EEPROM's "group frequency" entries represent the top
2099  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2100  */
2101 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2102                                        const struct iwl_channel_info *ch_info)
2103 {
2104         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2105         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2106         u8 group;
2107         u16 group_index = 0;    /* based on factory calib frequencies */
2108         u8 grp_channel;
2109
2110         /* Find the group index for the channel ... don't use index 1(?) */
2111         if (is_channel_a_band(ch_info)) {
2112                 for (group = 1; group < 5; group++) {
2113                         grp_channel = ch_grp[group].group_channel;
2114                         if (ch_info->channel <= grp_channel) {
2115                                 group_index = group;
2116                                 break;
2117                         }
2118                 }
2119                 /* group 4 has a few channels *above* its factory cal freq */
2120                 if (group == 5)
2121                         group_index = 4;
2122         } else
2123                 group_index = 0;        /* 2.4 GHz, group 0 */
2124
2125         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2126                         group_index);
2127         return group_index;
2128 }
2129
2130 /**
2131  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2132  *
2133  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2134  *   into radio/DSP gain settings table for requested power.
2135  */
2136 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2137                                        s8 requested_power,
2138                                        s32 setting_index, s32 *new_index)
2139 {
2140         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2141         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2142         s32 index0, index1;
2143         s32 power = 2 * requested_power;
2144         s32 i;
2145         const struct iwl3945_eeprom_txpower_sample *samples;
2146         s32 gains0, gains1;
2147         s32 res;
2148         s32 denominator;
2149
2150         chnl_grp = &eeprom->groups[setting_index];
2151         samples = chnl_grp->samples;
2152         for (i = 0; i < 5; i++) {
2153                 if (power == samples[i].power) {
2154                         *new_index = samples[i].gain_index;
2155                         return 0;
2156                 }
2157         }
2158
2159         if (power > samples[1].power) {
2160                 index0 = 0;
2161                 index1 = 1;
2162         } else if (power > samples[2].power) {
2163                 index0 = 1;
2164                 index1 = 2;
2165         } else if (power > samples[3].power) {
2166                 index0 = 2;
2167                 index1 = 3;
2168         } else {
2169                 index0 = 3;
2170                 index1 = 4;
2171         }
2172
2173         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2174         if (denominator == 0)
2175                 return -EINVAL;
2176         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2177         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2178         res = gains0 + (gains1 - gains0) *
2179             ((s32) power - (s32) samples[index0].power) / denominator +
2180             (1 << 18);
2181         *new_index = res >> 19;
2182         return 0;
2183 }
2184
2185 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2186 {
2187         u32 i;
2188         s32 rate_index;
2189         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2190         const struct iwl3945_eeprom_txpower_group *group;
2191
2192         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2193
2194         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2195                 s8 *clip_pwrs;  /* table of power levels for each rate */
2196                 s8 satur_pwr;   /* saturation power for each chnl group */
2197                 group = &eeprom->groups[i];
2198
2199                 /* sanity check on factory saturation power value */
2200                 if (group->saturation_power < 40) {
2201                         IWL_WARN(priv, "Error: saturation power is %d, "
2202                                     "less than minimum expected 40\n",
2203                                     group->saturation_power);
2204                         return;
2205                 }
2206
2207                 /*
2208                  * Derive requested power levels for each rate, based on
2209                  *   hardware capabilities (saturation power for band).
2210                  * Basic value is 3dB down from saturation, with further
2211                  *   power reductions for highest 3 data rates.  These
2212                  *   backoffs provide headroom for high rate modulation
2213                  *   power peaks, without too much distortion (clipping).
2214                  */
2215                 /* we'll fill in this array with h/w max power levels */
2216                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2217
2218                 /* divide factory saturation power by 2 to find -3dB level */
2219                 satur_pwr = (s8) (group->saturation_power >> 1);
2220
2221                 /* fill in channel group's nominal powers for each rate */
2222                 for (rate_index = 0;
2223                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2224                         switch (rate_index) {
2225                         case IWL_RATE_36M_INDEX_TABLE:
2226                                 if (i == 0)     /* B/G */
2227                                         *clip_pwrs = satur_pwr;
2228                                 else    /* A */
2229                                         *clip_pwrs = satur_pwr - 5;
2230                                 break;
2231                         case IWL_RATE_48M_INDEX_TABLE:
2232                                 if (i == 0)
2233                                         *clip_pwrs = satur_pwr - 7;
2234                                 else
2235                                         *clip_pwrs = satur_pwr - 10;
2236                                 break;
2237                         case IWL_RATE_54M_INDEX_TABLE:
2238                                 if (i == 0)
2239                                         *clip_pwrs = satur_pwr - 9;
2240                                 else
2241                                         *clip_pwrs = satur_pwr - 12;
2242                                 break;
2243                         default:
2244                                 *clip_pwrs = satur_pwr;
2245                                 break;
2246                         }
2247                 }
2248         }
2249 }
2250
2251 /**
2252  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2253  *
2254  * Second pass (during init) to set up priv->channel_info
2255  *
2256  * Set up Tx-power settings in our channel info database for each VALID
2257  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2258  * and current temperature.
2259  *
2260  * Since this is based on current temperature (at init time), these values may
2261  * not be valid for very long, but it gives us a starting/default point,
2262  * and allows us to active (i.e. using Tx) scan.
2263  *
2264  * This does *not* write values to NIC, just sets up our internal table.
2265  */
2266 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2267 {
2268         struct iwl_channel_info *ch_info = NULL;
2269         struct iwl3945_channel_power_info *pwr_info;
2270         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2271         int delta_index;
2272         u8 rate_index;
2273         u8 scan_tbl_index;
2274         const s8 *clip_pwrs;    /* array of power levels for each rate */
2275         u8 gain, dsp_atten;
2276         s8 power;
2277         u8 pwr_index, base_pwr_index, a_band;
2278         u8 i;
2279         int temperature;
2280
2281         /* save temperature reference,
2282          *   so we can determine next time to calibrate */
2283         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2284         priv->last_temperature = temperature;
2285
2286         iwl3945_hw_reg_init_channel_groups(priv);
2287
2288         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2289         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2290              i++, ch_info++) {
2291                 a_band = is_channel_a_band(ch_info);
2292                 if (!is_channel_valid(ch_info))
2293                         continue;
2294
2295                 /* find this channel's channel group (*not* "band") index */
2296                 ch_info->group_index =
2297                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2298
2299                 /* Get this chnlgrp's rate->max/clip-powers table */
2300                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2301
2302                 /* calculate power index *adjustment* value according to
2303                  *  diff between current temperature and factory temperature */
2304                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2305                                 eeprom->groups[ch_info->group_index].
2306                                 temperature);
2307
2308                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2309                                 ch_info->channel, delta_index, temperature +
2310                                 IWL_TEMP_CONVERT);
2311
2312                 /* set tx power value for all OFDM rates */
2313                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2314                      rate_index++) {
2315                         s32 uninitialized_var(power_idx);
2316                         int rc;
2317
2318                         /* use channel group's clip-power table,
2319                          *   but don't exceed channel's max power */
2320                         s8 pwr = min(ch_info->max_power_avg,
2321                                      clip_pwrs[rate_index]);
2322
2323                         pwr_info = &ch_info->power_info[rate_index];
2324
2325                         /* get base (i.e. at factory-measured temperature)
2326                          *    power table index for this rate's power */
2327                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2328                                                          ch_info->group_index,
2329                                                          &power_idx);
2330                         if (rc) {
2331                                 IWL_ERR(priv, "Invalid power index\n");
2332                                 return rc;
2333                         }
2334                         pwr_info->base_power_index = (u8) power_idx;
2335
2336                         /* temperature compensate */
2337                         power_idx += delta_index;
2338
2339                         /* stay within range of gain table */
2340                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2341
2342                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2343                         pwr_info->requested_power = pwr;
2344                         pwr_info->power_table_index = (u8) power_idx;
2345                         pwr_info->tpc.tx_gain =
2346                             power_gain_table[a_band][power_idx].tx_gain;
2347                         pwr_info->tpc.dsp_atten =
2348                             power_gain_table[a_band][power_idx].dsp_atten;
2349                 }
2350
2351                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2352                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2353                 power = pwr_info->requested_power +
2354                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2355                 pwr_index = pwr_info->power_table_index +
2356                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2357                 base_pwr_index = pwr_info->base_power_index +
2358                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2359
2360                 /* stay within table range */
2361                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2362                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2363                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2364
2365                 /* fill each CCK rate's iwl3945_channel_power_info structure
2366                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2367                  * NOTE:  CCK rates start at end of OFDM rates! */
2368                 for (rate_index = 0;
2369                      rate_index < IWL_CCK_RATES; rate_index++) {
2370                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2371                         pwr_info->requested_power = power;
2372                         pwr_info->power_table_index = pwr_index;
2373                         pwr_info->base_power_index = base_pwr_index;
2374                         pwr_info->tpc.tx_gain = gain;
2375                         pwr_info->tpc.dsp_atten = dsp_atten;
2376                 }
2377
2378                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2379                 for (scan_tbl_index = 0;
2380                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2381                         s32 actual_index = (scan_tbl_index == 0) ?
2382                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2383                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2384                                 actual_index, clip_pwrs, ch_info, a_band);
2385                 }
2386         }
2387
2388         return 0;
2389 }
2390
2391 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2392 {
2393         int rc;
2394
2395         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2396         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2397                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2398         if (rc < 0)
2399                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2400
2401         return 0;
2402 }
2403
2404 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2405 {
2406         int txq_id = txq->q.id;
2407
2408         struct iwl3945_shared *shared_data = priv->shared_virt;
2409
2410         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2411
2412         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2413         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2414
2415         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2416                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2417                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2418                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2419                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2420                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2421
2422         /* fake read to flush all prev. writes */
2423         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2424
2425         return 0;
2426 }
2427
2428 /*
2429  * HCMD utils
2430  */
2431 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2432 {
2433         switch (cmd_id) {
2434         case REPLY_RXON:
2435                 return sizeof(struct iwl3945_rxon_cmd);
2436         case POWER_TABLE_CMD:
2437                 return sizeof(struct iwl3945_powertable_cmd);
2438         default:
2439                 return len;
2440         }
2441 }
2442
2443
2444 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2445 {
2446         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2447         addsta->mode = cmd->mode;
2448         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2449         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2450         addsta->station_flags = cmd->station_flags;
2451         addsta->station_flags_msk = cmd->station_flags_msk;
2452         addsta->tid_disable_tx = cpu_to_le16(0);
2453         addsta->rate_n_flags = cmd->rate_n_flags;
2454         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2455         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2456         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2457
2458         return (u16)sizeof(struct iwl3945_addsta_cmd);
2459 }
2460
2461
2462 /**
2463  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2464  */
2465 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2466 {
2467         int rc, i, index, prev_index;
2468         struct iwl3945_rate_scaling_cmd rate_cmd = {
2469                 .reserved = {0, 0, 0},
2470         };
2471         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2472
2473         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2474                 index = iwl3945_rates[i].table_rs_index;
2475
2476                 table[index].rate_n_flags =
2477                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2478                 table[index].try_cnt = priv->retry_rate;
2479                 prev_index = iwl3945_get_prev_ieee_rate(i);
2480                 table[index].next_rate_index =
2481                                 iwl3945_rates[prev_index].table_rs_index;
2482         }
2483
2484         switch (priv->band) {
2485         case IEEE80211_BAND_5GHZ:
2486                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2487                 /* If one of the following CCK rates is used,
2488                  * have it fall back to the 6M OFDM rate */
2489                 for (i = IWL_RATE_1M_INDEX_TABLE;
2490                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2491                         table[i].next_rate_index =
2492                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2493
2494                 /* Don't fall back to CCK rates */
2495                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2496                                                 IWL_RATE_9M_INDEX_TABLE;
2497
2498                 /* Don't drop out of OFDM rates */
2499                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2500                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2501                 break;
2502
2503         case IEEE80211_BAND_2GHZ:
2504                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2505                 /* If an OFDM rate is used, have it fall back to the
2506                  * 1M CCK rates */
2507
2508                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2509                     iwl_is_associated(priv)) {
2510
2511                         index = IWL_FIRST_CCK_RATE;
2512                         for (i = IWL_RATE_6M_INDEX_TABLE;
2513                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2514                                 table[i].next_rate_index =
2515                                         iwl3945_rates[index].table_rs_index;
2516
2517                         index = IWL_RATE_11M_INDEX_TABLE;
2518                         /* CCK shouldn't fall back to OFDM... */
2519                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2520                 }
2521                 break;
2522
2523         default:
2524                 WARN_ON(1);
2525                 break;
2526         }
2527
2528         /* Update the rate scaling for control frame Tx */
2529         rate_cmd.table_id = 0;
2530         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2531                               &rate_cmd);
2532         if (rc)
2533                 return rc;
2534
2535         /* Update the rate scaling for data frame Tx */
2536         rate_cmd.table_id = 1;
2537         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2538                                 &rate_cmd);
2539 }
2540
2541 /* Called when initializing driver */
2542 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2543 {
2544         memset((void *)&priv->hw_params, 0,
2545                sizeof(struct iwl_hw_params));
2546
2547         priv->shared_virt =
2548             pci_alloc_consistent(priv->pci_dev,
2549                                  sizeof(struct iwl3945_shared),
2550                                  &priv->shared_phys);
2551
2552         if (!priv->shared_virt) {
2553                 IWL_ERR(priv, "failed to allocate pci memory\n");
2554                 mutex_unlock(&priv->mutex);
2555                 return -ENOMEM;
2556         }
2557
2558         /* Assign number of Usable TX queues */
2559         priv->hw_params.max_txq_num = IWL39_NUM_QUEUES;
2560
2561         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2562         priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2563         priv->hw_params.max_pkt_size = 2342;
2564         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2565         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2566         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2567         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2568
2569         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2570         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2571
2572         return 0;
2573 }
2574
2575 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2576                           struct iwl3945_frame *frame, u8 rate)
2577 {
2578         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2579         unsigned int frame_size;
2580
2581         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2582         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2583
2584         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2585         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2586
2587         frame_size = iwl3945_fill_beacon_frame(priv,
2588                                 tx_beacon_cmd->frame,
2589                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2590
2591         BUG_ON(frame_size > MAX_MPDU_SIZE);
2592         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2593
2594         tx_beacon_cmd->tx.rate = rate;
2595         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2596                                       TX_CMD_FLG_TSF_MSK);
2597
2598         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2599         tx_beacon_cmd->tx.supp_rates[0] =
2600                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2601
2602         tx_beacon_cmd->tx.supp_rates[1] =
2603                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2604
2605         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2606 }
2607
2608 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2609 {
2610         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2611         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2612 }
2613
2614 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2615 {
2616         INIT_DELAYED_WORK(&priv->thermal_periodic,
2617                           iwl3945_bg_reg_txpower_periodic);
2618 }
2619
2620 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2621 {
2622         cancel_delayed_work(&priv->thermal_periodic);
2623 }
2624
2625 /* check contents of special bootstrap uCode SRAM */
2626 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2627  {
2628         __le32 *image = priv->ucode_boot.v_addr;
2629         u32 len = priv->ucode_boot.len;
2630         u32 reg;
2631         u32 val;
2632
2633         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2634
2635         /* verify BSM SRAM contents */
2636         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2637         for (reg = BSM_SRAM_LOWER_BOUND;
2638              reg < BSM_SRAM_LOWER_BOUND + len;
2639              reg += sizeof(u32), image++) {
2640                 val = iwl_read_prph(priv, reg);
2641                 if (val != le32_to_cpu(*image)) {
2642                         IWL_ERR(priv, "BSM uCode verification failed at "
2643                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2644                                   BSM_SRAM_LOWER_BOUND,
2645                                   reg - BSM_SRAM_LOWER_BOUND, len,
2646                                   val, le32_to_cpu(*image));
2647                         return -EIO;
2648                 }
2649         }
2650
2651         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2652
2653         return 0;
2654 }
2655
2656
2657 /******************************************************************************
2658  *
2659  * EEPROM related functions
2660  *
2661  ******************************************************************************/
2662
2663 /*
2664  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2665  * embedded controller) as EEPROM reader; each read is a series of pulses
2666  * to/from the EEPROM chip, not a single event, so even reads could conflict
2667  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2668  * simply claims ownership, which should be safe when this function is called
2669  * (i.e. before loading uCode!).
2670  */
2671 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2672 {
2673         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2674         return 0;
2675 }
2676
2677
2678 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2679 {
2680         return;
2681 }
2682
2683  /**
2684   * iwl3945_load_bsm - Load bootstrap instructions
2685   *
2686   * BSM operation:
2687   *
2688   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2689   * in special SRAM that does not power down during RFKILL.  When powering back
2690   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2691   * the bootstrap program into the on-board processor, and starts it.
2692   *
2693   * The bootstrap program loads (via DMA) instructions and data for a new
2694   * program from host DRAM locations indicated by the host driver in the
2695   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2696   * automatically.
2697   *
2698   * When initializing the NIC, the host driver points the BSM to the
2699   * "initialize" uCode image.  This uCode sets up some internal data, then
2700   * notifies host via "initialize alive" that it is complete.
2701   *
2702   * The host then replaces the BSM_DRAM_* pointer values to point to the
2703   * normal runtime uCode instructions and a backup uCode data cache buffer
2704   * (filled initially with starting data values for the on-board processor),
2705   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2706   * which begins normal operation.
2707   *
2708   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2709   * the backup data cache in DRAM before SRAM is powered down.
2710   *
2711   * When powering back up, the BSM loads the bootstrap program.  This reloads
2712   * the runtime uCode instructions and the backup data cache into SRAM,
2713   * and re-launches the runtime uCode from where it left off.
2714   */
2715 static int iwl3945_load_bsm(struct iwl_priv *priv)
2716 {
2717         __le32 *image = priv->ucode_boot.v_addr;
2718         u32 len = priv->ucode_boot.len;
2719         dma_addr_t pinst;
2720         dma_addr_t pdata;
2721         u32 inst_len;
2722         u32 data_len;
2723         int rc;
2724         int i;
2725         u32 done;
2726         u32 reg_offset;
2727
2728         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2729
2730         /* make sure bootstrap program is no larger than BSM's SRAM size */
2731         if (len > IWL39_MAX_BSM_SIZE)
2732                 return -EINVAL;
2733
2734         /* Tell bootstrap uCode where to find the "Initialize" uCode
2735         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2736         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2737         *        after the "initialize" uCode has run, to point to
2738         *        runtime/protocol instructions and backup data cache. */
2739         pinst = priv->ucode_init.p_addr;
2740         pdata = priv->ucode_init_data.p_addr;
2741         inst_len = priv->ucode_init.len;
2742         data_len = priv->ucode_init_data.len;
2743
2744         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2745         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2746         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2747         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2748
2749         /* Fill BSM memory with bootstrap instructions */
2750         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2751              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2752              reg_offset += sizeof(u32), image++)
2753                 _iwl_write_prph(priv, reg_offset,
2754                                           le32_to_cpu(*image));
2755
2756         rc = iwl3945_verify_bsm(priv);
2757         if (rc)
2758                 return rc;
2759
2760         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2761         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2762         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2763                                  IWL39_RTC_INST_LOWER_BOUND);
2764         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2765
2766         /* Load bootstrap code into instruction SRAM now,
2767          *   to prepare to load "initialize" uCode */
2768         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2769                 BSM_WR_CTRL_REG_BIT_START);
2770
2771         /* Wait for load of bootstrap uCode to finish */
2772         for (i = 0; i < 100; i++) {
2773                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2774                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2775                         break;
2776                 udelay(10);
2777         }
2778         if (i < 100)
2779                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2780         else {
2781                 IWL_ERR(priv, "BSM write did not complete!\n");
2782                 return -EIO;
2783         }
2784
2785         /* Enable future boot loads whenever power management unit triggers it
2786          *   (e.g. when powering back up after power-save shutdown) */
2787         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2788                 BSM_WR_CTRL_REG_BIT_START_EN);
2789
2790         return 0;
2791 }
2792
2793 #define IWL3945_UCODE_GET(item)                                         \
2794 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2795                                     u32 api_ver)                        \
2796 {                                                                       \
2797         return le32_to_cpu(ucode->u.v1.item);                           \
2798 }
2799
2800 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2801 {
2802         return UCODE_HEADER_SIZE(1);
2803 }
2804 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2805                                    u32 api_ver)
2806 {
2807         return 0;
2808 }
2809 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2810                                   u32 api_ver)
2811 {
2812         return (u8 *) ucode->u.v1.data;
2813 }
2814
2815 IWL3945_UCODE_GET(inst_size);
2816 IWL3945_UCODE_GET(data_size);
2817 IWL3945_UCODE_GET(init_size);
2818 IWL3945_UCODE_GET(init_data_size);
2819 IWL3945_UCODE_GET(boot_size);
2820
2821 static struct iwl_hcmd_ops iwl3945_hcmd = {
2822         .rxon_assoc = iwl3945_send_rxon_assoc,
2823         .commit_rxon = iwl3945_commit_rxon,
2824 };
2825
2826 static struct iwl_ucode_ops iwl3945_ucode = {
2827         .get_header_size = iwl3945_ucode_get_header_size,
2828         .get_build = iwl3945_ucode_get_build,
2829         .get_inst_size = iwl3945_ucode_get_inst_size,
2830         .get_data_size = iwl3945_ucode_get_data_size,
2831         .get_init_size = iwl3945_ucode_get_init_size,
2832         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2833         .get_boot_size = iwl3945_ucode_get_boot_size,
2834         .get_data = iwl3945_ucode_get_data,
2835 };
2836
2837 static struct iwl_lib_ops iwl3945_lib = {
2838         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2839         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2840         .txq_init = iwl3945_hw_tx_queue_init,
2841         .load_ucode = iwl3945_load_bsm,
2842         .apm_ops = {
2843                 .init = iwl3945_apm_init,
2844                 .reset = iwl3945_apm_reset,
2845                 .stop = iwl3945_apm_stop,
2846                 .config = iwl3945_nic_config,
2847                 .set_pwr_src = iwl3945_set_pwr_src,
2848         },
2849         .eeprom_ops = {
2850                 .regulatory_bands = {
2851                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2852                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2853                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2854                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2855                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2856                         EEPROM_REGULATORY_BAND_NO_HT40,
2857                         EEPROM_REGULATORY_BAND_NO_HT40,
2858                 },
2859                 .verify_signature  = iwlcore_eeprom_verify_signature,
2860                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2861                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2862                 .query_addr = iwlcore_eeprom_query_addr,
2863         },
2864         .send_tx_power  = iwl3945_send_tx_power,
2865         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2866         .post_associate = iwl3945_post_associate,
2867         .isr = iwl_isr_legacy,
2868         .config_ap = iwl3945_config_ap,
2869 };
2870
2871 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2872         .get_hcmd_size = iwl3945_get_hcmd_size,
2873         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2874 };
2875
2876 static struct iwl_ops iwl3945_ops = {
2877         .ucode = &iwl3945_ucode,
2878         .lib = &iwl3945_lib,
2879         .hcmd = &iwl3945_hcmd,
2880         .utils = &iwl3945_hcmd_utils,
2881 };
2882
2883 static struct iwl_cfg iwl3945_bg_cfg = {
2884         .name = "3945BG",
2885         .fw_name_pre = IWL3945_FW_PRE,
2886         .ucode_api_max = IWL3945_UCODE_API_MAX,
2887         .ucode_api_min = IWL3945_UCODE_API_MIN,
2888         .sku = IWL_SKU_G,
2889         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2890         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2891         .ops = &iwl3945_ops,
2892         .mod_params = &iwl3945_mod_params,
2893         .use_isr_legacy = true,
2894         .ht_greenfield_support = false,
2895 };
2896
2897 static struct iwl_cfg iwl3945_abg_cfg = {
2898         .name = "3945ABG",
2899         .fw_name_pre = IWL3945_FW_PRE,
2900         .ucode_api_max = IWL3945_UCODE_API_MAX,
2901         .ucode_api_min = IWL3945_UCODE_API_MIN,
2902         .sku = IWL_SKU_A|IWL_SKU_G,
2903         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2904         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2905         .ops = &iwl3945_ops,
2906         .mod_params = &iwl3945_mod_params,
2907         .use_isr_legacy = true,
2908         .ht_greenfield_support = false,
2909 };
2910
2911 struct pci_device_id iwl3945_hw_card_ids[] = {
2912         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2913         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2914         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2915         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2916         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2917         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2918         {0}
2919 };
2920
2921 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);