drivers/net/wireless/b43legacy/main.c

   1 /*
   2  *
   3  *  Broadcom B43legacy wireless driver
   4  *
   5  *  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6  *  Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
   7  *  Copyright (c) 2005, 2006 Michael Buesch <m@bues.ch>
   8  *  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9  *  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10  *  Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
  11  *
  12  *  Some parts of the code in this file are derived from the ipw2200
  13  *  driver  Copyright(c) 2003 - 2004 Intel Corporation.
  14
  15  *  This program is free software; you can redistribute it and/or modify
  16  *  it under the terms of the GNU General Public License as published by
  17  *  the Free Software Foundation; either version 2 of the License, or
  18  *  (at your option) any later version.
  19  *
  20  *  This program is distributed in the hope that it will be useful,
  21  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *  GNU General Public License for more details.
  24  *
  25  *  You should have received a copy of the GNU General Public License
  26  *  along with this program; see the file COPYING.  If not, write to
  27  *  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  28  *  Boston, MA 02110-1301, USA.
  29  *
  30  */
  31
  32 #include <linux/delay.h>
  33 #include <linux/init.h>
  34 #include <linux/module.h>
  35 #include <linux/if_arp.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/firmware.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/sched.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <linux/slab.h>
  43 #include <net/dst.h>
  44 #include <asm/unaligned.h>
  45
  46 #include "b43legacy.h"
  47 #include "main.h"
  48 #include "debugfs.h"
  49 #include "phy.h"
  50 #include "dma.h"
  51 #include "pio.h"
  52 #include "sysfs.h"
  53 #include "xmit.h"
  54 #include "radio.h"
  55
  56
  57 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
  58 MODULE_AUTHOR("Martin Langer");
  59 MODULE_AUTHOR("Stefano Brivio");
  60 MODULE_AUTHOR("Michael Buesch");
  61 MODULE_LICENSE("GPL");
  62
  63 MODULE_FIRMWARE("b43legacy/ucode2.fw");
  64 MODULE_FIRMWARE("b43legacy/ucode4.fw");
  65
  66 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  67 static int modparam_pio;
  68 module_param_named(pio, modparam_pio, int, 0444);
  69 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  70 #elif defined(CONFIG_B43LEGACY_DMA)
  71 # define modparam_pio   0
  72 #elif defined(CONFIG_B43LEGACY_PIO)
  73 # define modparam_pio   1
  74 #endif
  75
  76 static int modparam_bad_frames_preempt;
  77 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  78 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
  79                  " Preemption");
  80
  81 static char modparam_fwpostfix[16];
  82 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  83 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
  84
  85 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
  86 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
  87         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
  88         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
  89         SSB_DEVTABLE_END
  90 };
  91 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
  92
  93
  94 /* Channel and ratetables are shared for all devices.
  95  * They can't be const, because ieee80211 puts some precalculated
  96  * data in there. This data is the same for all devices, so we don't
  97  * get concurrency issues */
  98 #define RATETAB_ENT(_rateid, _flags) \
  99         {                                                               \
 100                 .bitrate        = B43legacy_RATE_TO_100KBPS(_rateid),   \
 101                 .hw_value       = (_rateid),                            \
 102                 .flags          = (_flags),                             \
 103         }
 104 /*
 105  * NOTE: When changing this, sync with xmit.c's
 106  *       b43legacy_plcp_get_bitrate_idx_* functions!
 107  */
 108 static struct ieee80211_rate __b43legacy_ratetable[] = {
 109         RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
 110         RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
 111         RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
 112         RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
 113         RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
 114         RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
 115         RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
 116         RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
 117         RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
 118         RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
 119         RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
 120         RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
 121 };
 122 #define b43legacy_b_ratetable           (__b43legacy_ratetable + 0)
 123 #define b43legacy_b_ratetable_size      4
 124 #define b43legacy_g_ratetable           (__b43legacy_ratetable + 0)
 125 #define b43legacy_g_ratetable_size      12
 126
 127 #define CHANTAB_ENT(_chanid, _freq) \
 128         {                                                       \
 129                 .center_freq    = (_freq),                      \
 130                 .hw_value       = (_chanid),                    \
 131         }
 132 static struct ieee80211_channel b43legacy_bg_chantable[] = {
 133         CHANTAB_ENT(1, 2412),
 134         CHANTAB_ENT(2, 2417),
 135         CHANTAB_ENT(3, 2422),
 136         CHANTAB_ENT(4, 2427),
 137         CHANTAB_ENT(5, 2432),
 138         CHANTAB_ENT(6, 2437),
 139         CHANTAB_ENT(7, 2442),
 140         CHANTAB_ENT(8, 2447),
 141         CHANTAB_ENT(9, 2452),
 142         CHANTAB_ENT(10, 2457),
 143         CHANTAB_ENT(11, 2462),
 144         CHANTAB_ENT(12, 2467),
 145         CHANTAB_ENT(13, 2472),
 146         CHANTAB_ENT(14, 2484),
 147 };
 148
 149 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
 150         .channels = b43legacy_bg_chantable,
 151         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
 152         .bitrates = b43legacy_b_ratetable,
 153         .n_bitrates = b43legacy_b_ratetable_size,
 154 };
 155
 156 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
 157         .channels = b43legacy_bg_chantable,
 158         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
 159         .bitrates = b43legacy_g_ratetable,
 160         .n_bitrates = b43legacy_g_ratetable_size,
 161 };
 162
 163 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
 164 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
 165 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
 166 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
 167
 168
 169 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
 170 {
 171         if (!wl || !wl->current_dev)
 172                 return 1;
 173         if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
 174                 return 1;
 175         /* We are up and running.
 176          * Ratelimit the messages to avoid DoS over the net. */
 177         return net_ratelimit();
 178 }
 179
 180 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
 181 {
 182         struct va_format vaf;
 183         va_list args;
 184
 185         if (!b43legacy_ratelimit(wl))
 186                 return;
 187
 188         va_start(args, fmt);
 189
 190         vaf.fmt = fmt;
 191         vaf.va = &args;
 192
 193         printk(KERN_INFO "b43legacy-%s: %pV",
 194                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 195
 196         va_end(args);
 197 }
 198
 199 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
 200 {
 201         struct va_format vaf;
 202         va_list args;
 203
 204         if (!b43legacy_ratelimit(wl))
 205                 return;
 206
 207         va_start(args, fmt);
 208
 209         vaf.fmt = fmt;
 210         vaf.va = &args;
 211
 212         printk(KERN_ERR "b43legacy-%s ERROR: %pV",
 213                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 214
 215         va_end(args);
 216 }
 217
 218 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
 219 {
 220         struct va_format vaf;
 221         va_list args;
 222
 223         if (!b43legacy_ratelimit(wl))
 224                 return;
 225
 226         va_start(args, fmt);
 227
 228         vaf.fmt = fmt;
 229         vaf.va = &args;
 230
 231         printk(KERN_WARNING "b43legacy-%s warning: %pV",
 232                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 233
 234         va_end(args);
 235 }
 236
 237 #if B43legacy_DEBUG
 238 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
 239 {
 240         struct va_format vaf;
 241         va_list args;
 242
 243         va_start(args, fmt);
 244
 245         vaf.fmt = fmt;
 246         vaf.va = &args;
 247
 248         printk(KERN_DEBUG "b43legacy-%s debug: %pV",
 249                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan", &vaf);
 250
 251         va_end(args);
 252 }
 253 #endif /* DEBUG */
 254
 255 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
 256                                 u32 val)
 257 {
 258         u32 status;
 259
 260         B43legacy_WARN_ON(offset % 4 != 0);
 261
 262         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 263         if (status & B43legacy_MACCTL_BE)
 264                 val = swab32(val);
 265
 266         b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
 267         mmiowb();
 268         b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
 269 }
 270
 271 static inline
 272 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
 273                                 u16 routing, u16 offset)
 274 {
 275         u32 control;
 276
 277         /* "offset" is the WORD offset. */
 278
 279         control = routing;
 280         control <<= 16;
 281         control |= offset;
 282         b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
 283 }
 284
 285 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
 286                        u16 routing, u16 offset)
 287 {
 288         u32 ret;
 289
 290         if (routing == B43legacy_SHM_SHARED) {
 291                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 292                 if (offset & 0x0003) {
 293                         /* Unaligned access */
 294                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 295                         ret = b43legacy_read16(dev,
 296                                 B43legacy_MMIO_SHM_DATA_UNALIGNED);
 297                         ret <<= 16;
 298                         b43legacy_shm_control_word(dev, routing,
 299                                                      (offset >> 2) + 1);
 300                         ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
 301
 302                         return ret;
 303                 }
 304                 offset >>= 2;
 305         }
 306         b43legacy_shm_control_word(dev, routing, offset);
 307         ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
 308
 309         return ret;
 310 }
 311
 312 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
 313                            u16 routing, u16 offset)
 314 {
 315         u16 ret;
 316
 317         if (routing == B43legacy_SHM_SHARED) {
 318                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 319                 if (offset & 0x0003) {
 320                         /* Unaligned access */
 321                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 322                         ret = b43legacy_read16(dev,
 323                                              B43legacy_MMIO_SHM_DATA_UNALIGNED);
 324
 325                         return ret;
 326                 }
 327                 offset >>= 2;
 328         }
 329         b43legacy_shm_control_word(dev, routing, offset);
 330         ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
 331
 332         return ret;
 333 }
 334
 335 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
 336                            u16 routing, u16 offset,
 337                            u32 value)
 338 {
 339         if (routing == B43legacy_SHM_SHARED) {
 340                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 341                 if (offset & 0x0003) {
 342                         /* Unaligned access */
 343                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 344                         mmiowb();
 345                         b43legacy_write16(dev,
 346                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
 347                                           (value >> 16) & 0xffff);
 348                         mmiowb();
 349                         b43legacy_shm_control_word(dev, routing,
 350                                                    (offset >> 2) + 1);
 351                         mmiowb();
 352                         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
 353                                           value & 0xffff);
 354                         return;
 355                 }
 356                 offset >>= 2;
 357         }
 358         b43legacy_shm_control_word(dev, routing, offset);
 359         mmiowb();
 360         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
 361 }
 362
 363 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
 364                            u16 value)
 365 {
 366         if (routing == B43legacy_SHM_SHARED) {
 367                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 368                 if (offset & 0x0003) {
 369                         /* Unaligned access */
 370                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 371                         mmiowb();
 372                         b43legacy_write16(dev,
 373                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
 374                                           value);
 375                         return;
 376                 }
 377                 offset >>= 2;
 378         }
 379         b43legacy_shm_control_word(dev, routing, offset);
 380         mmiowb();
 381         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
 382 }
 383
 384 /* Read HostFlags */
 385 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
 386 {
 387         u32 ret;
 388
 389         ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 390                                    B43legacy_SHM_SH_HOSTFHI);
 391         ret <<= 16;
 392         ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 393                                     B43legacy_SHM_SH_HOSTFLO);
 394
 395         return ret;
 396 }
 397
 398 /* Write HostFlags */
 399 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
 400 {
 401         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
 402                               B43legacy_SHM_SH_HOSTFLO,
 403                               (value & 0x0000FFFF));
 404         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
 405                               B43legacy_SHM_SH_HOSTFHI,
 406                               ((value & 0xFFFF0000) >> 16));
 407 }
 408
 409 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
 410 {
 411         /* We need to be careful. As we read the TSF from multiple
 412          * registers, we should take care of register overflows.
 413          * In theory, the whole tsf read process should be atomic.
 414          * We try to be atomic here, by restaring the read process,
 415          * if any of the high registers changed (overflew).
 416          */
 417         if (dev->dev->id.revision >= 3) {
 418                 u32 low;
 419                 u32 high;
 420                 u32 high2;
 421
 422                 do {
 423                         high = b43legacy_read32(dev,
 424                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
 425                         low = b43legacy_read32(dev,
 426                                         B43legacy_MMIO_REV3PLUS_TSF_LOW);
 427                         high2 = b43legacy_read32(dev,
 428                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
 429                 } while (unlikely(high != high2));
 430
 431                 *tsf = high;
 432                 *tsf <<= 32;
 433                 *tsf |= low;
 434         } else {
 435                 u64 tmp;
 436                 u16 v0;
 437                 u16 v1;
 438                 u16 v2;
 439                 u16 v3;
 440                 u16 test1;
 441                 u16 test2;
 442                 u16 test3;
 443
 444                 do {
 445                         v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
 446                         v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
 447                         v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
 448                         v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
 449
 450                         test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
 451                         test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
 452                         test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
 453                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 454
 455                 *tsf = v3;
 456                 *tsf <<= 48;
 457                 tmp = v2;
 458                 tmp <<= 32;
 459                 *tsf |= tmp;
 460                 tmp = v1;
 461                 tmp <<= 16;
 462                 *tsf |= tmp;
 463                 *tsf |= v0;
 464         }
 465 }
 466
 467 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
 468 {
 469         u32 status;
 470
 471         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 472         status |= B43legacy_MACCTL_TBTTHOLD;
 473         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
 474         mmiowb();
 475 }
 476
 477 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
 478 {
 479         u32 status;
 480
 481         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 482         status &= ~B43legacy_MACCTL_TBTTHOLD;
 483         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
 484 }
 485
 486 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
 487 {
 488         /* Be careful with the in-progress timer.
 489          * First zero out the low register, so we have a full
 490          * register-overflow duration to complete the operation.
 491          */
 492         if (dev->dev->id.revision >= 3) {
 493                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 494                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 495
 496                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
 497                 mmiowb();
 498                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
 499                                     hi);
 500                 mmiowb();
 501                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
 502                                     lo);
 503         } else {
 504                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 505                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 506                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 507                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 508
 509                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
 510                 mmiowb();
 511                 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
 512                 mmiowb();
 513                 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
 514                 mmiowb();
 515                 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
 516                 mmiowb();
 517                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
 518         }
 519 }
 520
 521 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
 522 {
 523         b43legacy_time_lock(dev);
 524         b43legacy_tsf_write_locked(dev, tsf);
 525         b43legacy_time_unlock(dev);
 526 }
 527
 528 static
 529 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
 530                              u16 offset, const u8 *mac)
 531 {
 532         static const u8 zero_addr[ETH_ALEN] = { 0 };
 533         u16 data;
 534
 535         if (!mac)
 536                 mac = zero_addr;
 537
 538         offset |= 0x0020;
 539         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
 540
 541         data = mac[0];
 542         data |= mac[1] << 8;
 543         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
 544         data = mac[2];
 545         data |= mac[3] << 8;
 546         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
 547         data = mac[4];
 548         data |= mac[5] << 8;
 549         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
 550 }
 551
 552 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
 553 {
 554         static const u8 zero_addr[ETH_ALEN] = { 0 };
 555         const u8 *mac = dev->wl->mac_addr;
 556         const u8 *bssid = dev->wl->bssid;
 557         u8 mac_bssid[ETH_ALEN * 2];
 558         int i;
 559         u32 tmp;
 560
 561         if (!bssid)
 562                 bssid = zero_addr;
 563         if (!mac)
 564                 mac = zero_addr;
 565
 566         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
 567
 568         memcpy(mac_bssid, mac, ETH_ALEN);
 569         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 570
 571         /* Write our MAC address and BSSID to template ram */
 572         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 573                 tmp =  (u32)(mac_bssid[i + 0]);
 574                 tmp |= (u32)(mac_bssid[i + 1]) << 8;
 575                 tmp |= (u32)(mac_bssid[i + 2]) << 16;
 576                 tmp |= (u32)(mac_bssid[i + 3]) << 24;
 577                 b43legacy_ram_write(dev, 0x20 + i, tmp);
 578                 b43legacy_ram_write(dev, 0x78 + i, tmp);
 579                 b43legacy_ram_write(dev, 0x478 + i, tmp);
 580         }
 581 }
 582
 583 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
 584 {
 585         b43legacy_write_mac_bssid_templates(dev);
 586         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
 587                                 dev->wl->mac_addr);
 588 }
 589
 590 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
 591                                     u16 slot_time)
 592 {
 593         /* slot_time is in usec. */
 594         if (dev->phy.type != B43legacy_PHYTYPE_G)
 595                 return;
 596         b43legacy_write16(dev, 0x684, 510 + slot_time);
 597         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
 598                               slot_time);
 599 }
 600
 601 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
 602 {
 603         b43legacy_set_slot_time(dev, 9);
 604 }
 605
 606 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
 607 {
 608         b43legacy_set_slot_time(dev, 20);
 609 }
 610
 611 /* Synchronize IRQ top- and bottom-half.
 612  * IRQs must be masked before calling this.
 613  * This must not be called with the irq_lock held.
 614  */
 615 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
 616 {
 617         synchronize_irq(dev->dev->irq);
 618         tasklet_kill(&dev->isr_tasklet);
 619 }
 620
 621 /* DummyTransmission function, as documented on
 622  * http://bcm-specs.sipsolutions.net/DummyTransmission
 623  */
 624 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
 625 {
 626         struct b43legacy_phy *phy = &dev->phy;
 627         unsigned int i;
 628         unsigned int max_loop;
 629         u16 value;
 630         u32 buffer[5] = {
 631                 0x00000000,
 632                 0x00D40000,
 633                 0x00000000,
 634                 0x01000000,
 635                 0x00000000,
 636         };
 637
 638         switch (phy->type) {
 639         case B43legacy_PHYTYPE_B:
 640         case B43legacy_PHYTYPE_G:
 641                 max_loop = 0xFA;
 642                 buffer[0] = 0x000B846E;
 643                 break;
 644         default:
 645                 B43legacy_BUG_ON(1);
 646                 return;
 647         }
 648
 649         for (i = 0; i < 5; i++)
 650                 b43legacy_ram_write(dev, i * 4, buffer[i]);
 651
 652         /* dummy read follows */
 653         b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 654
 655         b43legacy_write16(dev, 0x0568, 0x0000);
 656         b43legacy_write16(dev, 0x07C0, 0x0000);
 657         b43legacy_write16(dev, 0x050C, 0x0000);
 658         b43legacy_write16(dev, 0x0508, 0x0000);
 659         b43legacy_write16(dev, 0x050A, 0x0000);
 660         b43legacy_write16(dev, 0x054C, 0x0000);
 661         b43legacy_write16(dev, 0x056A, 0x0014);
 662         b43legacy_write16(dev, 0x0568, 0x0826);
 663         b43legacy_write16(dev, 0x0500, 0x0000);
 664         b43legacy_write16(dev, 0x0502, 0x0030);
 665
 666         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 667                 b43legacy_radio_write16(dev, 0x0051, 0x0017);
 668         for (i = 0x00; i < max_loop; i++) {
 669                 value = b43legacy_read16(dev, 0x050E);
 670                 if (value & 0x0080)
 671                         break;
 672                 udelay(10);
 673         }
 674         for (i = 0x00; i < 0x0A; i++) {
 675                 value = b43legacy_read16(dev, 0x050E);
 676                 if (value & 0x0400)
 677                         break;
 678                 udelay(10);
 679         }
 680         for (i = 0x00; i < 0x0A; i++) {
 681                 value = b43legacy_read16(dev, 0x0690);
 682                 if (!(value & 0x0100))
 683                         break;
 684                 udelay(10);
 685         }
 686         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 687                 b43legacy_radio_write16(dev, 0x0051, 0x0037);
 688 }
 689
 690 /* Turn the Analog ON/OFF */
 691 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
 692 {
 693         b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
 694 }
 695
 696 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
 697 {
 698         u32 tmslow;
 699         u32 macctl;
 700
 701         flags |= B43legacy_TMSLOW_PHYCLKEN;
 702         flags |= B43legacy_TMSLOW_PHYRESET;
 703         ssb_device_enable(dev->dev, flags);
 704         msleep(2); /* Wait for the PLL to turn on. */
 705
 706         /* Now take the PHY out of Reset again */
 707         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 708         tmslow |= SSB_TMSLOW_FGC;
 709         tmslow &= ~B43legacy_TMSLOW_PHYRESET;
 710         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 711         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
 712         msleep(1);
 713         tmslow &= ~SSB_TMSLOW_FGC;
 714         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 715         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
 716         msleep(1);
 717
 718         /* Turn Analog ON */
 719         b43legacy_switch_analog(dev, 1);
 720
 721         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 722         macctl &= ~B43legacy_MACCTL_GMODE;
 723         if (flags & B43legacy_TMSLOW_GMODE) {
 724                 macctl |= B43legacy_MACCTL_GMODE;
 725                 dev->phy.gmode = 1;
 726         } else
 727                 dev->phy.gmode = 0;
 728         macctl |= B43legacy_MACCTL_IHR_ENABLED;
 729         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
 730 }
 731
 732 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
 733 {
 734         u32 v0;
 735         u32 v1;
 736         u16 tmp;
 737         struct b43legacy_txstatus stat;
 738
 739         while (1) {
 740                 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
 741                 if (!(v0 & 0x00000001))
 742                         break;
 743                 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
 744
 745                 stat.cookie = (v0 >> 16);
 746                 stat.seq = (v1 & 0x0000FFFF);
 747                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 748                 tmp = (v0 & 0x0000FFFF);
 749                 stat.frame_count = ((tmp & 0xF000) >> 12);
 750                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 751                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 752                 stat.pm_indicated = !!(tmp & 0x0080);
 753                 stat.intermediate = !!(tmp & 0x0040);
 754                 stat.for_ampdu = !!(tmp & 0x0020);
 755                 stat.acked = !!(tmp & 0x0002);
 756
 757                 b43legacy_handle_txstatus(dev, &stat);
 758         }
 759 }
 760
 761 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
 762 {
 763         u32 dummy;
 764
 765         if (dev->dev->id.revision < 5)
 766                 return;
 767         /* Read all entries from the microcode TXstatus FIFO
 768          * and throw them away.
 769          */
 770         while (1) {
 771                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
 772                 if (!(dummy & 0x00000001))
 773                         break;
 774                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
 775         }
 776 }
 777
 778 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
 779 {
 780         u32 val = 0;
 781
 782         val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
 783         val <<= 16;
 784         val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
 785
 786         return val;
 787 }
 788
 789 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
 790 {
 791         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
 792                               (jssi & 0x0000FFFF));
 793         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
 794                               (jssi & 0xFFFF0000) >> 16);
 795 }
 796
 797 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
 798 {
 799         b43legacy_jssi_write(dev, 0x7F7F7F7F);
 800         b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
 801                           b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
 802                           | B43legacy_MACCMD_BGNOISE);
 803         B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
 804                             dev->phy.channel);
 805 }
 806
 807 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
 808 {
 809         /* Top half of Link Quality calculation. */
 810
 811         if (dev->noisecalc.calculation_running)
 812                 return;
 813         dev->noisecalc.channel_at_start = dev->phy.channel;
 814         dev->noisecalc.calculation_running = 1;
 815         dev->noisecalc.nr_samples = 0;
 816
 817         b43legacy_generate_noise_sample(dev);
 818 }
 819
 820 static void handle_irq_noise(struct b43legacy_wldev *dev)
 821 {
 822         struct b43legacy_phy *phy = &dev->phy;
 823         u16 tmp;
 824         u8 noise[4];
 825         u8 i;
 826         u8 j;
 827         s32 average;
 828
 829         /* Bottom half of Link Quality calculation. */
 830
 831         B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
 832         if (dev->noisecalc.channel_at_start != phy->channel)
 833                 goto drop_calculation;
 834         *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
 835         if (noise[0] == 0x7F || noise[1] == 0x7F ||
 836             noise[2] == 0x7F || noise[3] == 0x7F)
 837                 goto generate_new;
 838
 839         /* Get the noise samples. */
 840         B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
 841         i = dev->noisecalc.nr_samples;
 842         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 843         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 844         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 845         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 846         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
 847         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
 848         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
 849         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
 850         dev->noisecalc.nr_samples++;
 851         if (dev->noisecalc.nr_samples == 8) {
 852                 /* Calculate the Link Quality by the noise samples. */
 853                 average = 0;
 854                 for (i = 0; i < 8; i++) {
 855                         for (j = 0; j < 4; j++)
 856                                 average += dev->noisecalc.samples[i][j];
 857                 }
 858                 average /= (8 * 4);
 859                 average *= 125;
 860                 average += 64;
 861                 average /= 128;
 862                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 863                                              0x40C);
 864                 tmp = (tmp / 128) & 0x1F;
 865                 if (tmp >= 8)
 866                         average += 2;
 867                 else
 868                         average -= 25;
 869                 if (tmp == 8)
 870                         average -= 72;
 871                 else
 872                         average -= 48;
 873
 874                 dev->stats.link_noise = average;
 875 drop_calculation:
 876                 dev->noisecalc.calculation_running = 0;
 877                 return;
 878         }
 879 generate_new:
 880         b43legacy_generate_noise_sample(dev);
 881 }
 882
 883 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
 884 {
 885         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
 886                 /* TODO: PS TBTT */
 887         } else {
 888                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
 889                         b43legacy_power_saving_ctl_bits(dev, -1, -1);
 890         }
 891         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
 892                 dev->dfq_valid = 1;
 893 }
 894
 895 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
 896 {
 897         if (dev->dfq_valid) {
 898                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
 899                                   b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
 900                                   | B43legacy_MACCMD_DFQ_VALID);
 901                 dev->dfq_valid = 0;
 902         }
 903 }
 904
 905 static void handle_irq_pmq(struct b43legacy_wldev *dev)
 906 {
 907         u32 tmp;
 908
 909         /* TODO: AP mode. */
 910
 911         while (1) {
 912                 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
 913                 if (!(tmp & 0x00000008))
 914                         break;
 915         }
 916         /* 16bit write is odd, but correct. */
 917         b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
 918 }
 919
 920 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
 921                                             const u8 *data, u16 size,
 922                                             u16 ram_offset,
 923                                             u16 shm_size_offset, u8 rate)
 924 {
 925         u32 i;
 926         u32 tmp;
 927         struct b43legacy_plcp_hdr4 plcp;
 928
 929         plcp.data = 0;
 930         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
 931         b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
 932         ram_offset += sizeof(u32);
 933         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
 934          * So leave the first two bytes of the next write blank.
 935          */
 936         tmp = (u32)(data[0]) << 16;
 937         tmp |= (u32)(data[1]) << 24;
 938         b43legacy_ram_write(dev, ram_offset, tmp);
 939         ram_offset += sizeof(u32);
 940         for (i = 2; i < size; i += sizeof(u32)) {
 941                 tmp = (u32)(data[i + 0]);
 942                 if (i + 1 < size)
 943                         tmp |= (u32)(data[i + 1]) << 8;
 944                 if (i + 2 < size)
 945                         tmp |= (u32)(data[i + 2]) << 16;
 946                 if (i + 3 < size)
 947                         tmp |= (u32)(data[i + 3]) << 24;
 948                 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
 949         }
 950         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
 951                               size + sizeof(struct b43legacy_plcp_hdr6));
 952 }
 953
 954 /* Convert a b43legacy antenna number value to the PHY TX control value. */
 955 static u16 b43legacy_antenna_to_phyctl(int antenna)
 956 {
 957         switch (antenna) {
 958         case B43legacy_ANTENNA0:
 959                 return B43legacy_TX4_PHY_ANT0;
 960         case B43legacy_ANTENNA1:
 961                 return B43legacy_TX4_PHY_ANT1;
 962         }
 963         return B43legacy_TX4_PHY_ANTLAST;
 964 }
 965
 966 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
 967                                             u16 ram_offset,
 968                                             u16 shm_size_offset)
 969 {
 970
 971         unsigned int i, len, variable_len;
 972         const struct ieee80211_mgmt *bcn;
 973         const u8 *ie;
 974         bool tim_found = 0;
 975         unsigned int rate;
 976         u16 ctl;
 977         int antenna;
 978         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
 979
 980         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
 981         len = min((size_t)dev->wl->current_beacon->len,
 982                   0x200 - sizeof(struct b43legacy_plcp_hdr6));
 983         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
 984
 985         b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
 986                                         shm_size_offset, rate);
 987
 988         /* Write the PHY TX control parameters. */
 989         antenna = B43legacy_ANTENNA_DEFAULT;
 990         antenna = b43legacy_antenna_to_phyctl(antenna);
 991         ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 992                                    B43legacy_SHM_SH_BEACPHYCTL);
 993         /* We can't send beacons with short preamble. Would get PHY errors. */
 994         ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
 995         ctl &= ~B43legacy_TX4_PHY_ANT;
 996         ctl &= ~B43legacy_TX4_PHY_ENC;
 997         ctl |= antenna;
 998         ctl |= B43legacy_TX4_PHY_ENC_CCK;
 999         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1000                               B43legacy_SHM_SH_BEACPHYCTL, ctl);
1001
1002         /* Find the position of the TIM and the DTIM_period value
1003          * and write them to SHM. */
1004         ie = bcn->u.beacon.variable;
1005         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1006         for (i = 0; i < variable_len - 2; ) {
1007                 uint8_t ie_id, ie_len;
1008
1009                 ie_id = ie[i];
1010                 ie_len = ie[i + 1];
1011                 if (ie_id == 5) {
1012                         u16 tim_position;
1013                         u16 dtim_period;
1014                         /* This is the TIM Information Element */
1015
1016                         /* Check whether the ie_len is in the beacon data range. */
1017                         if (variable_len < ie_len + 2 + i)
1018                                 break;
1019                         /* A valid TIM is at least 4 bytes long. */
1020                         if (ie_len < 4)
1021                                 break;
1022                         tim_found = 1;
1023
1024                         tim_position = sizeof(struct b43legacy_plcp_hdr6);
1025                         tim_position += offsetof(struct ieee80211_mgmt,
1026                                                  u.beacon.variable);
1027                         tim_position += i;
1028
1029                         dtim_period = ie[i + 3];
1030
1031                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1032                                         B43legacy_SHM_SH_TIMPOS, tim_position);
1033                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1034                                         B43legacy_SHM_SH_DTIMP, dtim_period);
1035                         break;
1036                 }
1037                 i += ie_len + 2;
1038         }
1039         if (!tim_found) {
1040                 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1041                               "beacon template packet. AP or IBSS operation "
1042                               "may be broken.\n");
1043         } else
1044                 b43legacydbg(dev->wl, "Updated beacon template\n");
1045 }
1046
1047 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1048                                             u16 shm_offset, u16 size,
1049                                             struct ieee80211_rate *rate)
1050 {
1051         struct b43legacy_plcp_hdr4 plcp;
1052         u32 tmp;
1053         __le16 dur;
1054
1055         plcp.data = 0;
1056         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1057         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1058                                                dev->wl->vif,
1059                                                size,
1060                                                rate);
1061         /* Write PLCP in two parts and timing for packet transfer */
1062         tmp = le32_to_cpu(plcp.data);
1063         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1064                               tmp & 0xFFFF);
1065         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1066                               tmp >> 16);
1067         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1068                               le16_to_cpu(dur));
1069 }
1070
1071 /* Instead of using custom probe response template, this function
1072  * just patches custom beacon template by:
1073  * 1) Changing packet type
1074  * 2) Patching duration field
1075  * 3) Stripping TIM
1076  */
1077 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1078                                                u16 *dest_size,
1079                                                struct ieee80211_rate *rate)
1080 {
1081         const u8 *src_data;
1082         u8 *dest_data;
1083         u16 src_size, elem_size, src_pos, dest_pos;
1084         __le16 dur;
1085         struct ieee80211_hdr *hdr;
1086         size_t ie_start;
1087
1088         src_size = dev->wl->current_beacon->len;
1089         src_data = (const u8 *)dev->wl->current_beacon->data;
1090
1091         /* Get the start offset of the variable IEs in the packet. */
1092         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1093         B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1094                                                u.beacon.variable));
1095
1096         if (B43legacy_WARN_ON(src_size < ie_start))
1097                 return NULL;
1098
1099         dest_data = kmalloc(src_size, GFP_ATOMIC);
1100         if (unlikely(!dest_data))
1101                 return NULL;
1102
1103         /* Copy the static data and all Information Elements, except the TIM. */
1104         memcpy(dest_data, src_data, ie_start);
1105         src_pos = ie_start;
1106         dest_pos = ie_start;
1107         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1108                 elem_size = src_data[src_pos + 1] + 2;
1109                 if (src_data[src_pos] == 5) {
1110                         /* This is the TIM. */
1111                         continue;
1112                 }
1113                 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1114                 dest_pos += elem_size;
1115         }
1116         *dest_size = dest_pos;
1117         hdr = (struct ieee80211_hdr *)dest_data;
1118
1119         /* Set the frame control. */
1120         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1121                                          IEEE80211_STYPE_PROBE_RESP);
1122         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1123                                                dev->wl->vif,
1124                                                *dest_size,
1125                                                rate);
1126         hdr->duration_id = dur;
1127
1128         return dest_data;
1129 }
1130
1131 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1132                                                 u16 ram_offset,
1133                                                 u16 shm_size_offset,
1134                                                 struct ieee80211_rate *rate)
1135 {
1136         const u8 *probe_resp_data;
1137         u16 size;
1138
1139         size = dev->wl->current_beacon->len;
1140         probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1141         if (unlikely(!probe_resp_data))
1142                 return;
1143
1144         /* Looks like PLCP headers plus packet timings are stored for
1145          * all possible basic rates
1146          */
1147         b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1148                                         &b43legacy_b_ratetable[0]);
1149         b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1150                                         &b43legacy_b_ratetable[1]);
1151         b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1152                                         &b43legacy_b_ratetable[2]);
1153         b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1154                                         &b43legacy_b_ratetable[3]);
1155
1156         size = min((size_t)size,
1157                    0x200 - sizeof(struct b43legacy_plcp_hdr6));
1158         b43legacy_write_template_common(dev, probe_resp_data,
1159                                         size, ram_offset,
1160                                         shm_size_offset, rate->hw_value);
1161         kfree(probe_resp_data);
1162 }
1163
1164 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1165 {
1166         struct b43legacy_wl *wl = dev->wl;
1167
1168         if (wl->beacon0_uploaded)
1169                 return;
1170         b43legacy_write_beacon_template(dev, 0x68, 0x18);
1171         /* FIXME: Probe resp upload doesn't really belong here,
1172          *        but we don't use that feature anyway. */
1173         b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1174                                       &__b43legacy_ratetable[3]);
1175         wl->beacon0_uploaded = 1;
1176 }
1177
1178 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1179 {
1180         struct b43legacy_wl *wl = dev->wl;
1181
1182         if (wl->beacon1_uploaded)
1183                 return;
1184         b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1185         wl->beacon1_uploaded = 1;
1186 }
1187
1188 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1189 {
1190         struct b43legacy_wl *wl = dev->wl;
1191         u32 cmd, beacon0_valid, beacon1_valid;
1192
1193         if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1194                 return;
1195
1196         /* This is the bottom half of the asynchronous beacon update. */
1197
1198         /* Ignore interrupt in the future. */
1199         dev->irq_mask &= ~B43legacy_IRQ_BEACON;
1200
1201         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1202         beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1203         beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1204
1205         /* Schedule interrupt manually, if busy. */
1206         if (beacon0_valid && beacon1_valid) {
1207                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1208                 dev->irq_mask |= B43legacy_IRQ_BEACON;
1209                 return;
1210         }
1211
1212         if (unlikely(wl->beacon_templates_virgin)) {
1213                 /* We never uploaded a beacon before.
1214                  * Upload both templates now, but only mark one valid. */
1215                 wl->beacon_templates_virgin = 0;
1216                 b43legacy_upload_beacon0(dev);
1217                 b43legacy_upload_beacon1(dev);
1218                 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1219                 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1220                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1221         } else {
1222                 if (!beacon0_valid) {
1223                         b43legacy_upload_beacon0(dev);
1224                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1225                         cmd |= B43legacy_MACCMD_BEACON0_VALID;
1226                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1227                 } else if (!beacon1_valid) {
1228                         b43legacy_upload_beacon1(dev);
1229                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1230                         cmd |= B43legacy_MACCMD_BEACON1_VALID;
1231                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1232                 }
1233         }
1234 }
1235
1236 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1237 {
1238         struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1239                                          beacon_update_trigger);
1240         struct b43legacy_wldev *dev;
1241
1242         mutex_lock(&wl->mutex);
1243         dev = wl->current_dev;
1244         if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1245                 spin_lock_irq(&wl->irq_lock);
1246                 /* Update beacon right away or defer to IRQ. */
1247                 handle_irq_beacon(dev);
1248                 /* The handler might have updated the IRQ mask. */
1249                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1250                                   dev->irq_mask);
1251                 mmiowb();
1252                 spin_unlock_irq(&wl->irq_lock);
1253         }
1254         mutex_unlock(&wl->mutex);
1255 }
1256
1257 /* Asynchronously update the packet templates in template RAM.
1258  * Locking: Requires wl->irq_lock to be locked. */
1259 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1260 {
1261         struct sk_buff *beacon;
1262         /* This is the top half of the ansynchronous beacon update. The bottom
1263          * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1264          * sending an invalid beacon. This can happen for example, if the
1265          * firmware transmits a beacon while we are updating it. */
1266
1267         /* We could modify the existing beacon and set the aid bit in the TIM
1268          * field, but that would probably require resizing and moving of data
1269          * within the beacon template. Simply request a new beacon and let
1270          * mac80211 do the hard work. */
1271         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1272         if (unlikely(!beacon))
1273                 return;
1274
1275         if (wl->current_beacon)
1276                 dev_kfree_skb_any(wl->current_beacon);
1277         wl->current_beacon = beacon;
1278         wl->beacon0_uploaded = 0;
1279         wl->beacon1_uploaded = 0;
1280         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1281 }
1282
1283 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1284                                      u16 beacon_int)
1285 {
1286         b43legacy_time_lock(dev);
1287         if (dev->dev->id.revision >= 3) {
1288                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1289                                  (beacon_int << 16));
1290                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1291                                  (beacon_int << 10));
1292         } else {
1293                 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1294                 b43legacy_write16(dev, 0x610, beacon_int);
1295         }
1296         b43legacy_time_unlock(dev);
1297         b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1298 }
1299
1300 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1301 {
1302 }
1303
1304 /* Interrupt handler bottom-half */
1305 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1306 {
1307         u32 reason;
1308         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1309         u32 merged_dma_reason = 0;
1310         int i;
1311         unsigned long flags;
1312
1313         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1314
1315         B43legacy_WARN_ON(b43legacy_status(dev) <
1316                           B43legacy_STAT_INITIALIZED);
1317
1318         reason = dev->irq_reason;
1319         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1320                 dma_reason[i] = dev->dma_reason[i];
1321                 merged_dma_reason |= dma_reason[i];
1322         }
1323
1324         if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1325                 b43legacyerr(dev->wl, "MAC transmission error\n");
1326
1327         if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1328                 b43legacyerr(dev->wl, "PHY transmission error\n");
1329                 rmb();
1330                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1331                         b43legacyerr(dev->wl, "Too many PHY TX errors, "
1332                                               "restarting the controller\n");
1333                         b43legacy_controller_restart(dev, "PHY TX errors");
1334                 }
1335         }
1336
1337         if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1338                                           B43legacy_DMAIRQ_NONFATALMASK))) {
1339                 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1340                         b43legacyerr(dev->wl, "Fatal DMA error: "
1341                                "0x%08X, 0x%08X, 0x%08X, "
1342                                "0x%08X, 0x%08X, 0x%08X\n",
1343                                dma_reason[0], dma_reason[1],
1344                                dma_reason[2], dma_reason[3],
1345                                dma_reason[4], dma_reason[5]);
1346                         b43legacy_controller_restart(dev, "DMA error");
1347                         mmiowb();
1348                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1349                         return;
1350                 }
1351                 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1352                         b43legacyerr(dev->wl, "DMA error: "
1353                                "0x%08X, 0x%08X, 0x%08X, "
1354                                "0x%08X, 0x%08X, 0x%08X\n",
1355                                dma_reason[0], dma_reason[1],
1356                                dma_reason[2], dma_reason[3],
1357                                dma_reason[4], dma_reason[5]);
1358         }
1359
1360         if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1361                 handle_irq_ucode_debug(dev);
1362         if (reason & B43legacy_IRQ_TBTT_INDI)
1363                 handle_irq_tbtt_indication(dev);
1364         if (reason & B43legacy_IRQ_ATIM_END)
1365                 handle_irq_atim_end(dev);
1366         if (reason & B43legacy_IRQ_BEACON)
1367                 handle_irq_beacon(dev);
1368         if (reason & B43legacy_IRQ_PMQ)
1369                 handle_irq_pmq(dev);
1370         if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1371                 ;/*TODO*/
1372         if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1373                 handle_irq_noise(dev);
1374
1375         /* Check the DMA reason registers for received data. */
1376         if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1377                 if (b43legacy_using_pio(dev))
1378                         b43legacy_pio_rx(dev->pio.queue0);
1379                 else
1380                         b43legacy_dma_rx(dev->dma.rx_ring0);
1381         }
1382         B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1383         B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1384         if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1385                 if (b43legacy_using_pio(dev))
1386                         b43legacy_pio_rx(dev->pio.queue3);
1387                 else
1388                         b43legacy_dma_rx(dev->dma.rx_ring3);
1389         }
1390         B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1391         B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1392
1393         if (reason & B43legacy_IRQ_TX_OK)
1394                 handle_irq_transmit_status(dev);
1395
1396         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1397         mmiowb();
1398         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1399 }
1400
1401 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1402                                u16 base, int queueidx)
1403 {
1404         u16 rxctl;
1405
1406         rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1407         if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1408                 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1409         else
1410                 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1411 }
1412
1413 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1414 {
1415         if (b43legacy_using_pio(dev) &&
1416             (dev->dev->id.revision < 3) &&
1417             (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1418                 /* Apply a PIO specific workaround to the dma_reasons */
1419                 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1420                 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1421                 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1422                 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1423         }
1424
1425         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1426
1427         b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1428                           dev->dma_reason[0]);
1429         b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1430                           dev->dma_reason[1]);
1431         b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1432                           dev->dma_reason[2]);
1433         b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1434                           dev->dma_reason[3]);
1435         b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1436                           dev->dma_reason[4]);
1437         b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1438                           dev->dma_reason[5]);
1439 }
1440
1441 /* Interrupt handler top-half */
1442 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1443 {
1444         irqreturn_t ret = IRQ_NONE;
1445         struct b43legacy_wldev *dev = dev_id;
1446         u32 reason;
1447
1448         B43legacy_WARN_ON(!dev);
1449
1450         spin_lock(&dev->wl->irq_lock);
1451
1452         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1453                 /* This can only happen on shared IRQ lines. */
1454                 goto out;
1455         reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1456         if (reason == 0xffffffff) /* shared IRQ */
1457                 goto out;
1458         ret = IRQ_HANDLED;
1459         reason &= dev->irq_mask;
1460         if (!reason)
1461                 goto out;
1462
1463         dev->dma_reason[0] = b43legacy_read32(dev,
1464                                               B43legacy_MMIO_DMA0_REASON)
1465                                               & 0x0001DC00;
1466         dev->dma_reason[1] = b43legacy_read32(dev,
1467                                               B43legacy_MMIO_DMA1_REASON)
1468                                               & 0x0000DC00;
1469         dev->dma_reason[2] = b43legacy_read32(dev,
1470                                               B43legacy_MMIO_DMA2_REASON)
1471                                               & 0x0000DC00;
1472         dev->dma_reason[3] = b43legacy_read32(dev,
1473                                               B43legacy_MMIO_DMA3_REASON)
1474                                               & 0x0001DC00;
1475         dev->dma_reason[4] = b43legacy_read32(dev,
1476                                               B43legacy_MMIO_DMA4_REASON)
1477                                               & 0x0000DC00;
1478         dev->dma_reason[5] = b43legacy_read32(dev,
1479                                               B43legacy_MMIO_DMA5_REASON)
1480                                               & 0x0000DC00;
1481
1482         b43legacy_interrupt_ack(dev, reason);
1483         /* Disable all IRQs. They are enabled again in the bottom half. */
1484         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1485         /* Save the reason code and call our bottom half. */
1486         dev->irq_reason = reason;
1487         tasklet_schedule(&dev->isr_tasklet);
1488 out:
1489         mmiowb();
1490         spin_unlock(&dev->wl->irq_lock);
1491
1492         return ret;
1493 }
1494
1495 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1496 {
1497         release_firmware(dev->fw.ucode);
1498         dev->fw.ucode = NULL;
1499         release_firmware(dev->fw.pcm);
1500         dev->fw.pcm = NULL;
1501         release_firmware(dev->fw.initvals);
1502         dev->fw.initvals = NULL;
1503         release_firmware(dev->fw.initvals_band);
1504         dev->fw.initvals_band = NULL;
1505 }
1506
1507 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1508 {
1509         b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1510                      "Drivers/b43#devicefirmware "
1511                      "and download the correct firmware (version 3).\n");
1512 }
1513
1514 static int do_request_fw(struct b43legacy_wldev *dev,
1515                          const char *name,
1516                          const struct firmware **fw)
1517 {
1518         char path[sizeof(modparam_fwpostfix) + 32];
1519         struct b43legacy_fw_header *hdr;
1520         u32 size;
1521         int err;
1522
1523         if (!name)
1524                 return 0;
1525
1526         snprintf(path, ARRAY_SIZE(path),
1527                  "b43legacy%s/%s.fw",
1528                  modparam_fwpostfix, name);
1529         err = request_firmware(fw, path, dev->dev->dev);
1530         if (err) {
1531                 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1532                        "or load failed.\n", path);
1533                 return err;
1534         }
1535         if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1536                 goto err_format;
1537         hdr = (struct b43legacy_fw_header *)((*fw)->data);
1538         switch (hdr->type) {
1539         case B43legacy_FW_TYPE_UCODE:
1540         case B43legacy_FW_TYPE_PCM:
1541                 size = be32_to_cpu(hdr->size);
1542                 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1543                         goto err_format;
1544                 /* fallthrough */
1545         case B43legacy_FW_TYPE_IV:
1546                 if (hdr->ver != 1)
1547                         goto err_format;
1548                 break;
1549         default:
1550                 goto err_format;
1551         }
1552
1553         return err;
1554
1555 err_format:
1556         b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1557         return -EPROTO;
1558 }
1559
1560 static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1561 {
1562         struct b43legacy_firmware *fw = &dev->fw;
1563         const u8 rev = dev->dev->id.revision;
1564         const char *filename;
1565         int err;
1566
1567         /* do dummy read */
1568         ssb_read32(dev->dev, SSB_TMSHIGH);
1569         if (!fw->ucode) {
1570                 if (rev == 2)
1571                         filename = "ucode2";
1572                 else if (rev == 4)
1573                         filename = "ucode4";
1574                 else
1575                         filename = "ucode5";
1576                 err = do_request_fw(dev, filename, &fw->ucode);
1577                 if (err)
1578                         goto err_load;
1579         }
1580         if (!fw->pcm) {
1581                 if (rev < 5)
1582                         filename = "pcm4";
1583                 else
1584                         filename = "pcm5";
1585                 err = do_request_fw(dev, filename, &fw->pcm);
1586                 if (err)
1587                         goto err_load;
1588         }
1589         if (!fw->initvals) {
1590                 switch (dev->phy.type) {
1591                 case B43legacy_PHYTYPE_B:
1592                 case B43legacy_PHYTYPE_G:
1593                         if ((rev >= 5) && (rev <= 10))
1594                                 filename = "b0g0initvals5";
1595                         else if (rev == 2 || rev == 4)
1596                                 filename = "b0g0initvals2";
1597                         else
1598                                 goto err_no_initvals;
1599                         break;
1600                 default:
1601                         goto err_no_initvals;
1602                 }
1603                 err = do_request_fw(dev, filename, &fw->initvals);
1604                 if (err)
1605                         goto err_load;
1606         }
1607         if (!fw->initvals_band) {
1608                 switch (dev->phy.type) {
1609                 case B43legacy_PHYTYPE_B:
1610                 case B43legacy_PHYTYPE_G:
1611                         if ((rev >= 5) && (rev <= 10))
1612                                 filename = "b0g0bsinitvals5";
1613                         else if (rev >= 11)
1614                                 filename = NULL;
1615                         else if (rev == 2 || rev == 4)
1616                                 filename = NULL;
1617                         else
1618                                 goto err_no_initvals;
1619                         break;
1620                 default:
1621                         goto err_no_initvals;
1622                 }
1623                 err = do_request_fw(dev, filename, &fw->initvals_band);
1624                 if (err)
1625                         goto err_load;
1626         }
1627
1628         return 0;
1629
1630 err_load:
1631         b43legacy_print_fw_helptext(dev->wl);
1632         goto error;
1633
1634 err_no_initvals:
1635         err = -ENODEV;
1636         b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1637                "core rev %u\n", dev->phy.type, rev);
1638         goto error;
1639
1640 error:
1641         b43legacy_release_firmware(dev);
1642         return err;
1643 }
1644
1645 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1646 {
1647         struct wiphy *wiphy = dev->wl->hw->wiphy;
1648         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1649         const __be32 *data;
1650         unsigned int i;
1651         unsigned int len;
1652         u16 fwrev;
1653         u16 fwpatch;
1654         u16 fwdate;
1655         u16 fwtime;
1656         u32 tmp, macctl;
1657         int err = 0;
1658
1659         /* Jump the microcode PSM to offset 0 */
1660         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1661         B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1662         macctl |= B43legacy_MACCTL_PSM_JMP0;
1663         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1664         /* Zero out all microcode PSM registers and shared memory. */
1665         for (i = 0; i < 64; i++)
1666                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1667         for (i = 0; i < 4096; i += 2)
1668                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1669
1670         /* Upload Microcode. */
1671         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1672         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1673         b43legacy_shm_control_word(dev,
1674                                    B43legacy_SHM_UCODE |
1675                                    B43legacy_SHM_AUTOINC_W,
1676                                    0x0000);
1677         for (i = 0; i < len; i++) {
1678                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1679                                     be32_to_cpu(data[i]));
1680                 udelay(10);
1681         }
1682
1683         if (dev->fw.pcm) {
1684                 /* Upload PCM data. */
1685                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1686                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1687                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1688                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1689                 /* No need for autoinc bit in SHM_HW */
1690                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1691                 for (i = 0; i < len; i++) {
1692                         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1693                                           be32_to_cpu(data[i]));
1694                         udelay(10);
1695                 }
1696         }
1697
1698         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1699                           B43legacy_IRQ_ALL);
1700
1701         /* Start the microcode PSM */
1702         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1703         macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1704         macctl |= B43legacy_MACCTL_PSM_RUN;
1705         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1706
1707         /* Wait for the microcode to load and respond */
1708         i = 0;
1709         while (1) {
1710                 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1711                 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1712                         break;
1713                 i++;
1714                 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1715                         b43legacyerr(dev->wl, "Microcode not responding\n");
1716                         b43legacy_print_fw_helptext(dev->wl);
1717                         err = -ENODEV;
1718                         goto error;
1719                 }
1720                 msleep_interruptible(50);
1721                 if (signal_pending(current)) {
1722                         err = -EINTR;
1723                         goto error;
1724                 }
1725         }
1726         /* dummy read follows */
1727         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1728
1729         /* Get and check the revisions. */
1730         fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1731                                      B43legacy_SHM_SH_UCODEREV);
1732         fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1733                                        B43legacy_SHM_SH_UCODEPATCH);
1734         fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1735                                       B43legacy_SHM_SH_UCODEDATE);
1736         fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1737                                       B43legacy_SHM_SH_UCODETIME);
1738
1739         if (fwrev > 0x128) {
1740                 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1741                              " Only firmware from binary drivers version 3.x"
1742                              " is supported. You must change your firmware"
1743                              " files.\n");
1744                 b43legacy_print_fw_helptext(dev->wl);
1745                 err = -EOPNOTSUPP;
1746                 goto error;
1747         }
1748         b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1749                       "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1750                       (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1751                       (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1752                       fwtime & 0x1F);
1753
1754         dev->fw.rev = fwrev;
1755         dev->fw.patch = fwpatch;
1756
1757         snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
1758                         dev->fw.rev, dev->fw.patch);
1759         wiphy->hw_version = dev->dev->id.coreid;
1760
1761         return 0;
1762
1763 error:
1764         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1765         macctl &= ~B43legacy_MACCTL_PSM_RUN;
1766         macctl |= B43legacy_MACCTL_PSM_JMP0;
1767         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1768
1769         return err;
1770 }
1771
1772 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1773                                     const struct b43legacy_iv *ivals,
1774                                     size_t count,
1775                                     size_t array_size)
1776 {
1777         const struct b43legacy_iv *iv;
1778         u16 offset;
1779         size_t i;
1780         bool bit32;
1781
1782         BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1783         iv = ivals;
1784         for (i = 0; i < count; i++) {
1785                 if (array_size < sizeof(iv->offset_size))
1786                         goto err_format;
1787                 array_size -= sizeof(iv->offset_size);
1788                 offset = be16_to_cpu(iv->offset_size);
1789                 bit32 = !!(offset & B43legacy_IV_32BIT);
1790                 offset &= B43legacy_IV_OFFSET_MASK;
1791                 if (offset >= 0x1000)
1792                         goto err_format;
1793                 if (bit32) {
1794                         u32 value;
1795
1796                         if (array_size < sizeof(iv->data.d32))
1797                                 goto err_format;
1798                         array_size -= sizeof(iv->data.d32);
1799
1800                         value = get_unaligned_be32(&iv->data.d32);
1801                         b43legacy_write32(dev, offset, value);
1802
1803                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1804                                                         sizeof(__be16) +
1805                                                         sizeof(__be32));
1806                 } else {
1807                         u16 value;
1808
1809                         if (array_size < sizeof(iv->data.d16))
1810                                 goto err_format;
1811                         array_size -= sizeof(iv->data.d16);
1812
1813                         value = be16_to_cpu(iv->data.d16);
1814                         b43legacy_write16(dev, offset, value);
1815
1816                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1817                                                         sizeof(__be16) +
1818                                                         sizeof(__be16));
1819                 }
1820         }
1821         if (array_size)
1822                 goto err_format;
1823
1824         return 0;
1825
1826 err_format:
1827         b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1828         b43legacy_print_fw_helptext(dev->wl);
1829
1830         return -EPROTO;
1831 }
1832
1833 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1834 {
1835         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1836         const struct b43legacy_fw_header *hdr;
1837         struct b43legacy_firmware *fw = &dev->fw;
1838         const struct b43legacy_iv *ivals;
1839         size_t count;
1840         int err;
1841
1842         hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1843         ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1844         count = be32_to_cpu(hdr->size);
1845         err = b43legacy_write_initvals(dev, ivals, count,
1846                                  fw->initvals->size - hdr_len);
1847         if (err)
1848                 goto out;
1849         if (fw->initvals_band) {
1850                 hdr = (const struct b43legacy_fw_header *)
1851                       (fw->initvals_band->data);
1852                 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1853                         + hdr_len);
1854                 count = be32_to_cpu(hdr->size);
1855                 err = b43legacy_write_initvals(dev, ivals, count,
1856                                          fw->initvals_band->size - hdr_len);
1857                 if (err)
1858                         goto out;
1859         }
1860 out:
1861
1862         return err;
1863 }
1864
1865 /* Initialize the GPIOs
1866  * http://bcm-specs.sipsolutions.net/GPIO
1867  */
1868 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1869 {
1870         struct ssb_bus *bus = dev->dev->bus;
1871         struct ssb_device *gpiodev, *pcidev = NULL;
1872         u32 mask;
1873         u32 set;
1874
1875         b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1876                           b43legacy_read32(dev,
1877                           B43legacy_MMIO_MACCTL)
1878                           & 0xFFFF3FFF);
1879
1880         b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1881                           b43legacy_read16(dev,
1882                           B43legacy_MMIO_GPIO_MASK)
1883                           | 0x000F);
1884
1885         mask = 0x0000001F;
1886         set = 0x0000000F;
1887         if (dev->dev->bus->chip_id == 0x4301) {
1888                 mask |= 0x0060;
1889                 set |= 0x0060;
1890         }
1891         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1892                 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1893                                   b43legacy_read16(dev,
1894                                   B43legacy_MMIO_GPIO_MASK)
1895                                   | 0x0200);
1896                 mask |= 0x0200;
1897                 set |= 0x0200;
1898         }
1899         if (dev->dev->id.revision >= 2)
1900                 mask  |= 0x0010; /* FIXME: This is redundant. */
1901
1902 #ifdef CONFIG_SSB_DRIVER_PCICORE
1903         pcidev = bus->pcicore.dev;
1904 #endif
1905         gpiodev = bus->chipco.dev ? : pcidev;
1906         if (!gpiodev)
1907                 return 0;
1908         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1909                     (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1910                      & mask) | set);
1911
1912         return 0;
1913 }
1914
1915 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1916 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1917 {
1918         struct ssb_bus *bus = dev->dev->bus;
1919         struct ssb_device *gpiodev, *pcidev = NULL;
1920
1921 #ifdef CONFIG_SSB_DRIVER_PCICORE
1922         pcidev = bus->pcicore.dev;
1923 #endif
1924         gpiodev = bus->chipco.dev ? : pcidev;
1925         if (!gpiodev)
1926                 return;
1927         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1928 }
1929
1930 /* http://bcm-specs.sipsolutions.net/EnableMac */
1931 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1932 {
1933         dev->mac_suspended--;
1934         B43legacy_WARN_ON(dev->mac_suspended < 0);
1935         B43legacy_WARN_ON(irqs_disabled());
1936         if (dev->mac_suspended == 0) {
1937                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1938                                   b43legacy_read32(dev,
1939                                   B43legacy_MMIO_MACCTL)
1940                                   | B43legacy_MACCTL_ENABLED);
1941                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1942                                   B43legacy_IRQ_MAC_SUSPENDED);
1943                 /* the next two are dummy reads */
1944                 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1945                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1946                 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1947
1948                 /* Re-enable IRQs. */
1949                 spin_lock_irq(&dev->wl->irq_lock);
1950                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1951                                   dev->irq_mask);
1952                 spin_unlock_irq(&dev->wl->irq_lock);
1953         }
1954 }
1955
1956 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1957 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1958 {
1959         int i;
1960         u32 tmp;
1961
1962         might_sleep();
1963         B43legacy_WARN_ON(irqs_disabled());
1964         B43legacy_WARN_ON(dev->mac_suspended < 0);
1965
1966         if (dev->mac_suspended == 0) {
1967                 /* Mask IRQs before suspending MAC. Otherwise
1968                  * the MAC stays busy and won't suspend. */
1969                 spin_lock_irq(&dev->wl->irq_lock);
1970                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1971                 spin_unlock_irq(&dev->wl->irq_lock);
1972                 b43legacy_synchronize_irq(dev);
1973
1974                 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1975                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1976                                   b43legacy_read32(dev,
1977                                   B43legacy_MMIO_MACCTL)
1978                                   & ~B43legacy_MACCTL_ENABLED);
1979                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1980                 for (i = 40; i; i--) {
1981                         tmp = b43legacy_read32(dev,
1982                                                B43legacy_MMIO_GEN_IRQ_REASON);
1983                         if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1984                                 goto out;
1985                         msleep(1);
1986                 }
1987                 b43legacyerr(dev->wl, "MAC suspend failed\n");
1988         }
1989 out:
1990         dev->mac_suspended++;
1991 }
1992
1993 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1994 {
1995         struct b43legacy_wl *wl = dev->wl;
1996         u32 ctl;
1997         u16 cfp_pretbtt;
1998
1999         ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2000         /* Reset status to STA infrastructure mode. */
2001         ctl &= ~B43legacy_MACCTL_AP;
2002         ctl &= ~B43legacy_MACCTL_KEEP_CTL;
2003         ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
2004         ctl &= ~B43legacy_MACCTL_KEEP_BAD;
2005         ctl &= ~B43legacy_MACCTL_PROMISC;
2006         ctl &= ~B43legacy_MACCTL_BEACPROMISC;
2007         ctl |= B43legacy_MACCTL_INFRA;
2008
2009         if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
2010                 ctl |= B43legacy_MACCTL_AP;
2011         else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
2012                 ctl &= ~B43legacy_MACCTL_INFRA;
2013
2014         if (wl->filter_flags & FIF_CONTROL)
2015                 ctl |= B43legacy_MACCTL_KEEP_CTL;
2016         if (wl->filter_flags & FIF_FCSFAIL)
2017                 ctl |= B43legacy_MACCTL_KEEP_BAD;
2018         if (wl->filter_flags & FIF_PLCPFAIL)
2019                 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
2020         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2021                 ctl |= B43legacy_MACCTL_PROMISC;
2022         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2023                 ctl |= B43legacy_MACCTL_BEACPROMISC;
2024
2025         /* Workaround: On old hardware the HW-MAC-address-filter
2026          * doesn't work properly, so always run promisc in filter
2027          * it in software. */
2028         if (dev->dev->id.revision <= 4)
2029                 ctl |= B43legacy_MACCTL_PROMISC;
2030
2031         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2032
2033         cfp_pretbtt = 2;
2034         if ((ctl & B43legacy_MACCTL_INFRA) &&
2035             !(ctl & B43legacy_MACCTL_AP)) {
2036                 if (dev->dev->bus->chip_id == 0x4306 &&
2037                     dev->dev->bus->chip_rev == 3)
2038                         cfp_pretbtt = 100;
2039                 else
2040                         cfp_pretbtt = 50;
2041         }
2042         b43legacy_write16(dev, 0x612, cfp_pretbtt);
2043 }
2044
2045 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2046                                         u16 rate,
2047                                         int is_ofdm)
2048 {
2049         u16 offset;
2050
2051         if (is_ofdm) {
2052                 offset = 0x480;
2053                 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2054         } else {
2055                 offset = 0x4C0;
2056                 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2057         }
2058         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2059                               b43legacy_shm_read16(dev,
2060                               B43legacy_SHM_SHARED, offset));
2061 }
2062
2063 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2064 {
2065         switch (dev->phy.type) {
2066         case B43legacy_PHYTYPE_G:
2067                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2068                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2069                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2070                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2071                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2072                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2073                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2074                 /* fallthrough */
2075         case B43legacy_PHYTYPE_B:
2076                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2077                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2078                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2079                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2080                 break;
2081         default:
2082                 B43legacy_BUG_ON(1);
2083         }
2084 }
2085
2086 /* Set the TX-Antenna for management frames sent by firmware. */
2087 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2088                                           int antenna)
2089 {
2090         u16 ant = 0;
2091         u16 tmp;
2092
2093         switch (antenna) {
2094         case B43legacy_ANTENNA0:
2095                 ant |= B43legacy_TX4_PHY_ANT0;
2096                 break;
2097         case B43legacy_ANTENNA1:
2098                 ant |= B43legacy_TX4_PHY_ANT1;
2099                 break;
2100         case B43legacy_ANTENNA_AUTO:
2101                 ant |= B43legacy_TX4_PHY_ANTLAST;
2102                 break;
2103         default:
2104                 B43legacy_BUG_ON(1);
2105         }
2106
2107         /* FIXME We also need to set the other flags of the PHY control
2108          * field somewhere. */
2109
2110         /* For Beacons */
2111         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2112                                    B43legacy_SHM_SH_BEACPHYCTL);
2113         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2114         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2115                               B43legacy_SHM_SH_BEACPHYCTL, tmp);
2116         /* For ACK/CTS */
2117         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2118                                    B43legacy_SHM_SH_ACKCTSPHYCTL);
2119         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2120         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2121                               B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2122         /* For Probe Resposes */
2123         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2124                                    B43legacy_SHM_SH_PRPHYCTL);
2125         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2126         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2127                               B43legacy_SHM_SH_PRPHYCTL, tmp);
2128 }
2129
2130 /* This is the opposite of b43legacy_chip_init() */
2131 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2132 {
2133         b43legacy_radio_turn_off(dev, 1);
2134         b43legacy_gpio_cleanup(dev);
2135         /* firmware is released later */
2136 }
2137
2138 /* Initialize the chip
2139  * http://bcm-specs.sipsolutions.net/ChipInit
2140  */
2141 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2142 {
2143         struct b43legacy_phy *phy = &dev->phy;
2144         int err;
2145         int tmp;
2146         u32 value32, macctl;
2147         u16 value16;
2148
2149         /* Initialize the MAC control */
2150         macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2151         if (dev->phy.gmode)
2152                 macctl |= B43legacy_MACCTL_GMODE;
2153         macctl |= B43legacy_MACCTL_INFRA;
2154         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2155
2156         err = b43legacy_request_firmware(dev);
2157         if (err)
2158                 goto out;
2159         err = b43legacy_upload_microcode(dev);
2160         if (err)
2161                 goto out; /* firmware is released later */
2162
2163         err = b43legacy_gpio_init(dev);
2164         if (err)
2165                 goto out; /* firmware is released later */
2166
2167         err = b43legacy_upload_initvals(dev);
2168         if (err)
2169                 goto err_gpio_clean;
2170         b43legacy_radio_turn_on(dev);
2171
2172         b43legacy_write16(dev, 0x03E6, 0x0000);
2173         err = b43legacy_phy_init(dev);
2174         if (err)
2175                 goto err_radio_off;
2176
2177         /* Select initial Interference Mitigation. */
2178         tmp = phy->interfmode;
2179         phy->interfmode = B43legacy_INTERFMODE_NONE;
2180         b43legacy_radio_set_interference_mitigation(dev, tmp);
2181
2182         b43legacy_phy_set_antenna_diversity(dev);
2183         b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2184
2185         if (phy->type == B43legacy_PHYTYPE_B) {
2186                 value16 = b43legacy_read16(dev, 0x005E);
2187                 value16 |= 0x0004;
2188                 b43legacy_write16(dev, 0x005E, value16);
2189         }
2190         b43legacy_write32(dev, 0x0100, 0x01000000);
2191         if (dev->dev->id.revision < 5)
2192                 b43legacy_write32(dev, 0x010C, 0x01000000);
2193
2194         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2195         value32 &= ~B43legacy_MACCTL_INFRA;
2196         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2197         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2198         value32 |= B43legacy_MACCTL_INFRA;
2199         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2200
2201         if (b43legacy_using_pio(dev)) {
2202                 b43legacy_write32(dev, 0x0210, 0x00000100);
2203                 b43legacy_write32(dev, 0x0230, 0x00000100);
2204                 b43legacy_write32(dev, 0x0250, 0x00000100);
2205                 b43legacy_write32(dev, 0x0270, 0x00000100);
2206                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2207                                       0x0000);
2208         }
2209
2210         /* Probe Response Timeout value */
2211         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2212         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2213
2214         /* Initially set the wireless operation mode. */
2215         b43legacy_adjust_opmode(dev);
2216
2217         if (dev->dev->id.revision < 3) {
2218                 b43legacy_write16(dev, 0x060E, 0x0000);
2219                 b43legacy_write16(dev, 0x0610, 0x8000);
2220                 b43legacy_write16(dev, 0x0604, 0x0000);
2221                 b43legacy_write16(dev, 0x0606, 0x0200);
2222         } else {
2223                 b43legacy_write32(dev, 0x0188, 0x80000000);
2224                 b43legacy_write32(dev, 0x018C, 0x02000000);
2225         }
2226         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2227         b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2228         b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2229         b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2230         b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2231         b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2232         b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2233
2234         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2235         value32 |= B43legacy_TMSLOW_MACPHYCLKEN;
2236         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2237
2238         b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2239                           dev->dev->bus->chipco.fast_pwrup_delay);
2240
2241         /* PHY TX errors counter. */
2242         atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2243
2244         B43legacy_WARN_ON(err != 0);
2245         b43legacydbg(dev->wl, "Chip initialized\n");
2246 out:
2247         return err;
2248
2249 err_radio_off:
2250         b43legacy_radio_turn_off(dev, 1);
2251 err_gpio_clean:
2252         b43legacy_gpio_cleanup(dev);
2253         goto out;
2254 }
2255
2256 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2257 {
2258         struct b43legacy_phy *phy = &dev->phy;
2259
2260         if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2261                 return;
2262
2263         b43legacy_mac_suspend(dev);
2264         b43legacy_phy_lo_g_measure(dev);
2265         b43legacy_mac_enable(dev);
2266 }
2267
2268 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2269 {
2270         b43legacy_phy_lo_mark_all_unused(dev);
2271         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2272                 b43legacy_mac_suspend(dev);
2273                 b43legacy_calc_nrssi_slope(dev);
2274                 b43legacy_mac_enable(dev);
2275         }
2276 }
2277
2278 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2279 {
2280         /* Update device statistics. */
2281         b43legacy_calculate_link_quality(dev);
2282 }
2283
2284 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2285 {
2286         b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2287
2288         atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2289         wmb();
2290 }
2291
2292 static void do_periodic_work(struct b43legacy_wldev *dev)
2293 {
2294         unsigned int state;
2295
2296         state = dev->periodic_state;
2297         if (state % 8 == 0)
2298                 b43legacy_periodic_every120sec(dev);
2299         if (state % 4 == 0)
2300                 b43legacy_periodic_every60sec(dev);
2301         if (state % 2 == 0)
2302                 b43legacy_periodic_every30sec(dev);
2303         b43legacy_periodic_every15sec(dev);
2304 }
2305
2306 /* Periodic work locking policy:
2307  *      The whole periodic work handler is protected by
2308  *      wl->mutex. If another lock is needed somewhere in the
2309  *      pwork callchain, it's acquired in-place, where it's needed.
2310  */
2311 static void b43legacy_periodic_work_handler(struct work_struct *work)
2312 {
2313         struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2314                                              periodic_work.work);
2315         struct b43legacy_wl *wl = dev->wl;
2316         unsigned long delay;
2317
2318         mutex_lock(&wl->mutex);
2319
2320         if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2321                 goto out;
2322         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2323                 goto out_requeue;
2324
2325         do_periodic_work(dev);
2326
2327         dev->periodic_state++;
2328 out_requeue:
2329         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2330                 delay = msecs_to_jiffies(50);
2331         else
2332                 delay = round_jiffies_relative(HZ * 15);
2333         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2334 out:
2335         mutex_unlock(&wl->mutex);
2336 }
2337
2338 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2339 {
2340         struct delayed_work *work = &dev->periodic_work;
2341
2342         dev->periodic_state = 0;
2343         INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2344         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2345 }
2346
2347 /* Validate access to the chip (SHM) */
2348 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2349 {
2350         u32 value;
2351         u32 shm_backup;
2352
2353         shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2354         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2355         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2356                                  0xAA5555AA)
2357                 goto error;
2358         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2359         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2360                                  0x55AAAA55)
2361                 goto error;
2362         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2363
2364         value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2365         if ((value | B43legacy_MACCTL_GMODE) !=
2366             (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2367                 goto error;
2368
2369         value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2370         if (value)
2371                 goto error;
2372
2373         return 0;
2374 error:
2375         b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2376         return -ENODEV;
2377 }
2378
2379 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2380 {
2381         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2382         B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2383         dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2384                                         0x0056);
2385         /* KTP is a word address, but we address SHM bytewise.
2386          * So multiply by two.
2387          */
2388         dev->ktp *= 2;
2389         if (dev->dev->id.revision >= 5)
2390                 /* Number of RCMTA address slots */
2391                 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2392                                   dev->max_nr_keys - 8);
2393 }
2394
2395 #ifdef CONFIG_B43LEGACY_HWRNG
2396 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2397 {
2398         struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2399         unsigned long flags;
2400
2401         /* Don't take wl->mutex here, as it could deadlock with
2402          * hwrng internal locking. It's not needed to take
2403          * wl->mutex here, anyway. */
2404
2405         spin_lock_irqsave(&wl->irq_lock, flags);
2406         *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2407         spin_unlock_irqrestore(&wl->irq_lock, flags);
2408
2409         return (sizeof(u16));
2410 }
2411 #endif
2412
2413 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2414 {
2415 #ifdef CONFIG_B43LEGACY_HWRNG
2416         if (wl->rng_initialized)
2417                 hwrng_unregister(&wl->rng);
2418 #endif
2419 }
2420
2421 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2422 {
2423         int err = 0;
2424
2425 #ifdef CONFIG_B43LEGACY_HWRNG
2426         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2427                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2428         wl->rng.name = wl->rng_name;
2429         wl->rng.data_read = b43legacy_rng_read;
2430         wl->rng.priv = (unsigned long)wl;
2431         wl->rng_initialized = 1;
2432         err = hwrng_register(&wl->rng);
2433         if (err) {
2434                 wl->rng_initialized = 0;
2435                 b43legacyerr(wl, "Failed to register the random "
2436                        "number generator (%d)\n", err);
2437         }
2438
2439 #endif
2440         return err;
2441 }
2442
2443 static void b43legacy_op_tx(struct ieee80211_hw *hw,
2444                             struct sk_buff *skb)
2445 {
2446         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2447         struct b43legacy_wldev *dev = wl->current_dev;
2448         int err = -ENODEV;
2449         unsigned long flags;
2450
2451         if (unlikely(!dev))
2452                 goto out;
2453         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2454                 goto out;
2455         /* DMA-TX is done without a global lock. */
2456         if (b43legacy_using_pio(dev)) {
2457                 spin_lock_irqsave(&wl->irq_lock, flags);
2458                 err = b43legacy_pio_tx(dev, skb);
2459                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2460         } else
2461                 err = b43legacy_dma_tx(dev, skb);
2462 out:
2463         if (unlikely(err)) {
2464                 /* Drop the packet. */
2465                 dev_kfree_skb_any(skb);
2466         }
2467 }
2468
2469 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw,
2470                                 struct ieee80211_vif *vif, u16 queue,
2471                                 const struct ieee80211_tx_queue_params *params)
2472 {
2473         return 0;
2474 }
2475
2476 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2477                                   struct ieee80211_low_level_stats *stats)
2478 {
2479         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2480         unsigned long flags;
2481
2482         spin_lock_irqsave(&wl->irq_lock, flags);
2483         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2484         spin_unlock_irqrestore(&wl->irq_lock, flags);
2485
2486         return 0;
2487 }
2488
2489 static const char *phymode_to_string(unsigned int phymode)
2490 {
2491         switch (phymode) {
2492         case B43legacy_PHYMODE_B:
2493                 return "B";
2494         case B43legacy_PHYMODE_G:
2495                 return "G";
2496         default:
2497                 B43legacy_BUG_ON(1);
2498         }
2499         return "";
2500 }
2501
2502 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2503                                   unsigned int phymode,
2504                                   struct b43legacy_wldev **dev,
2505                                   bool *gmode)
2506 {
2507         struct b43legacy_wldev *d;
2508
2509         list_for_each_entry(d, &wl->devlist, list) {
2510                 if (d->phy.possible_phymodes & phymode) {
2511                         /* Ok, this device supports the PHY-mode.
2512                          * Set the gmode bit. */
2513                         *gmode = 1;
2514                         *dev = d;
2515
2516                         return 0;
2517                 }
2518         }
2519
2520         return -ESRCH;
2521 }
2522
2523 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2524 {
2525         struct ssb_device *sdev = dev->dev;
2526         u32 tmslow;
2527
2528         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2529         tmslow &= ~B43legacy_TMSLOW_GMODE;
2530         tmslow |= B43legacy_TMSLOW_PHYRESET;
2531         tmslow |= SSB_TMSLOW_FGC;
2532         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2533         msleep(1);
2534
2535         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2536         tmslow &= ~SSB_TMSLOW_FGC;
2537         tmslow |= B43legacy_TMSLOW_PHYRESET;
2538         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2539         msleep(1);
2540 }
2541
2542 /* Expects wl->mutex locked */
2543 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2544                                       unsigned int new_mode)
2545 {
2546         struct b43legacy_wldev *uninitialized_var(up_dev);
2547         struct b43legacy_wldev *down_dev;
2548         int err;
2549         bool gmode = 0;
2550         int prev_status;
2551
2552         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2553         if (err) {
2554                 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2555                        phymode_to_string(new_mode));
2556                 return err;
2557         }
2558         if ((up_dev == wl->current_dev) &&
2559             (!!wl->current_dev->phy.gmode == !!gmode))
2560                 /* This device is already running. */
2561                 return 0;
2562         b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2563                phymode_to_string(new_mode));
2564         down_dev = wl->current_dev;
2565
2566         prev_status = b43legacy_status(down_dev);
2567         /* Shutdown the currently running core. */
2568         if (prev_status >= B43legacy_STAT_STARTED)
2569                 b43legacy_wireless_core_stop(down_dev);
2570         if (prev_status >= B43legacy_STAT_INITIALIZED)
2571                 b43legacy_wireless_core_exit(down_dev);
2572
2573         if (down_dev != up_dev)
2574                 /* We switch to a different core, so we put PHY into
2575                  * RESET on the old core. */
2576                 b43legacy_put_phy_into_reset(down_dev);
2577
2578         /* Now start the new core. */
2579         up_dev->phy.gmode = gmode;
2580         if (prev_status >= B43legacy_STAT_INITIALIZED) {
2581                 err = b43legacy_wireless_core_init(up_dev);
2582                 if (err) {
2583                         b43legacyerr(wl, "Fatal: Could not initialize device"
2584                                      " for newly selected %s-PHY mode\n",
2585                                      phymode_to_string(new_mode));
2586                         goto init_failure;
2587                 }
2588         }
2589         if (prev_status >= B43legacy_STAT_STARTED) {
2590                 err = b43legacy_wireless_core_start(up_dev);
2591                 if (err) {
2592                         b43legacyerr(wl, "Fatal: Coult not start device for "
2593                                "newly selected %s-PHY mode\n",
2594                                phymode_to_string(new_mode));
2595                         b43legacy_wireless_core_exit(up_dev);
2596                         goto init_failure;
2597                 }
2598         }
2599         B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2600
2601         b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2602
2603         wl->current_dev = up_dev;
2604
2605         return 0;
2606 init_failure:
2607         /* Whoops, failed to init the new core. No core is operating now. */
2608         wl->current_dev = NULL;
2609         return err;
2610 }
2611
2612 /* Write the short and long frame retry limit values. */
2613 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2614                                        unsigned int short_retry,
2615                                        unsigned int long_retry)
2616 {
2617         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2618          * the chip-internal counter. */
2619         short_retry = min(short_retry, (unsigned int)0xF);
2620         long_retry = min(long_retry, (unsigned int)0xF);
2621
2622         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2623         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2624 }
2625
2626 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2627                                    u32 changed)
2628 {
2629         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2630         struct b43legacy_wldev *dev;
2631         struct b43legacy_phy *phy;
2632         struct ieee80211_conf *conf = &hw->conf;
2633         unsigned long flags;
2634         unsigned int new_phymode = 0xFFFF;
2635         int antenna_tx;
2636         int err = 0;
2637
2638         antenna_tx = B43legacy_ANTENNA_DEFAULT;
2639
2640         mutex_lock(&wl->mutex);
2641         dev = wl->current_dev;
2642         phy = &dev->phy;
2643
2644         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2645                 b43legacy_set_retry_limits(dev,
2646                                            conf->short_frame_max_tx_count,
2647                                            conf->long_frame_max_tx_count);
2648         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2649         if (!changed)
2650                 goto out_unlock_mutex;
2651
2652         /* Switch the PHY mode (if necessary). */
2653         switch (conf->channel->band) {
2654         case IEEE80211_BAND_2GHZ:
2655                 if (phy->type == B43legacy_PHYTYPE_B)
2656                         new_phymode = B43legacy_PHYMODE_B;
2657                 else
2658                         new_phymode = B43legacy_PHYMODE_G;
2659                 break;
2660         default:
2661                 B43legacy_WARN_ON(1);
2662         }
2663         err = b43legacy_switch_phymode(wl, new_phymode);
2664         if (err)
2665                 goto out_unlock_mutex;
2666
2667         /* Disable IRQs while reconfiguring the device.
2668          * This makes it possible to drop the spinlock throughout
2669          * the reconfiguration process. */
2670         spin_lock_irqsave(&wl->irq_lock, flags);
2671         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2672                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2673                 goto out_unlock_mutex;
2674         }
2675         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2676         spin_unlock_irqrestore(&wl->irq_lock, flags);
2677         b43legacy_synchronize_irq(dev);
2678
2679         /* Switch to the requested channel.
2680          * The firmware takes care of races with the TX handler. */
2681         if (conf->channel->hw_value != phy->channel)
2682                 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2683
2684         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
2685
2686         /* Adjust the desired TX power level. */
2687         if (conf->power_level != 0) {
2688                 if (conf->power_level != phy->power_level) {
2689                         phy->power_level = conf->power_level;
2690                         b43legacy_phy_xmitpower(dev);
2691                 }
2692         }
2693
2694         /* Antennas for RX and management frame TX. */
2695         b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2696
2697         if (wl->radio_enabled != phy->radio_on) {
2698                 if (wl->radio_enabled) {
2699                         b43legacy_radio_turn_on(dev);
2700                         b43legacyinfo(dev->wl, "Radio turned on by software\n");
2701                         if (!dev->radio_hw_enable)
2702                                 b43legacyinfo(dev->wl, "The hardware RF-kill"
2703                                               " button still turns the radio"
2704                                               " physically off. Press the"
2705                                               " button to turn it on.\n");
2706                 } else {
2707                         b43legacy_radio_turn_off(dev, 0);
2708                         b43legacyinfo(dev->wl, "Radio turned off by"
2709                                       " software\n");
2710                 }
2711         }
2712
2713         spin_lock_irqsave(&wl->irq_lock, flags);
2714         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2715         mmiowb();
2716         spin_unlock_irqrestore(&wl->irq_lock, flags);
2717 out_unlock_mutex:
2718         mutex_unlock(&wl->mutex);
2719
2720         return err;
2721 }
2722
2723 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2724 {
2725         struct ieee80211_supported_band *sband =
2726                 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2727         struct ieee80211_rate *rate;
2728         int i;
2729         u16 basic, direct, offset, basic_offset, rateptr;
2730
2731         for (i = 0; i < sband->n_bitrates; i++) {
2732                 rate = &sband->bitrates[i];
2733
2734                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2735                         direct = B43legacy_SHM_SH_CCKDIRECT;
2736                         basic = B43legacy_SHM_SH_CCKBASIC;
2737                         offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2738                         offset &= 0xF;
2739                 } else {
2740                         direct = B43legacy_SHM_SH_OFDMDIRECT;
2741                         basic = B43legacy_SHM_SH_OFDMBASIC;
2742                         offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2743                         offset &= 0xF;
2744                 }
2745
2746                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2747
2748                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2749                         basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2750                         basic_offset &= 0xF;
2751                 } else {
2752                         basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2753                         basic_offset &= 0xF;
2754                 }
2755
2756                 /*
2757                  * Get the pointer that we need to point to
2758                  * from the direct map
2759                  */
2760                 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2761                                                direct + 2 * basic_offset);
2762                 /* and write it to the basic map */
2763                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2764                                       basic + 2 * offset, rateptr);
2765         }
2766 }
2767
2768 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2769                                     struct ieee80211_vif *vif,
2770                                     struct ieee80211_bss_conf *conf,
2771                                     u32 changed)
2772 {
2773         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2774         struct b43legacy_wldev *dev;
2775         unsigned long flags;
2776
2777         mutex_lock(&wl->mutex);
2778         B43legacy_WARN_ON(wl->vif != vif);
2779
2780         dev = wl->current_dev;
2781
2782         /* Disable IRQs while reconfiguring the device.
2783          * This makes it possible to drop the spinlock throughout
2784          * the reconfiguration process. */
2785         spin_lock_irqsave(&wl->irq_lock, flags);
2786         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2787                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2788                 goto out_unlock_mutex;
2789         }
2790         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2791
2792         if (changed & BSS_CHANGED_BSSID) {
2793                 b43legacy_synchronize_irq(dev);
2794
2795                 if (conf->bssid)
2796                         memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2797                 else
2798                         memset(wl->bssid, 0, ETH_ALEN);
2799         }
2800
2801         if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2802                 if (changed & BSS_CHANGED_BEACON &&
2803                     (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2804                      b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2805                         b43legacy_update_templates(wl);
2806
2807                 if (changed & BSS_CHANGED_BSSID)
2808                         b43legacy_write_mac_bssid_templates(dev);
2809         }
2810         spin_unlock_irqrestore(&wl->irq_lock, flags);
2811
2812         b43legacy_mac_suspend(dev);
2813
2814         if (changed & BSS_CHANGED_BEACON_INT &&
2815             (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2816              b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2817                 b43legacy_set_beacon_int(dev, conf->beacon_int);
2818
2819         if (changed & BSS_CHANGED_BASIC_RATES)
2820                 b43legacy_update_basic_rates(dev, conf->basic_rates);
2821
2822         if (changed & BSS_CHANGED_ERP_SLOT) {
2823                 if (conf->use_short_slot)
2824                         b43legacy_short_slot_timing_enable(dev);
2825                 else
2826                         b43legacy_short_slot_timing_disable(dev);
2827         }
2828
2829         b43legacy_mac_enable(dev);
2830
2831         spin_lock_irqsave(&wl->irq_lock, flags);
2832         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2833         /* XXX: why? */
2834         mmiowb();
2835         spin_unlock_irqrestore(&wl->irq_lock, flags);
2836  out_unlock_mutex:
2837         mutex_unlock(&wl->mutex);
2838 }
2839
2840 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2841                                           unsigned int changed,
2842                                           unsigned int *fflags,u64 multicast)
2843 {
2844         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2845         struct b43legacy_wldev *dev = wl->current_dev;
2846         unsigned long flags;
2847
2848         if (!dev) {
2849                 *fflags = 0;
2850                 return;
2851         }
2852
2853         spin_lock_irqsave(&wl->irq_lock, flags);
2854         *fflags &= FIF_PROMISC_IN_BSS |
2855                   FIF_ALLMULTI |
2856                   FIF_FCSFAIL |
2857                   FIF_PLCPFAIL |
2858                   FIF_CONTROL |
2859                   FIF_OTHER_BSS |
2860                   FIF_BCN_PRBRESP_PROMISC;
2861
2862         changed &= FIF_PROMISC_IN_BSS |
2863                    FIF_ALLMULTI |
2864                    FIF_FCSFAIL |
2865                    FIF_PLCPFAIL |
2866                    FIF_CONTROL |
2867                    FIF_OTHER_BSS |
2868                    FIF_BCN_PRBRESP_PROMISC;
2869
2870         wl->filter_flags = *fflags;
2871
2872         if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2873                 b43legacy_adjust_opmode(dev);
2874         spin_unlock_irqrestore(&wl->irq_lock, flags);
2875 }
2876
2877 /* Locking: wl->mutex */
2878 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2879 {
2880         struct b43legacy_wl *wl = dev->wl;
2881         unsigned long flags;
2882
2883         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2884                 return;
2885
2886         /* Disable and sync interrupts. We must do this before than
2887          * setting the status to INITIALIZED, as the interrupt handler
2888          * won't care about IRQs then. */
2889         spin_lock_irqsave(&wl->irq_lock, flags);
2890         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2891         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2892         spin_unlock_irqrestore(&wl->irq_lock, flags);
2893         b43legacy_synchronize_irq(dev);
2894
2895         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2896
2897         mutex_unlock(&wl->mutex);
2898         /* Must unlock as it would otherwise deadlock. No races here.
2899          * Cancel the possibly running self-rearming periodic work. */
2900         cancel_delayed_work_sync(&dev->periodic_work);
2901         mutex_lock(&wl->mutex);
2902
2903         ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2904
2905         b43legacy_mac_suspend(dev);
2906         free_irq(dev->dev->irq, dev);
2907         b43legacydbg(wl, "Wireless interface stopped\n");
2908 }
2909
2910 /* Locking: wl->mutex */
2911 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2912 {
2913         int err;
2914
2915         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2916
2917         drain_txstatus_queue(dev);
2918         err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2919                           IRQF_SHARED, KBUILD_MODNAME, dev);
2920         if (err) {
2921                 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2922                        dev->dev->irq);
2923                 goto out;
2924         }
2925         /* We are ready to run. */
2926         ieee80211_wake_queues(dev->wl->hw);
2927         b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2928
2929         /* Start data flow (TX/RX) */
2930         b43legacy_mac_enable(dev);
2931         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2932
2933         /* Start maintenance work */
2934         b43legacy_periodic_tasks_setup(dev);
2935
2936         b43legacydbg(dev->wl, "Wireless interface started\n");
2937 out:
2938         return err;
2939 }
2940
2941 /* Get PHY and RADIO versioning numbers */
2942 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2943 {
2944         struct b43legacy_phy *phy = &dev->phy;
2945         u32 tmp;
2946         u8 analog_type;
2947         u8 phy_type;
2948         u8 phy_rev;
2949         u16 radio_manuf;
2950         u16 radio_ver;
2951         u16 radio_rev;
2952         int unsupported = 0;
2953
2954         /* Get PHY versioning */
2955         tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2956         analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2957                       >> B43legacy_PHYVER_ANALOG_SHIFT;
2958         phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2959         phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2960         switch (phy_type) {
2961         case B43legacy_PHYTYPE_B:
2962                 if (phy_rev != 2 && phy_rev != 4
2963                     && phy_rev != 6 && phy_rev != 7)
2964                         unsupported = 1;
2965                 break;
2966         case B43legacy_PHYTYPE_G:
2967                 if (phy_rev > 8)
2968                         unsupported = 1;
2969                 break;
2970         default:
2971                 unsupported = 1;
2972         }
2973         if (unsupported) {
2974                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2975                        "(Analog %u, Type %u, Revision %u)\n",
2976                        analog_type, phy_type, phy_rev);
2977                 return -EOPNOTSUPP;
2978         }
2979         b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2980                analog_type, phy_type, phy_rev);
2981
2982
2983         /* Get RADIO versioning */
2984         if (dev->dev->bus->chip_id == 0x4317) {
2985                 if (dev->dev->bus->chip_rev == 0)
2986                         tmp = 0x3205017F;
2987                 else if (dev->dev->bus->chip_rev == 1)
2988                         tmp = 0x4205017F;
2989                 else
2990                         tmp = 0x5205017F;
2991         } else {
2992                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2993                                   B43legacy_RADIOCTL_ID);
2994                 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2995                 tmp <<= 16;
2996                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2997                                   B43legacy_RADIOCTL_ID);
2998                 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2999         }
3000         radio_manuf = (tmp & 0x00000FFF);
3001         radio_ver = (tmp & 0x0FFFF000) >> 12;
3002         radio_rev = (tmp & 0xF0000000) >> 28;
3003         switch (phy_type) {
3004         case B43legacy_PHYTYPE_B:
3005                 if ((radio_ver & 0xFFF0) != 0x2050)
3006                         unsupported = 1;
3007                 break;
3008         case B43legacy_PHYTYPE_G:
3009                 if (radio_ver != 0x2050)
3010                         unsupported = 1;
3011                 break;
3012         default:
3013                 B43legacy_BUG_ON(1);
3014         }
3015         if (unsupported) {
3016                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
3017                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3018                        radio_manuf, radio_ver, radio_rev);
3019                 return -EOPNOTSUPP;
3020         }
3021         b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3022                      " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3023
3024
3025         phy->radio_manuf = radio_manuf;
3026         phy->radio_ver = radio_ver;
3027         phy->radio_rev = radio_rev;
3028
3029         phy->analog = analog_type;
3030         phy->type = phy_type;
3031         phy->rev = phy_rev;
3032
3033         return 0;
3034 }
3035
3036 static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3037                                       struct b43legacy_phy *phy)
3038 {
3039         struct b43legacy_lopair *lo;
3040         int i;
3041
3042         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3043         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3044
3045         /* Assume the radio is enabled. If it's not enabled, the state will
3046          * immediately get fixed on the first periodic work run. */
3047         dev->radio_hw_enable = 1;
3048
3049         phy->savedpctlreg = 0xFFFF;
3050         phy->aci_enable = 0;
3051         phy->aci_wlan_automatic = 0;
3052         phy->aci_hw_rssi = 0;
3053
3054         lo = phy->_lo_pairs;
3055         if (lo)
3056                 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3057                                      B43legacy_LO_COUNT);
3058         phy->max_lb_gain = 0;
3059         phy->trsw_rx_gain = 0;
3060
3061         /* Set default attenuation values. */
3062         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3063         phy->rfatt = b43legacy_default_radio_attenuation(dev);
3064         phy->txctl1 = b43legacy_default_txctl1(dev);
3065         phy->txpwr_offset = 0;
3066
3067         /* NRSSI */
3068         phy->nrssislope = 0;
3069         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3070                 phy->nrssi[i] = -1000;
3071         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3072                 phy->nrssi_lt[i] = i;
3073
3074         phy->lofcal = 0xFFFF;
3075         phy->initval = 0xFFFF;
3076
3077         phy->interfmode = B43legacy_INTERFMODE_NONE;
3078         phy->channel = 0xFF;
3079 }
3080
3081 static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3082 {
3083         /* Flags */
3084         dev->dfq_valid = 0;
3085
3086         /* Stats */
3087         memset(&dev->stats, 0, sizeof(dev->stats));
3088
3089         setup_struct_phy_for_init(dev, &dev->phy);
3090
3091         /* IRQ related flags */
3092         dev->irq_reason = 0;
3093         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3094         dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE;
3095
3096         dev->mac_suspended = 1;
3097
3098         /* Noise calculation context */
3099         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3100 }
3101
3102 static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3103                                           bool idle) {
3104         u16 pu_delay = 1050;
3105
3106         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3107                 pu_delay = 500;
3108         if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3109                 pu_delay = max(pu_delay, (u16)2400);
3110
3111         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3112                               B43legacy_SHM_SH_SPUWKUP, pu_delay);
3113 }
3114
3115 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3116 static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3117 {
3118         u16 pretbtt;
3119
3120         /* The time value is in microseconds. */
3121         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3122                 pretbtt = 2;
3123         else
3124                 pretbtt = 250;
3125         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3126                               B43legacy_SHM_SH_PRETBTT, pretbtt);
3127         b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3128 }
3129
3130 /* Shutdown a wireless core */
3131 /* Locking: wl->mutex */
3132 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3133 {
3134         struct b43legacy_phy *phy = &dev->phy;
3135         u32 macctl;
3136
3137         B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3138         if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3139                 return;
3140         b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3141
3142         /* Stop the microcode PSM. */
3143         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3144         macctl &= ~B43legacy_MACCTL_PSM_RUN;
3145         macctl |= B43legacy_MACCTL_PSM_JMP0;
3146         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3147
3148         b43legacy_leds_exit(dev);
3149         b43legacy_rng_exit(dev->wl);
3150         b43legacy_pio_free(dev);
3151         b43legacy_dma_free(dev);
3152         b43legacy_chip_exit(dev);
3153         b43legacy_radio_turn_off(dev, 1);
3154         b43legacy_switch_analog(dev, 0);
3155         if (phy->dyn_tssi_tbl)
3156                 kfree(phy->tssi2dbm);
3157         kfree(phy->lo_control);
3158         phy->lo_control = NULL;
3159         if (dev->wl->current_beacon) {
3160                 dev_kfree_skb_any(dev->wl->current_beacon);
3161                 dev->wl->current_beacon = NULL;
3162         }
3163
3164         ssb_device_disable(dev->dev, 0);
3165         ssb_bus_may_powerdown(dev->dev->bus);
3166 }
3167
3168 static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3169 {
3170         struct b43legacy_phy *phy = &dev->phy;
3171         int i;
3172
3173         /* Set default attenuation values. */
3174         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3175         phy->rfatt = b43legacy_default_radio_attenuation(dev);
3176         phy->txctl1 = b43legacy_default_txctl1(dev);
3177         phy->txctl2 = 0xFFFF;
3178         phy->txpwr_offset = 0;
3179
3180         /* NRSSI */
3181         phy->nrssislope = 0;
3182         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3183                 phy->nrssi[i] = -1000;
3184         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3185                 phy->nrssi_lt[i] = i;
3186
3187         phy->lofcal = 0xFFFF;
3188         phy->initval = 0xFFFF;
3189
3190         phy->aci_enable = 0;
3191         phy->aci_wlan_automatic = 0;
3192         phy->aci_hw_rssi = 0;
3193
3194         phy->antenna_diversity = 0xFFFF;
3195         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3196         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3197
3198         /* Flags */
3199         phy->calibrated = 0;
3200
3201         if (phy->_lo_pairs)
3202                 memset(phy->_lo_pairs, 0,
3203                        sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3204         memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3205 }
3206
3207 /* Initialize a wireless core */
3208 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3209 {
3210         struct b43legacy_wl *wl = dev->wl;
3211         struct ssb_bus *bus = dev->dev->bus;
3212         struct b43legacy_phy *phy = &dev->phy;
3213         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3214         int err;
3215         u32 hf;
3216         u32 tmp;
3217
3218         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3219
3220         err = ssb_bus_powerup(bus, 0);
3221         if (err)
3222                 goto out;
3223         if (!ssb_device_is_enabled(dev->dev)) {
3224                 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3225                 b43legacy_wireless_core_reset(dev, tmp);
3226         }
3227
3228         if ((phy->type == B43legacy_PHYTYPE_B) ||
3229             (phy->type == B43legacy_PHYTYPE_G)) {
3230                 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3231                                          * B43legacy_LO_COUNT,
3232                                          GFP_KERNEL);
3233                 if (!phy->_lo_pairs)
3234                         return -ENOMEM;
3235         }
3236         setup_struct_wldev_for_init(dev);
3237
3238         err = b43legacy_phy_init_tssi2dbm_table(dev);
3239         if (err)
3240                 goto err_kfree_lo_control;
3241
3242         /* Enable IRQ routing to this device. */
3243         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3244
3245         prepare_phy_data_for_init(dev);
3246         b43legacy_phy_calibrate(dev);
3247         err = b43legacy_chip_init(dev);
3248         if (err)
3249                 goto err_kfree_tssitbl;
3250         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3251                               B43legacy_SHM_SH_WLCOREREV,
3252                               dev->dev->id.revision);
3253         hf = b43legacy_hf_read(dev);
3254         if (phy->type == B43legacy_PHYTYPE_G) {
3255                 hf |= B43legacy_HF_SYMW;
3256                 if (phy->rev == 1)
3257                         hf |= B43legacy_HF_GDCW;
3258                 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
3259                         hf |= B43legacy_HF_OFDMPABOOST;
3260         } else if (phy->type == B43legacy_PHYTYPE_B) {
3261                 hf |= B43legacy_HF_SYMW;
3262                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3263                         hf &= ~B43legacy_HF_GDCW;
3264         }
3265         b43legacy_hf_write(dev, hf);
3266
3267         b43legacy_set_retry_limits(dev,
3268                                    B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3269                                    B43legacy_DEFAULT_LONG_RETRY_LIMIT);
3270
3271         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3272                               0x0044, 3);
3273         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3274                               0x0046, 2);
3275
3276         /* Disable sending probe responses from firmware.
3277          * Setting the MaxTime to one usec will always trigger
3278          * a timeout, so we never send any probe resp.
3279          * A timeout of zero is infinite. */
3280         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3281                               B43legacy_SHM_SH_PRMAXTIME, 1);
3282
3283         b43legacy_rate_memory_init(dev);
3284
3285         /* Minimum Contention Window */
3286         if (phy->type == B43legacy_PHYTYPE_B)
3287                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3288                                       0x0003, 31);
3289         else
3290                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3291                                       0x0003, 15);
3292         /* Maximum Contention Window */
3293         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3294                               0x0004, 1023);
3295
3296         do {
3297                 if (b43legacy_using_pio(dev))
3298                         err = b43legacy_pio_init(dev);
3299                 else {
3300                         err = b43legacy_dma_init(dev);
3301                         if (!err)
3302                                 b43legacy_qos_init(dev);
3303                 }
3304         } while (err == -EAGAIN);
3305         if (err)
3306                 goto err_chip_exit;
3307
3308         b43legacy_set_synth_pu_delay(dev, 1);
3309
3310         ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3311         b43legacy_upload_card_macaddress(dev);
3312         b43legacy_security_init(dev);
3313         b43legacy_rng_init(wl);
3314
3315         ieee80211_wake_queues(dev->wl->hw);
3316         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3317
3318         b43legacy_leds_init(dev);
3319 out:
3320         return err;
3321
3322 err_chip_exit:
3323         b43legacy_chip_exit(dev);
3324 err_kfree_tssitbl:
3325         if (phy->dyn_tssi_tbl)
3326                 kfree(phy->tssi2dbm);
3327 err_kfree_lo_control:
3328         kfree(phy->lo_control);
3329         phy->lo_control = NULL;
3330         ssb_bus_may_powerdown(bus);
3331         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3332         return err;
3333 }
3334
3335 static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
3336                                       struct ieee80211_vif *vif)
3337 {
3338         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3339         struct b43legacy_wldev *dev;
3340         unsigned long flags;
3341         int err = -EOPNOTSUPP;
3342
3343         /* TODO: allow WDS/AP devices to coexist */
3344
3345         if (vif->type != NL80211_IFTYPE_AP &&
3346             vif->type != NL80211_IFTYPE_STATION &&
3347             vif->type != NL80211_IFTYPE_WDS &&
3348             vif->type != NL80211_IFTYPE_ADHOC)
3349                 return -EOPNOTSUPP;
3350
3351         mutex_lock(&wl->mutex);
3352         if (wl->operating)
3353                 goto out_mutex_unlock;
3354
3355         b43legacydbg(wl, "Adding Interface type %d\n", vif->type);
3356
3357         dev = wl->current_dev;
3358         wl->operating = 1;
3359         wl->vif = vif;
3360         wl->if_type = vif->type;
3361         memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
3362
3363         spin_lock_irqsave(&wl->irq_lock, flags);
3364         b43legacy_adjust_opmode(dev);
3365         b43legacy_set_pretbtt(dev);
3366         b43legacy_set_synth_pu_delay(dev, 0);
3367         b43legacy_upload_card_macaddress(dev);
3368         spin_unlock_irqrestore(&wl->irq_lock, flags);
3369
3370         err = 0;
3371  out_mutex_unlock:
3372         mutex_unlock(&wl->mutex);
3373
3374         return err;
3375 }
3376
3377 static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
3378                                           struct ieee80211_vif *vif)
3379 {
3380         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3381         struct b43legacy_wldev *dev = wl->current_dev;
3382         unsigned long flags;
3383
3384         b43legacydbg(wl, "Removing Interface type %d\n", vif->type);
3385
3386         mutex_lock(&wl->mutex);
3387
3388         B43legacy_WARN_ON(!wl->operating);
3389         B43legacy_WARN_ON(wl->vif != vif);
3390         wl->vif = NULL;
3391
3392         wl->operating = 0;
3393
3394         spin_lock_irqsave(&wl->irq_lock, flags);
3395         b43legacy_adjust_opmode(dev);
3396         memset(wl->mac_addr, 0, ETH_ALEN);
3397         b43legacy_upload_card_macaddress(dev);
3398         spin_unlock_irqrestore(&wl->irq_lock, flags);
3399
3400         mutex_unlock(&wl->mutex);
3401 }
3402
3403 static int b43legacy_op_start(struct ieee80211_hw *hw)
3404 {
3405         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3406         struct b43legacy_wldev *dev = wl->current_dev;
3407         int did_init = 0;
3408         int err = 0;
3409
3410         /* Kill all old instance specific information to make sure
3411          * the card won't use it in the short timeframe between start
3412          * and mac80211 reconfiguring it. */
3413         memset(wl->bssid, 0, ETH_ALEN);
3414         memset(wl->mac_addr, 0, ETH_ALEN);
3415         wl->filter_flags = 0;
3416         wl->beacon0_uploaded = 0;
3417         wl->beacon1_uploaded = 0;
3418         wl->beacon_templates_virgin = 1;
3419         wl->radio_enabled = 1;
3420
3421         mutex_lock(&wl->mutex);
3422
3423         if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3424                 err = b43legacy_wireless_core_init(dev);
3425                 if (err)
3426                         goto out_mutex_unlock;
3427                 did_init = 1;
3428         }
3429
3430         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3431                 err = b43legacy_wireless_core_start(dev);
3432                 if (err) {
3433                         if (did_init)
3434                                 b43legacy_wireless_core_exit(dev);
3435                         goto out_mutex_unlock;
3436                 }
3437         }
3438
3439         wiphy_rfkill_start_polling(hw->wiphy);
3440
3441 out_mutex_unlock:
3442         mutex_unlock(&wl->mutex);
3443
3444         return err;
3445 }
3446
3447 static void b43legacy_op_stop(struct ieee80211_hw *hw)
3448 {
3449         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3450         struct b43legacy_wldev *dev = wl->current_dev;
3451